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0005 #include <linux/kernel.h>
0006 #include <linux/module.h>
0007 #include <linux/init.h>
0008 #include <linux/err.h>
0009 #include <linux/of.h>
0010 #include <linux/of_device.h>
0011 #include <linux/regulator/of_regulator.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/reboot.h>
0014 #include <linux/regulator/driver.h>
0015 #include <linux/regulator/machine.h>
0016 #include <linux/regulator/pfuze100.h>
0017 #include <linux/i2c.h>
0018 #include <linux/slab.h>
0019 #include <linux/regmap.h>
0020
0021 #define PFUZE_FLAG_DISABLE_SW BIT(1)
0022
0023 #define PFUZE_NUMREGS 128
0024 #define PFUZE100_VOL_OFFSET 0
0025 #define PFUZE100_STANDBY_OFFSET 1
0026 #define PFUZE100_MODE_OFFSET 3
0027 #define PFUZE100_CONF_OFFSET 4
0028
0029 #define PFUZE100_DEVICEID 0x0
0030 #define PFUZE100_REVID 0x3
0031 #define PFUZE100_FABID 0x4
0032
0033 #define PFUZE100_COINVOL 0x1a
0034 #define PFUZE100_SW1ABVOL 0x20
0035 #define PFUZE100_SW1ABMODE 0x23
0036 #define PFUZE100_SW1CVOL 0x2e
0037 #define PFUZE100_SW1CMODE 0x31
0038 #define PFUZE100_SW2VOL 0x35
0039 #define PFUZE100_SW2MODE 0x38
0040 #define PFUZE100_SW3AVOL 0x3c
0041 #define PFUZE100_SW3AMODE 0x3f
0042 #define PFUZE100_SW3BVOL 0x43
0043 #define PFUZE100_SW3BMODE 0x46
0044 #define PFUZE100_SW4VOL 0x4a
0045 #define PFUZE100_SW4MODE 0x4d
0046 #define PFUZE100_SWBSTCON1 0x66
0047 #define PFUZE100_VREFDDRCON 0x6a
0048 #define PFUZE100_VSNVSVOL 0x6b
0049 #define PFUZE100_VGEN1VOL 0x6c
0050 #define PFUZE100_VGEN2VOL 0x6d
0051 #define PFUZE100_VGEN3VOL 0x6e
0052 #define PFUZE100_VGEN4VOL 0x6f
0053 #define PFUZE100_VGEN5VOL 0x70
0054 #define PFUZE100_VGEN6VOL 0x71
0055
0056 #define PFUZE100_SWxMODE_MASK 0xf
0057 #define PFUZE100_SWxMODE_APS_APS 0x8
0058 #define PFUZE100_SWxMODE_APS_OFF 0x4
0059
0060 #define PFUZE100_VGENxLPWR BIT(6)
0061 #define PFUZE100_VGENxSTBY BIT(5)
0062
0063 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, };
0064
0065 struct pfuze_regulator {
0066 struct regulator_desc desc;
0067 unsigned char stby_reg;
0068 unsigned char stby_mask;
0069 bool sw_reg;
0070 };
0071
0072 struct pfuze_chip {
0073 int chip_id;
0074 int flags;
0075 struct regmap *regmap;
0076 struct device *dev;
0077 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
0078 struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
0079 struct pfuze_regulator *pfuze_regulators;
0080 };
0081
0082 static const int pfuze100_swbst[] = {
0083 5000000, 5050000, 5100000, 5150000,
0084 };
0085
0086 static const int pfuze100_vsnvs[] = {
0087 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
0088 };
0089
0090 static const int pfuze100_coin[] = {
0091 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
0092 };
0093
0094 static const int pfuze3000_sw1a[] = {
0095 700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
0096 900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
0097 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
0098 1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
0099 };
0100
0101 static const int pfuze3000_sw2lo[] = {
0102 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
0103 };
0104
0105 static const int pfuze3000_sw2hi[] = {
0106 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
0107 };
0108
0109 static const struct of_device_id pfuze_dt_ids[] = {
0110 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
0111 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
0112 { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
0113 { .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001},
0114 { }
0115 };
0116 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
0117
0118 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
0119 {
0120 struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
0121 int id = rdev_get_id(rdev);
0122 bool reg_has_ramp_delay;
0123 unsigned int ramp_bits = 0;
0124 int ret;
0125
0126 switch (pfuze100->chip_id) {
0127 case PFUZE3001:
0128
0129 reg_has_ramp_delay = false;
0130 break;
0131 case PFUZE3000:
0132 reg_has_ramp_delay = (id < PFUZE3000_SWBST);
0133 break;
0134 case PFUZE200:
0135 reg_has_ramp_delay = (id < PFUZE200_SWBST);
0136 break;
0137 case PFUZE100:
0138 default:
0139 reg_has_ramp_delay = (id < PFUZE100_SWBST);
0140 break;
0141 }
0142
0143 if (reg_has_ramp_delay) {
0144 if (ramp_delay > 0) {
0145 ramp_delay = 12500 / ramp_delay;
0146 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
0147 }
0148
0149 ret = regmap_update_bits(pfuze100->regmap,
0150 rdev->desc->vsel_reg + 4,
0151 0xc0, ramp_bits << 6);
0152 if (ret < 0)
0153 dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
0154 } else {
0155 ret = -EACCES;
0156 }
0157
0158 return ret;
0159 }
0160
0161 static const struct regulator_ops pfuze100_ldo_regulator_ops = {
0162 .enable = regulator_enable_regmap,
0163 .disable = regulator_disable_regmap,
0164 .is_enabled = regulator_is_enabled_regmap,
0165 .list_voltage = regulator_list_voltage_linear,
0166 .set_voltage_sel = regulator_set_voltage_sel_regmap,
0167 .get_voltage_sel = regulator_get_voltage_sel_regmap,
0168 };
0169
0170 static const struct regulator_ops pfuze100_fixed_regulator_ops = {
0171 .enable = regulator_enable_regmap,
0172 .disable = regulator_disable_regmap,
0173 .is_enabled = regulator_is_enabled_regmap,
0174 .list_voltage = regulator_list_voltage_linear,
0175 };
0176
0177 static const struct regulator_ops pfuze100_sw_regulator_ops = {
0178 .list_voltage = regulator_list_voltage_linear,
0179 .set_voltage_sel = regulator_set_voltage_sel_regmap,
0180 .get_voltage_sel = regulator_get_voltage_sel_regmap,
0181 .set_voltage_time_sel = regulator_set_voltage_time_sel,
0182 .set_ramp_delay = pfuze100_set_ramp_delay,
0183 };
0184
0185 static const struct regulator_ops pfuze100_sw_disable_regulator_ops = {
0186 .enable = regulator_enable_regmap,
0187 .disable = regulator_disable_regmap,
0188 .is_enabled = regulator_is_enabled_regmap,
0189 .list_voltage = regulator_list_voltage_linear,
0190 .set_voltage_sel = regulator_set_voltage_sel_regmap,
0191 .get_voltage_sel = regulator_get_voltage_sel_regmap,
0192 .set_voltage_time_sel = regulator_set_voltage_time_sel,
0193 .set_ramp_delay = pfuze100_set_ramp_delay,
0194 };
0195
0196 static const struct regulator_ops pfuze100_swb_regulator_ops = {
0197 .enable = regulator_enable_regmap,
0198 .disable = regulator_disable_regmap,
0199 .is_enabled = regulator_is_enabled_regmap,
0200 .list_voltage = regulator_list_voltage_table,
0201 .map_voltage = regulator_map_voltage_ascend,
0202 .set_voltage_sel = regulator_set_voltage_sel_regmap,
0203 .get_voltage_sel = regulator_get_voltage_sel_regmap,
0204
0205 };
0206
0207 static const struct regulator_ops pfuze3000_sw_regulator_ops = {
0208 .enable = regulator_enable_regmap,
0209 .disable = regulator_disable_regmap,
0210 .is_enabled = regulator_is_enabled_regmap,
0211 .list_voltage = regulator_list_voltage_table,
0212 .map_voltage = regulator_map_voltage_ascend,
0213 .set_voltage_sel = regulator_set_voltage_sel_regmap,
0214 .get_voltage_sel = regulator_get_voltage_sel_regmap,
0215 .set_voltage_time_sel = regulator_set_voltage_time_sel,
0216 .set_ramp_delay = pfuze100_set_ramp_delay,
0217
0218 };
0219
0220 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
0221 [_chip ## _ ## _name] = { \
0222 .desc = { \
0223 .name = #_name, \
0224 .n_voltages = 1, \
0225 .ops = &pfuze100_fixed_regulator_ops, \
0226 .type = REGULATOR_VOLTAGE, \
0227 .id = _chip ## _ ## _name, \
0228 .owner = THIS_MODULE, \
0229 .min_uV = (voltage), \
0230 .enable_reg = (base), \
0231 .enable_mask = 0x10, \
0232 }, \
0233 }
0234
0235 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
0236 [_chip ## _ ## _name] = { \
0237 .desc = { \
0238 .name = #_name,\
0239 .n_voltages = ((max) - (min)) / (step) + 1, \
0240 .ops = &pfuze100_sw_regulator_ops, \
0241 .type = REGULATOR_VOLTAGE, \
0242 .id = _chip ## _ ## _name, \
0243 .owner = THIS_MODULE, \
0244 .min_uV = (min), \
0245 .uV_step = (step), \
0246 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
0247 .vsel_mask = 0x3f, \
0248 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
0249 .enable_mask = 0xf, \
0250 }, \
0251 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
0252 .stby_mask = 0x3f, \
0253 .sw_reg = true, \
0254 }
0255
0256 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
0257 [_chip ## _ ## _name] = { \
0258 .desc = { \
0259 .name = #_name, \
0260 .n_voltages = ARRAY_SIZE(voltages), \
0261 .ops = &pfuze100_swb_regulator_ops, \
0262 .type = REGULATOR_VOLTAGE, \
0263 .id = _chip ## _ ## _name, \
0264 .owner = THIS_MODULE, \
0265 .volt_table = voltages, \
0266 .vsel_reg = (base), \
0267 .vsel_mask = (mask), \
0268 .enable_reg = (base), \
0269 .enable_mask = 0x48, \
0270 }, \
0271 }
0272
0273 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
0274 [_chip ## _ ## _name] = { \
0275 .desc = { \
0276 .name = #_name, \
0277 .n_voltages = ((max) - (min)) / (step) + 1, \
0278 .ops = &pfuze100_ldo_regulator_ops, \
0279 .type = REGULATOR_VOLTAGE, \
0280 .id = _chip ## _ ## _name, \
0281 .owner = THIS_MODULE, \
0282 .min_uV = (min), \
0283 .uV_step = (step), \
0284 .vsel_reg = (base), \
0285 .vsel_mask = 0xf, \
0286 .enable_reg = (base), \
0287 .enable_mask = 0x10, \
0288 }, \
0289 .stby_reg = (base), \
0290 .stby_mask = 0x20, \
0291 }
0292
0293 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \
0294 [_chip ## _ ## _name] = { \
0295 .desc = { \
0296 .name = #_name, \
0297 .n_voltages = ARRAY_SIZE(voltages), \
0298 .ops = &pfuze100_swb_regulator_ops, \
0299 .type = REGULATOR_VOLTAGE, \
0300 .id = _chip ## _ ## _name, \
0301 .owner = THIS_MODULE, \
0302 .volt_table = voltages, \
0303 .vsel_reg = (base), \
0304 .vsel_mask = (mask), \
0305 .enable_reg = (base), \
0306 .enable_mask = 0x8, \
0307 }, \
0308 }
0309
0310 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
0311 .desc = { \
0312 .name = #_name, \
0313 .n_voltages = ((max) - (min)) / (step) + 1, \
0314 .ops = &pfuze100_ldo_regulator_ops, \
0315 .type = REGULATOR_VOLTAGE, \
0316 .id = _chip ## _ ## _name, \
0317 .owner = THIS_MODULE, \
0318 .min_uV = (min), \
0319 .uV_step = (step), \
0320 .vsel_reg = (base), \
0321 .vsel_mask = 0x3, \
0322 .enable_reg = (base), \
0323 .enable_mask = 0x10, \
0324 }, \
0325 .stby_reg = (base), \
0326 .stby_mask = 0x20, \
0327 }
0328
0329
0330 #define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages) \
0331 [_chip ## _ ## _name] = { \
0332 .desc = { \
0333 .name = #_name, \
0334 .n_voltages = ARRAY_SIZE(voltages), \
0335 .ops = &pfuze3000_sw_regulator_ops, \
0336 .type = REGULATOR_VOLTAGE, \
0337 .id = _chip ## _ ## _name, \
0338 .owner = THIS_MODULE, \
0339 .volt_table = voltages, \
0340 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
0341 .vsel_mask = (mask), \
0342 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
0343 .enable_mask = 0xf, \
0344 .enable_val = 0x8, \
0345 .enable_time = 500, \
0346 }, \
0347 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
0348 .stby_mask = (mask), \
0349 .sw_reg = true, \
0350 }
0351
0352 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
0353 .desc = { \
0354 .name = #_name,\
0355 .n_voltages = ((max) - (min)) / (step) + 1, \
0356 .ops = &pfuze100_sw_regulator_ops, \
0357 .type = REGULATOR_VOLTAGE, \
0358 .id = _chip ## _ ## _name, \
0359 .owner = THIS_MODULE, \
0360 .min_uV = (min), \
0361 .uV_step = (step), \
0362 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
0363 .vsel_mask = 0xf, \
0364 }, \
0365 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
0366 .stby_mask = 0xf, \
0367 }
0368
0369
0370 static struct pfuze_regulator pfuze100_regulators[] = {
0371 PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
0372 PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
0373 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
0374 PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
0375 PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
0376 PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
0377 PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
0378 PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
0379 PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
0380 PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
0381 PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
0382 PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
0383 PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
0384 PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
0385 PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
0386 PFUZE100_COIN_REG(PFUZE100, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
0387 };
0388
0389 static struct pfuze_regulator pfuze200_regulators[] = {
0390 PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
0391 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
0392 PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
0393 PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
0394 PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
0395 PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
0396 PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
0397 PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
0398 PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
0399 PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
0400 PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
0401 PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
0402 PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
0403 PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
0404 };
0405
0406 static struct pfuze_regulator pfuze3000_regulators[] = {
0407 PFUZE3000_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
0408 PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
0409 PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
0410 PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
0411 PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
0412 PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
0413 PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
0414 PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
0415 PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
0416 PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
0417 PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
0418 PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
0419 PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
0420 };
0421
0422 static struct pfuze_regulator pfuze3001_regulators[] = {
0423 PFUZE3000_SW_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
0424 PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
0425 PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
0426 PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
0427 PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
0428 PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
0429 PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
0430 PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
0431 PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
0432 PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
0433 };
0434
0435
0436 static struct of_regulator_match pfuze100_matches[] = {
0437 { .name = "sw1ab", },
0438 { .name = "sw1c", },
0439 { .name = "sw2", },
0440 { .name = "sw3a", },
0441 { .name = "sw3b", },
0442 { .name = "sw4", },
0443 { .name = "swbst", },
0444 { .name = "vsnvs", },
0445 { .name = "vrefddr", },
0446 { .name = "vgen1", },
0447 { .name = "vgen2", },
0448 { .name = "vgen3", },
0449 { .name = "vgen4", },
0450 { .name = "vgen5", },
0451 { .name = "vgen6", },
0452 { .name = "coin", },
0453 };
0454
0455
0456 static struct of_regulator_match pfuze200_matches[] = {
0457
0458 { .name = "sw1ab", },
0459 { .name = "sw2", },
0460 { .name = "sw3a", },
0461 { .name = "sw3b", },
0462 { .name = "swbst", },
0463 { .name = "vsnvs", },
0464 { .name = "vrefddr", },
0465 { .name = "vgen1", },
0466 { .name = "vgen2", },
0467 { .name = "vgen3", },
0468 { .name = "vgen4", },
0469 { .name = "vgen5", },
0470 { .name = "vgen6", },
0471 { .name = "coin", },
0472 };
0473
0474
0475 static struct of_regulator_match pfuze3000_matches[] = {
0476
0477 { .name = "sw1a", },
0478 { .name = "sw1b", },
0479 { .name = "sw2", },
0480 { .name = "sw3", },
0481 { .name = "swbst", },
0482 { .name = "vsnvs", },
0483 { .name = "vrefddr", },
0484 { .name = "vldo1", },
0485 { .name = "vldo2", },
0486 { .name = "vccsd", },
0487 { .name = "v33", },
0488 { .name = "vldo3", },
0489 { .name = "vldo4", },
0490 };
0491
0492
0493 static struct of_regulator_match pfuze3001_matches[] = {
0494
0495 { .name = "sw1", },
0496 { .name = "sw2", },
0497 { .name = "sw3", },
0498 { .name = "vsnvs", },
0499 { .name = "vldo1", },
0500 { .name = "vldo2", },
0501 { .name = "vccsd", },
0502 { .name = "v33", },
0503 { .name = "vldo3", },
0504 { .name = "vldo4", },
0505 };
0506
0507 static struct of_regulator_match *pfuze_matches;
0508
0509 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
0510 {
0511 struct device *dev = chip->dev;
0512 struct device_node *np, *parent;
0513 int ret;
0514
0515 np = of_node_get(dev->of_node);
0516 if (!np)
0517 return -EINVAL;
0518
0519 if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw"))
0520 chip->flags |= PFUZE_FLAG_DISABLE_SW;
0521
0522 parent = of_get_child_by_name(np, "regulators");
0523 if (!parent) {
0524 dev_err(dev, "regulators node not found\n");
0525 of_node_put(np);
0526 return -EINVAL;
0527 }
0528
0529 switch (chip->chip_id) {
0530 case PFUZE3001:
0531 pfuze_matches = pfuze3001_matches;
0532 ret = of_regulator_match(dev, parent, pfuze3001_matches,
0533 ARRAY_SIZE(pfuze3001_matches));
0534 break;
0535 case PFUZE3000:
0536 pfuze_matches = pfuze3000_matches;
0537 ret = of_regulator_match(dev, parent, pfuze3000_matches,
0538 ARRAY_SIZE(pfuze3000_matches));
0539 break;
0540 case PFUZE200:
0541 pfuze_matches = pfuze200_matches;
0542 ret = of_regulator_match(dev, parent, pfuze200_matches,
0543 ARRAY_SIZE(pfuze200_matches));
0544 break;
0545
0546 case PFUZE100:
0547 default:
0548 pfuze_matches = pfuze100_matches;
0549 ret = of_regulator_match(dev, parent, pfuze100_matches,
0550 ARRAY_SIZE(pfuze100_matches));
0551 break;
0552 }
0553
0554 of_node_put(parent);
0555 of_node_put(np);
0556 if (ret < 0) {
0557 dev_err(dev, "Error parsing regulator init data: %d\n",
0558 ret);
0559 return ret;
0560 }
0561
0562 return 0;
0563 }
0564
0565 static inline struct regulator_init_data *match_init_data(int index)
0566 {
0567 return pfuze_matches[index].init_data;
0568 }
0569
0570 static inline struct device_node *match_of_node(int index)
0571 {
0572 return pfuze_matches[index].of_node;
0573 }
0574
0575 static int pfuze_power_off_prepare(struct sys_off_data *data)
0576 {
0577 struct pfuze_chip *syspm_pfuze_chip = data->cb_data;
0578
0579 dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off");
0580
0581
0582 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE,
0583 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
0584 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE,
0585 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
0586 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE,
0587 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
0588 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE,
0589 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
0590 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE,
0591 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
0592 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE,
0593 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
0594
0595 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL,
0596 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
0597 PFUZE100_VGENxSTBY);
0598 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL,
0599 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
0600 PFUZE100_VGENxSTBY);
0601 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL,
0602 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
0603 PFUZE100_VGENxSTBY);
0604 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL,
0605 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
0606 PFUZE100_VGENxSTBY);
0607 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL,
0608 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
0609 PFUZE100_VGENxSTBY);
0610 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL,
0611 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
0612 PFUZE100_VGENxSTBY);
0613
0614 return NOTIFY_DONE;
0615 }
0616
0617 static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip)
0618 {
0619 int err;
0620
0621 if (pfuze_chip->chip_id != PFUZE100) {
0622 dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n");
0623 return -ENODEV;
0624 }
0625
0626 err = devm_register_sys_off_handler(pfuze_chip->dev,
0627 SYS_OFF_MODE_POWER_OFF_PREPARE,
0628 SYS_OFF_PRIO_DEFAULT,
0629 pfuze_power_off_prepare,
0630 pfuze_chip);
0631 if (err) {
0632 dev_err(pfuze_chip->dev, "failed to register sys-off handler: %d\n",
0633 err);
0634 return err;
0635 }
0636
0637 return 0;
0638 }
0639
0640 static int pfuze_identify(struct pfuze_chip *pfuze_chip)
0641 {
0642 unsigned int value;
0643 int ret;
0644
0645 ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
0646 if (ret)
0647 return ret;
0648
0649 if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
0650
0651
0652
0653
0654 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
0655 } else if ((value & 0x0f) != pfuze_chip->chip_id &&
0656 (value & 0xf0) >> 4 != pfuze_chip->chip_id &&
0657 (value != pfuze_chip->chip_id)) {
0658
0659 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
0660 return -ENODEV;
0661 }
0662
0663 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
0664 if (ret)
0665 return ret;
0666 dev_info(pfuze_chip->dev,
0667 "Full layer: %x, Metal layer: %x\n",
0668 (value & 0xf0) >> 4, value & 0x0f);
0669
0670 ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
0671 if (ret)
0672 return ret;
0673 dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
0674 (value & 0xc) >> 2, value & 0x3);
0675
0676 return 0;
0677 }
0678
0679 static const struct regmap_config pfuze_regmap_config = {
0680 .reg_bits = 8,
0681 .val_bits = 8,
0682 .max_register = PFUZE_NUMREGS - 1,
0683 .cache_type = REGCACHE_RBTREE,
0684 };
0685
0686 static int pfuze100_regulator_probe(struct i2c_client *client,
0687 const struct i2c_device_id *id)
0688 {
0689 struct pfuze_chip *pfuze_chip;
0690 struct regulator_config config = { };
0691 int i, ret;
0692 const struct of_device_id *match;
0693 u32 regulator_num;
0694 u32 sw_check_start, sw_check_end, sw_hi = 0x40;
0695
0696 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
0697 GFP_KERNEL);
0698 if (!pfuze_chip)
0699 return -ENOMEM;
0700
0701 if (client->dev.of_node) {
0702 match = of_match_device(of_match_ptr(pfuze_dt_ids),
0703 &client->dev);
0704 if (!match) {
0705 dev_err(&client->dev, "Error: No device match found\n");
0706 return -ENODEV;
0707 }
0708 pfuze_chip->chip_id = (int)(long)match->data;
0709 } else if (id) {
0710 pfuze_chip->chip_id = id->driver_data;
0711 } else {
0712 dev_err(&client->dev, "No dts match or id table match found\n");
0713 return -ENODEV;
0714 }
0715
0716 i2c_set_clientdata(client, pfuze_chip);
0717 pfuze_chip->dev = &client->dev;
0718
0719 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
0720 if (IS_ERR(pfuze_chip->regmap)) {
0721 ret = PTR_ERR(pfuze_chip->regmap);
0722 dev_err(&client->dev,
0723 "regmap allocation failed with err %d\n", ret);
0724 return ret;
0725 }
0726
0727 ret = pfuze_identify(pfuze_chip);
0728 if (ret) {
0729 dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
0730 return ret;
0731 }
0732
0733
0734 switch (pfuze_chip->chip_id) {
0735 case PFUZE3001:
0736 pfuze_chip->pfuze_regulators = pfuze3001_regulators;
0737 regulator_num = ARRAY_SIZE(pfuze3001_regulators);
0738 sw_check_start = PFUZE3001_SW2;
0739 sw_check_end = PFUZE3001_SW2;
0740 sw_hi = 1 << 3;
0741 break;
0742 case PFUZE3000:
0743 pfuze_chip->pfuze_regulators = pfuze3000_regulators;
0744 regulator_num = ARRAY_SIZE(pfuze3000_regulators);
0745 sw_check_start = PFUZE3000_SW2;
0746 sw_check_end = PFUZE3000_SW2;
0747 sw_hi = 1 << 3;
0748 break;
0749 case PFUZE200:
0750 pfuze_chip->pfuze_regulators = pfuze200_regulators;
0751 regulator_num = ARRAY_SIZE(pfuze200_regulators);
0752 sw_check_start = PFUZE200_SW2;
0753 sw_check_end = PFUZE200_SW3B;
0754 break;
0755 case PFUZE100:
0756 default:
0757 pfuze_chip->pfuze_regulators = pfuze100_regulators;
0758 regulator_num = ARRAY_SIZE(pfuze100_regulators);
0759 sw_check_start = PFUZE100_SW2;
0760 sw_check_end = PFUZE100_SW4;
0761 break;
0762 }
0763 dev_info(&client->dev, "pfuze%s found.\n",
0764 (pfuze_chip->chip_id == PFUZE100) ? "100" :
0765 (((pfuze_chip->chip_id == PFUZE200) ? "200" :
0766 ((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001"))));
0767
0768 memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
0769 regulator_num * sizeof(struct pfuze_regulator));
0770
0771 ret = pfuze_parse_regulators_dt(pfuze_chip);
0772 if (ret)
0773 return ret;
0774
0775 for (i = 0; i < regulator_num; i++) {
0776 struct regulator_init_data *init_data;
0777 struct regulator_desc *desc;
0778 int val;
0779
0780 desc = &pfuze_chip->regulator_descs[i].desc;
0781
0782 init_data = match_init_data(i);
0783
0784
0785 if (i >= sw_check_start && i <= sw_check_end) {
0786 ret = regmap_read(pfuze_chip->regmap,
0787 desc->vsel_reg, &val);
0788 if (ret) {
0789 dev_err(&client->dev, "Fails to read from the register.\n");
0790 return ret;
0791 }
0792
0793 if (val & sw_hi) {
0794 if (pfuze_chip->chip_id == PFUZE3000 ||
0795 pfuze_chip->chip_id == PFUZE3001) {
0796 desc->volt_table = pfuze3000_sw2hi;
0797 desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
0798 } else {
0799 desc->min_uV = 800000;
0800 desc->uV_step = 50000;
0801 desc->n_voltages = 51;
0802 }
0803 }
0804 }
0805
0806
0807
0808
0809
0810
0811
0812 if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) {
0813 if (pfuze_chip->chip_id == PFUZE100 ||
0814 pfuze_chip->chip_id == PFUZE200) {
0815 if (pfuze_chip->regulator_descs[i].sw_reg) {
0816 desc->ops = &pfuze100_sw_disable_regulator_ops;
0817 desc->enable_val = 0x8;
0818 desc->disable_val = 0x0;
0819 desc->enable_time = 500;
0820 }
0821 }
0822 }
0823
0824 config.dev = &client->dev;
0825 config.init_data = init_data;
0826 config.driver_data = pfuze_chip;
0827 config.of_node = match_of_node(i);
0828
0829 pfuze_chip->regulators[i] =
0830 devm_regulator_register(&client->dev, desc, &config);
0831 if (IS_ERR(pfuze_chip->regulators[i])) {
0832 dev_err(&client->dev, "register regulator%s failed\n",
0833 pfuze_chip->pfuze_regulators[i].desc.name);
0834 return PTR_ERR(pfuze_chip->regulators[i]);
0835 }
0836 }
0837
0838 if (of_property_read_bool(client->dev.of_node,
0839 "fsl,pmic-stby-poweroff"))
0840 return pfuze_power_off_prepare_init(pfuze_chip);
0841
0842 return 0;
0843 }
0844
0845 static struct i2c_driver pfuze_driver = {
0846 .driver = {
0847 .name = "pfuze100-regulator",
0848 .of_match_table = pfuze_dt_ids,
0849 },
0850 .probe = pfuze100_regulator_probe,
0851 };
0852 module_i2c_driver(pfuze_driver);
0853
0854 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
0855 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC");
0856 MODULE_LICENSE("GPL v2");
