0001
0002
0003
0004
0005
0006 #include <linux/module.h>
0007 #include <linux/of.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/regmap.h>
0010 #include <linux/mfd/mt6397/core.h>
0011 #include <linux/mfd/mt6397/registers.h>
0012 #include <linux/regulator/driver.h>
0013 #include <linux/regulator/machine.h>
0014 #include <linux/regulator/mt6397-regulator.h>
0015 #include <linux/regulator/of_regulator.h>
0016 #include <dt-bindings/regulator/mediatek,mt6397-regulator.h>
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027 struct mt6397_regulator_info {
0028 struct regulator_desc desc;
0029 u32 qi;
0030 u32 vselon_reg;
0031 u32 vselctrl_reg;
0032 u32 vselctrl_mask;
0033 u32 modeset_reg;
0034 u32 modeset_mask;
0035 };
0036
0037 #define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
0038 vosel, vosel_mask, voselon, vosel_ctrl, _modeset_reg, \
0039 _modeset_shift) \
0040 [MT6397_ID_##vreg] = { \
0041 .desc = { \
0042 .name = #vreg, \
0043 .of_match = of_match_ptr(match), \
0044 .ops = &mt6397_volt_range_ops, \
0045 .type = REGULATOR_VOLTAGE, \
0046 .id = MT6397_ID_##vreg, \
0047 .owner = THIS_MODULE, \
0048 .n_voltages = (max - min)/step + 1, \
0049 .linear_ranges = volt_ranges, \
0050 .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
0051 .vsel_reg = vosel, \
0052 .vsel_mask = vosel_mask, \
0053 .enable_reg = enreg, \
0054 .enable_mask = BIT(0), \
0055 .of_map_mode = mt6397_map_mode, \
0056 }, \
0057 .qi = BIT(13), \
0058 .vselon_reg = voselon, \
0059 .vselctrl_reg = vosel_ctrl, \
0060 .vselctrl_mask = BIT(1), \
0061 .modeset_reg = _modeset_reg, \
0062 .modeset_mask = BIT(_modeset_shift), \
0063 }
0064
0065 #define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
0066 vosel_mask) \
0067 [MT6397_ID_##vreg] = { \
0068 .desc = { \
0069 .name = #vreg, \
0070 .of_match = of_match_ptr(match), \
0071 .ops = &mt6397_volt_table_ops, \
0072 .type = REGULATOR_VOLTAGE, \
0073 .id = MT6397_ID_##vreg, \
0074 .owner = THIS_MODULE, \
0075 .n_voltages = ARRAY_SIZE(ldo_volt_table), \
0076 .volt_table = ldo_volt_table, \
0077 .vsel_reg = vosel, \
0078 .vsel_mask = vosel_mask, \
0079 .enable_reg = enreg, \
0080 .enable_mask = BIT(enbit), \
0081 }, \
0082 .qi = BIT(15), \
0083 }
0084
0085 #define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \
0086 [MT6397_ID_##vreg] = { \
0087 .desc = { \
0088 .name = #vreg, \
0089 .of_match = of_match_ptr(match), \
0090 .ops = &mt6397_volt_fixed_ops, \
0091 .type = REGULATOR_VOLTAGE, \
0092 .id = MT6397_ID_##vreg, \
0093 .owner = THIS_MODULE, \
0094 .n_voltages = 1, \
0095 .enable_reg = enreg, \
0096 .enable_mask = BIT(enbit), \
0097 .min_uV = volt, \
0098 }, \
0099 .qi = BIT(15), \
0100 }
0101
0102 static const struct linear_range buck_volt_range1[] = {
0103 REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),
0104 };
0105
0106 static const struct linear_range buck_volt_range2[] = {
0107 REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250),
0108 };
0109
0110 static const struct linear_range buck_volt_range3[] = {
0111 REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000),
0112 };
0113
0114 static const unsigned int ldo_volt_table1[] = {
0115 1500000, 1800000, 2500000, 2800000,
0116 };
0117
0118 static const unsigned int ldo_volt_table2[] = {
0119 1800000, 3300000,
0120 };
0121
0122 static const unsigned int ldo_volt_table3[] = {
0123 3000000, 3300000,
0124 };
0125
0126 static const unsigned int ldo_volt_table4[] = {
0127 1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
0128 };
0129
0130 static const unsigned int ldo_volt_table5[] = {
0131 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
0132 };
0133
0134 static const unsigned int ldo_volt_table5_v2[] = {
0135 1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
0136 };
0137
0138 static const unsigned int ldo_volt_table6[] = {
0139 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000,
0140 };
0141
0142 static const unsigned int ldo_volt_table7[] = {
0143 1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000,
0144 };
0145
0146 static unsigned int mt6397_map_mode(unsigned int mode)
0147 {
0148 switch (mode) {
0149 case MT6397_BUCK_MODE_AUTO:
0150 return REGULATOR_MODE_NORMAL;
0151 case MT6397_BUCK_MODE_FORCE_PWM:
0152 return REGULATOR_MODE_FAST;
0153 default:
0154 return REGULATOR_MODE_INVALID;
0155 }
0156 }
0157
0158 static int mt6397_regulator_set_mode(struct regulator_dev *rdev,
0159 unsigned int mode)
0160 {
0161 struct mt6397_regulator_info *info = rdev_get_drvdata(rdev);
0162 int ret, val;
0163
0164 switch (mode) {
0165 case REGULATOR_MODE_FAST:
0166 val = MT6397_BUCK_MODE_FORCE_PWM;
0167 break;
0168 case REGULATOR_MODE_NORMAL:
0169 val = MT6397_BUCK_MODE_AUTO;
0170 break;
0171 default:
0172 ret = -EINVAL;
0173 goto err_mode;
0174 }
0175
0176 dev_dbg(&rdev->dev, "mt6397 buck set_mode %#x, %#x, %#x\n",
0177 info->modeset_reg, info->modeset_mask, val);
0178
0179 val <<= ffs(info->modeset_mask) - 1;
0180
0181 ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
0182 info->modeset_mask, val);
0183 err_mode:
0184 if (ret != 0) {
0185 dev_err(&rdev->dev,
0186 "Failed to set mt6397 buck mode: %d\n", ret);
0187 return ret;
0188 }
0189
0190 return 0;
0191 }
0192
0193 static unsigned int mt6397_regulator_get_mode(struct regulator_dev *rdev)
0194 {
0195 struct mt6397_regulator_info *info = rdev_get_drvdata(rdev);
0196 int ret, regval;
0197
0198 ret = regmap_read(rdev->regmap, info->modeset_reg, ®val);
0199 if (ret != 0) {
0200 dev_err(&rdev->dev,
0201 "Failed to get mt6397 buck mode: %d\n", ret);
0202 return ret;
0203 }
0204
0205 regval &= info->modeset_mask;
0206 regval >>= ffs(info->modeset_mask) - 1;
0207
0208 switch (regval) {
0209 case MT6397_BUCK_MODE_AUTO:
0210 return REGULATOR_MODE_NORMAL;
0211 case MT6397_BUCK_MODE_FORCE_PWM:
0212 return REGULATOR_MODE_FAST;
0213 default:
0214 return -EINVAL;
0215 }
0216 }
0217
0218 static int mt6397_get_status(struct regulator_dev *rdev)
0219 {
0220 int ret;
0221 u32 regval;
0222 struct mt6397_regulator_info *info = rdev_get_drvdata(rdev);
0223
0224 ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val);
0225 if (ret != 0) {
0226 dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
0227 return ret;
0228 }
0229
0230 return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
0231 }
0232
0233 static const struct regulator_ops mt6397_volt_range_ops = {
0234 .list_voltage = regulator_list_voltage_linear_range,
0235 .map_voltage = regulator_map_voltage_linear_range,
0236 .set_voltage_sel = regulator_set_voltage_sel_regmap,
0237 .get_voltage_sel = regulator_get_voltage_sel_regmap,
0238 .set_voltage_time_sel = regulator_set_voltage_time_sel,
0239 .enable = regulator_enable_regmap,
0240 .disable = regulator_disable_regmap,
0241 .is_enabled = regulator_is_enabled_regmap,
0242 .get_status = mt6397_get_status,
0243 .set_mode = mt6397_regulator_set_mode,
0244 .get_mode = mt6397_regulator_get_mode,
0245 };
0246
0247 static const struct regulator_ops mt6397_volt_table_ops = {
0248 .list_voltage = regulator_list_voltage_table,
0249 .map_voltage = regulator_map_voltage_iterate,
0250 .set_voltage_sel = regulator_set_voltage_sel_regmap,
0251 .get_voltage_sel = regulator_get_voltage_sel_regmap,
0252 .set_voltage_time_sel = regulator_set_voltage_time_sel,
0253 .enable = regulator_enable_regmap,
0254 .disable = regulator_disable_regmap,
0255 .is_enabled = regulator_is_enabled_regmap,
0256 .get_status = mt6397_get_status,
0257 };
0258
0259 static const struct regulator_ops mt6397_volt_fixed_ops = {
0260 .list_voltage = regulator_list_voltage_linear,
0261 .enable = regulator_enable_regmap,
0262 .disable = regulator_disable_regmap,
0263 .is_enabled = regulator_is_enabled_regmap,
0264 .get_status = mt6397_get_status,
0265 };
0266
0267
0268 static struct mt6397_regulator_info mt6397_regulators[] = {
0269 MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250,
0270 buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f,
0271 MT6397_VCA15_CON10, MT6397_VCA15_CON5, MT6397_VCA15_CON2, 11),
0272 MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250,
0273 buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f,
0274 MT6397_VPCA7_CON10, MT6397_VPCA7_CON5, MT6397_VPCA7_CON2, 8),
0275 MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250,
0276 buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9,
0277 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5,
0278 MT6397_VSRMCA15_CON2, 8),
0279 MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250,
0280 buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9,
0281 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5,
0282 MT6397_VSRMCA7_CON2, 8),
0283 MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250,
0284 buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f,
0285 MT6397_VCORE_CON10, MT6397_VCORE_CON5, MT6397_VCORE_CON2, 8),
0286 MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1,
0287 MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f,
0288 MT6397_VGPU_CON10, MT6397_VGPU_CON5, MT6397_VGPU_CON2, 8),
0289 MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2,
0290 MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f,
0291 MT6397_VDRM_CON10, MT6397_VDRM_CON5, MT6397_VDRM_CON2, 8),
0292 MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000,
0293 buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f,
0294 MT6397_VIO18_CON10, MT6397_VIO18_CON5, MT6397_VIO18_CON2, 8),
0295 MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000),
0296 MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000),
0297 MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1,
0298 MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0),
0299 MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000),
0300 MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000),
0301 MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2,
0302 MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10),
0303 MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3,
0304 MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80),
0305 MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3,
0306 MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10),
0307 MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4,
0308 MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0),
0309 MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5,
0310 MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0),
0311 MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5,
0312 MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0),
0313 MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5,
0314 MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0),
0315 MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6,
0316 MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0),
0317 MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5,
0318 MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0),
0319 MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7,
0320 MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00),
0321 };
0322
0323 static int mt6397_set_buck_vosel_reg(struct platform_device *pdev)
0324 {
0325 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
0326 int i;
0327 u32 regval;
0328
0329 for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
0330 if (mt6397_regulators[i].vselctrl_reg) {
0331 if (regmap_read(mt6397->regmap,
0332 mt6397_regulators[i].vselctrl_reg,
0333 ®val) < 0) {
0334 dev_err(&pdev->dev,
0335 "Failed to read buck ctrl\n");
0336 return -EIO;
0337 }
0338
0339 if (regval & mt6397_regulators[i].vselctrl_mask) {
0340 mt6397_regulators[i].desc.vsel_reg =
0341 mt6397_regulators[i].vselon_reg;
0342 }
0343 }
0344 }
0345
0346 return 0;
0347 }
0348
0349 static int mt6397_regulator_probe(struct platform_device *pdev)
0350 {
0351 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
0352 struct regulator_config config = {};
0353 struct regulator_dev *rdev;
0354 int i;
0355 u32 reg_value, version;
0356
0357
0358 if (mt6397_set_buck_vosel_reg(pdev))
0359 return -EIO;
0360
0361
0362 if (regmap_read(mt6397->regmap, MT6397_CID, ®_value) < 0) {
0363 dev_err(&pdev->dev, "Failed to read Chip ID\n");
0364 return -EIO;
0365 }
0366 dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
0367
0368 version = (reg_value & 0xFF);
0369 switch (version) {
0370 case MT6397_REGULATOR_ID91:
0371 mt6397_regulators[MT6397_ID_VGP2].desc.volt_table =
0372 ldo_volt_table5_v2;
0373 break;
0374 default:
0375 break;
0376 }
0377
0378 for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
0379 config.dev = &pdev->dev;
0380 config.driver_data = &mt6397_regulators[i];
0381 config.regmap = mt6397->regmap;
0382 rdev = devm_regulator_register(&pdev->dev,
0383 &mt6397_regulators[i].desc, &config);
0384 if (IS_ERR(rdev)) {
0385 dev_err(&pdev->dev, "failed to register %s\n",
0386 mt6397_regulators[i].desc.name);
0387 return PTR_ERR(rdev);
0388 }
0389 }
0390
0391 return 0;
0392 }
0393
0394 static const struct platform_device_id mt6397_platform_ids[] = {
0395 {"mt6397-regulator", 0},
0396 { },
0397 };
0398 MODULE_DEVICE_TABLE(platform, mt6397_platform_ids);
0399
0400 static const struct of_device_id mt6397_of_match[] = {
0401 { .compatible = "mediatek,mt6397-regulator", },
0402 { },
0403 };
0404 MODULE_DEVICE_TABLE(of, mt6397_of_match);
0405
0406 static struct platform_driver mt6397_regulator_driver = {
0407 .driver = {
0408 .name = "mt6397-regulator",
0409 .of_match_table = of_match_ptr(mt6397_of_match),
0410 },
0411 .probe = mt6397_regulator_probe,
0412 .id_table = mt6397_platform_ids,
0413 };
0414
0415 module_platform_driver(mt6397_regulator_driver);
0416
0417 MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>");
0418 MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC");
0419 MODULE_LICENSE("GPL");