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0005 #include <linux/mfd/mt6358/registers.h>
0006 #include <linux/mfd/mt6397/core.h>
0007 #include <linux/module.h>
0008 #include <linux/of.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/regmap.h>
0011 #include <linux/regulator/driver.h>
0012 #include <linux/regulator/machine.h>
0013 #include <linux/regulator/mt6358-regulator.h>
0014 #include <linux/regulator/of_regulator.h>
0015
0016 #define MT6358_BUCK_MODE_AUTO 0
0017 #define MT6358_BUCK_MODE_FORCE_PWM 1
0018
0019
0020
0021
0022
0023
0024
0025 struct mt6358_regulator_info {
0026 struct regulator_desc desc;
0027 u32 status_reg;
0028 u32 qi;
0029 const u32 *index_table;
0030 unsigned int n_table;
0031 u32 da_vsel_reg;
0032 u32 da_vsel_mask;
0033 u32 modeset_reg;
0034 u32 modeset_mask;
0035 };
0036
0037 #define MT6358_BUCK(match, vreg, min, max, step, \
0038 volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \
0039 _modeset_reg, _modeset_shift) \
0040 [MT6358_ID_##vreg] = { \
0041 .desc = { \
0042 .name = #vreg, \
0043 .of_match = of_match_ptr(match), \
0044 .ops = &mt6358_volt_range_ops, \
0045 .type = REGULATOR_VOLTAGE, \
0046 .id = MT6358_ID_##vreg, \
0047 .owner = THIS_MODULE, \
0048 .n_voltages = ((max) - (min)) / (step) + 1, \
0049 .linear_ranges = volt_ranges, \
0050 .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
0051 .vsel_reg = MT6358_BUCK_##vreg##_ELR0, \
0052 .vsel_mask = vosel_mask, \
0053 .enable_reg = MT6358_BUCK_##vreg##_CON0, \
0054 .enable_mask = BIT(0), \
0055 .of_map_mode = mt6358_map_mode, \
0056 }, \
0057 .status_reg = MT6358_BUCK_##vreg##_DBG1, \
0058 .qi = BIT(0), \
0059 .da_vsel_reg = _da_vsel_reg, \
0060 .da_vsel_mask = _da_vsel_mask, \
0061 .modeset_reg = _modeset_reg, \
0062 .modeset_mask = BIT(_modeset_shift), \
0063 }
0064
0065 #define MT6358_LDO(match, vreg, ldo_volt_table, \
0066 ldo_index_table, enreg, enbit, vosel, \
0067 vosel_mask) \
0068 [MT6358_ID_##vreg] = { \
0069 .desc = { \
0070 .name = #vreg, \
0071 .of_match = of_match_ptr(match), \
0072 .ops = &mt6358_volt_table_ops, \
0073 .type = REGULATOR_VOLTAGE, \
0074 .id = MT6358_ID_##vreg, \
0075 .owner = THIS_MODULE, \
0076 .n_voltages = ARRAY_SIZE(ldo_volt_table), \
0077 .volt_table = ldo_volt_table, \
0078 .vsel_reg = vosel, \
0079 .vsel_mask = vosel_mask, \
0080 .enable_reg = enreg, \
0081 .enable_mask = BIT(enbit), \
0082 }, \
0083 .status_reg = MT6358_LDO_##vreg##_CON1, \
0084 .qi = BIT(15), \
0085 .index_table = ldo_index_table, \
0086 .n_table = ARRAY_SIZE(ldo_index_table), \
0087 }
0088
0089 #define MT6358_LDO1(match, vreg, min, max, step, \
0090 volt_ranges, _da_vsel_reg, _da_vsel_mask, \
0091 vosel, vosel_mask) \
0092 [MT6358_ID_##vreg] = { \
0093 .desc = { \
0094 .name = #vreg, \
0095 .of_match = of_match_ptr(match), \
0096 .ops = &mt6358_volt_range_ops, \
0097 .type = REGULATOR_VOLTAGE, \
0098 .id = MT6358_ID_##vreg, \
0099 .owner = THIS_MODULE, \
0100 .n_voltages = ((max) - (min)) / (step) + 1, \
0101 .linear_ranges = volt_ranges, \
0102 .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
0103 .vsel_reg = vosel, \
0104 .vsel_mask = vosel_mask, \
0105 .enable_reg = MT6358_LDO_##vreg##_CON0, \
0106 .enable_mask = BIT(0), \
0107 }, \
0108 .da_vsel_reg = _da_vsel_reg, \
0109 .da_vsel_mask = _da_vsel_mask, \
0110 .status_reg = MT6358_LDO_##vreg##_DBG1, \
0111 .qi = BIT(0), \
0112 }
0113
0114 #define MT6358_REG_FIXED(match, vreg, \
0115 enreg, enbit, volt) \
0116 [MT6358_ID_##vreg] = { \
0117 .desc = { \
0118 .name = #vreg, \
0119 .of_match = of_match_ptr(match), \
0120 .ops = &mt6358_volt_fixed_ops, \
0121 .type = REGULATOR_VOLTAGE, \
0122 .id = MT6358_ID_##vreg, \
0123 .owner = THIS_MODULE, \
0124 .n_voltages = 1, \
0125 .enable_reg = enreg, \
0126 .enable_mask = BIT(enbit), \
0127 .min_uV = volt, \
0128 }, \
0129 .status_reg = MT6358_LDO_##vreg##_CON1, \
0130 .qi = BIT(15), \
0131 }
0132
0133 #define MT6366_BUCK(match, vreg, min, max, step, \
0134 volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \
0135 _modeset_reg, _modeset_shift) \
0136 [MT6366_ID_##vreg] = { \
0137 .desc = { \
0138 .name = #vreg, \
0139 .of_match = of_match_ptr(match), \
0140 .ops = &mt6358_volt_range_ops, \
0141 .type = REGULATOR_VOLTAGE, \
0142 .id = MT6366_ID_##vreg, \
0143 .owner = THIS_MODULE, \
0144 .n_voltages = ((max) - (min)) / (step) + 1, \
0145 .linear_ranges = volt_ranges, \
0146 .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
0147 .vsel_reg = MT6358_BUCK_##vreg##_ELR0, \
0148 .vsel_mask = vosel_mask, \
0149 .enable_reg = MT6358_BUCK_##vreg##_CON0, \
0150 .enable_mask = BIT(0), \
0151 .of_map_mode = mt6358_map_mode, \
0152 }, \
0153 .status_reg = MT6358_BUCK_##vreg##_DBG1, \
0154 .qi = BIT(0), \
0155 .da_vsel_reg = _da_vsel_reg, \
0156 .da_vsel_mask = _da_vsel_mask, \
0157 .modeset_reg = _modeset_reg, \
0158 .modeset_mask = BIT(_modeset_shift), \
0159 }
0160
0161 #define MT6366_LDO(match, vreg, ldo_volt_table, \
0162 ldo_index_table, enreg, enbit, vosel, \
0163 vosel_mask) \
0164 [MT6366_ID_##vreg] = { \
0165 .desc = { \
0166 .name = #vreg, \
0167 .of_match = of_match_ptr(match), \
0168 .ops = &mt6358_volt_table_ops, \
0169 .type = REGULATOR_VOLTAGE, \
0170 .id = MT6366_ID_##vreg, \
0171 .owner = THIS_MODULE, \
0172 .n_voltages = ARRAY_SIZE(ldo_volt_table), \
0173 .volt_table = ldo_volt_table, \
0174 .vsel_reg = vosel, \
0175 .vsel_mask = vosel_mask, \
0176 .enable_reg = enreg, \
0177 .enable_mask = BIT(enbit), \
0178 }, \
0179 .status_reg = MT6358_LDO_##vreg##_CON1, \
0180 .qi = BIT(15), \
0181 .index_table = ldo_index_table, \
0182 .n_table = ARRAY_SIZE(ldo_index_table), \
0183 }
0184
0185 #define MT6366_LDO1(match, vreg, min, max, step, \
0186 volt_ranges, _da_vsel_reg, _da_vsel_mask, \
0187 vosel, vosel_mask) \
0188 [MT6366_ID_##vreg] = { \
0189 .desc = { \
0190 .name = #vreg, \
0191 .of_match = of_match_ptr(match), \
0192 .ops = &mt6358_volt_range_ops, \
0193 .type = REGULATOR_VOLTAGE, \
0194 .id = MT6366_ID_##vreg, \
0195 .owner = THIS_MODULE, \
0196 .n_voltages = ((max) - (min)) / (step) + 1, \
0197 .linear_ranges = volt_ranges, \
0198 .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
0199 .vsel_reg = vosel, \
0200 .vsel_mask = vosel_mask, \
0201 .enable_reg = MT6358_LDO_##vreg##_CON0, \
0202 .enable_mask = BIT(0), \
0203 }, \
0204 .da_vsel_reg = _da_vsel_reg, \
0205 .da_vsel_mask = _da_vsel_mask, \
0206 .status_reg = MT6358_LDO_##vreg##_DBG1, \
0207 .qi = BIT(0), \
0208 }
0209
0210 #define MT6366_REG_FIXED(match, vreg, \
0211 enreg, enbit, volt) \
0212 [MT6366_ID_##vreg] = { \
0213 .desc = { \
0214 .name = #vreg, \
0215 .of_match = of_match_ptr(match), \
0216 .ops = &mt6358_volt_fixed_ops, \
0217 .type = REGULATOR_VOLTAGE, \
0218 .id = MT6366_ID_##vreg, \
0219 .owner = THIS_MODULE, \
0220 .n_voltages = 1, \
0221 .enable_reg = enreg, \
0222 .enable_mask = BIT(enbit), \
0223 .min_uV = volt, \
0224 }, \
0225 .status_reg = MT6358_LDO_##vreg##_CON1, \
0226 .qi = BIT(15), \
0227 }
0228
0229 static const struct linear_range buck_volt_range1[] = {
0230 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
0231 };
0232
0233 static const struct linear_range buck_volt_range2[] = {
0234 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
0235 };
0236
0237 static const struct linear_range buck_volt_range3[] = {
0238 REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
0239 };
0240
0241 static const struct linear_range buck_volt_range4[] = {
0242 REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
0243 };
0244
0245 static const unsigned int vdram2_voltages[] = {
0246 600000, 1800000,
0247 };
0248
0249 static const unsigned int vsim_voltages[] = {
0250 1700000, 1800000, 2700000, 3000000, 3100000,
0251 };
0252
0253 static const unsigned int vibr_voltages[] = {
0254 1200000, 1300000, 1500000, 1800000,
0255 2000000, 2800000, 3000000, 3300000,
0256 };
0257
0258 static const unsigned int vusb_voltages[] = {
0259 3000000, 3100000,
0260 };
0261
0262 static const unsigned int vcamd_voltages[] = {
0263 900000, 1000000, 1100000, 1200000,
0264 1300000, 1500000, 1800000,
0265 };
0266
0267 static const unsigned int vefuse_voltages[] = {
0268 1700000, 1800000, 1900000,
0269 };
0270
0271 static const unsigned int vmch_vemc_voltages[] = {
0272 2900000, 3000000, 3300000,
0273 };
0274
0275 static const unsigned int vcama_voltages[] = {
0276 1800000, 2500000, 2700000,
0277 2800000, 2900000, 3000000,
0278 };
0279
0280 static const unsigned int vcn33_bt_wifi_voltages[] = {
0281 3300000, 3400000, 3500000,
0282 };
0283
0284 static const unsigned int vmc_voltages[] = {
0285 1800000, 2900000, 3000000, 3300000,
0286 };
0287
0288 static const unsigned int vldo28_voltages[] = {
0289 2800000, 3000000,
0290 };
0291
0292 static const u32 vdram2_idx[] = {
0293 0, 12,
0294 };
0295
0296 static const u32 vsim_idx[] = {
0297 3, 4, 8, 11, 12,
0298 };
0299
0300 static const u32 vibr_idx[] = {
0301 0, 1, 2, 4, 5, 9, 11, 13,
0302 };
0303
0304 static const u32 vusb_idx[] = {
0305 3, 4,
0306 };
0307
0308 static const u32 vcamd_idx[] = {
0309 3, 4, 5, 6, 7, 9, 12,
0310 };
0311
0312 static const u32 vefuse_idx[] = {
0313 11, 12, 13,
0314 };
0315
0316 static const u32 vmch_vemc_idx[] = {
0317 2, 3, 5,
0318 };
0319
0320 static const u32 vcama_idx[] = {
0321 0, 7, 9, 10, 11, 12,
0322 };
0323
0324 static const u32 vcn33_bt_wifi_idx[] = {
0325 1, 2, 3,
0326 };
0327
0328 static const u32 vmc_idx[] = {
0329 4, 10, 11, 13,
0330 };
0331
0332 static const u32 vldo28_idx[] = {
0333 1, 3,
0334 };
0335
0336 static unsigned int mt6358_map_mode(unsigned int mode)
0337 {
0338 return mode == MT6358_BUCK_MODE_AUTO ?
0339 REGULATOR_MODE_NORMAL : REGULATOR_MODE_FAST;
0340 }
0341
0342 static int mt6358_set_voltage_sel(struct regulator_dev *rdev,
0343 unsigned int selector)
0344 {
0345 int idx, ret;
0346 const u32 *pvol;
0347 struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
0348
0349 pvol = info->index_table;
0350
0351 idx = pvol[selector];
0352 idx <<= ffs(info->desc.vsel_mask) - 1;
0353 ret = regmap_update_bits(rdev->regmap, info->desc.vsel_reg,
0354 info->desc.vsel_mask, idx);
0355
0356 return ret;
0357 }
0358
0359 static int mt6358_get_voltage_sel(struct regulator_dev *rdev)
0360 {
0361 int idx, ret;
0362 u32 selector;
0363 struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
0364 const u32 *pvol;
0365
0366 ret = regmap_read(rdev->regmap, info->desc.vsel_reg, &selector);
0367 if (ret != 0) {
0368 dev_info(&rdev->dev,
0369 "Failed to get mt6358 %s vsel reg: %d\n",
0370 info->desc.name, ret);
0371 return ret;
0372 }
0373
0374 selector = (selector & info->desc.vsel_mask) >>
0375 (ffs(info->desc.vsel_mask) - 1);
0376 pvol = info->index_table;
0377 for (idx = 0; idx < info->desc.n_voltages; idx++) {
0378 if (pvol[idx] == selector)
0379 return idx;
0380 }
0381
0382 return -EINVAL;
0383 }
0384
0385 static int mt6358_get_buck_voltage_sel(struct regulator_dev *rdev)
0386 {
0387 int ret, regval;
0388 struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
0389
0390 ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val);
0391 if (ret != 0) {
0392 dev_err(&rdev->dev,
0393 "Failed to get mt6358 Buck %s vsel reg: %d\n",
0394 info->desc.name, ret);
0395 return ret;
0396 }
0397
0398 ret = (regval & info->da_vsel_mask) >> (ffs(info->da_vsel_mask) - 1);
0399
0400 return ret;
0401 }
0402
0403 static int mt6358_get_status(struct regulator_dev *rdev)
0404 {
0405 int ret;
0406 u32 regval;
0407 struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
0408
0409 ret = regmap_read(rdev->regmap, info->status_reg, ®val);
0410 if (ret != 0) {
0411 dev_info(&rdev->dev, "Failed to get enable reg: %d\n", ret);
0412 return ret;
0413 }
0414
0415 return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
0416 }
0417
0418 static int mt6358_regulator_set_mode(struct regulator_dev *rdev,
0419 unsigned int mode)
0420 {
0421 struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
0422 int val;
0423
0424 switch (mode) {
0425 case REGULATOR_MODE_FAST:
0426 val = MT6358_BUCK_MODE_FORCE_PWM;
0427 break;
0428 case REGULATOR_MODE_NORMAL:
0429 val = MT6358_BUCK_MODE_AUTO;
0430 break;
0431 default:
0432 return -EINVAL;
0433 }
0434
0435 dev_dbg(&rdev->dev, "mt6358 buck set_mode %#x, %#x, %#x\n",
0436 info->modeset_reg, info->modeset_mask, val);
0437
0438 val <<= ffs(info->modeset_mask) - 1;
0439
0440 return regmap_update_bits(rdev->regmap, info->modeset_reg,
0441 info->modeset_mask, val);
0442 }
0443
0444 static unsigned int mt6358_regulator_get_mode(struct regulator_dev *rdev)
0445 {
0446 struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
0447 int ret, regval;
0448
0449 ret = regmap_read(rdev->regmap, info->modeset_reg, ®val);
0450 if (ret != 0) {
0451 dev_err(&rdev->dev,
0452 "Failed to get mt6358 buck mode: %d\n", ret);
0453 return ret;
0454 }
0455
0456 switch ((regval & info->modeset_mask) >> (ffs(info->modeset_mask) - 1)) {
0457 case MT6358_BUCK_MODE_AUTO:
0458 return REGULATOR_MODE_NORMAL;
0459 case MT6358_BUCK_MODE_FORCE_PWM:
0460 return REGULATOR_MODE_FAST;
0461 default:
0462 return -EINVAL;
0463 }
0464 }
0465
0466 static const struct regulator_ops mt6358_volt_range_ops = {
0467 .list_voltage = regulator_list_voltage_linear_range,
0468 .map_voltage = regulator_map_voltage_linear_range,
0469 .set_voltage_sel = regulator_set_voltage_sel_regmap,
0470 .get_voltage_sel = mt6358_get_buck_voltage_sel,
0471 .set_voltage_time_sel = regulator_set_voltage_time_sel,
0472 .enable = regulator_enable_regmap,
0473 .disable = regulator_disable_regmap,
0474 .is_enabled = regulator_is_enabled_regmap,
0475 .get_status = mt6358_get_status,
0476 .set_mode = mt6358_regulator_set_mode,
0477 .get_mode = mt6358_regulator_get_mode,
0478 };
0479
0480 static const struct regulator_ops mt6358_volt_table_ops = {
0481 .list_voltage = regulator_list_voltage_table,
0482 .map_voltage = regulator_map_voltage_iterate,
0483 .set_voltage_sel = mt6358_set_voltage_sel,
0484 .get_voltage_sel = mt6358_get_voltage_sel,
0485 .set_voltage_time_sel = regulator_set_voltage_time_sel,
0486 .enable = regulator_enable_regmap,
0487 .disable = regulator_disable_regmap,
0488 .is_enabled = regulator_is_enabled_regmap,
0489 .get_status = mt6358_get_status,
0490 };
0491
0492 static const struct regulator_ops mt6358_volt_fixed_ops = {
0493 .list_voltage = regulator_list_voltage_linear,
0494 .enable = regulator_enable_regmap,
0495 .disable = regulator_disable_regmap,
0496 .is_enabled = regulator_is_enabled_regmap,
0497 .get_status = mt6358_get_status,
0498 };
0499
0500
0501 static struct mt6358_regulator_info mt6358_regulators[] = {
0502 MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
0503 buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
0504 MT6358_VDRAM1_ANA_CON0, 8),
0505 MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
0506 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
0507 MT6358_VCORE_VGPU_ANA_CON0, 1),
0508 MT6358_BUCK("buck_vcore_sshub", VCORE_SSHUB, 500000, 1293750, 6250,
0509 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f,
0510 MT6358_VCORE_VGPU_ANA_CON0, 1),
0511 MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
0512 buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f,
0513 MT6358_VPA_ANA_CON0, 3),
0514 MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
0515 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
0516 MT6358_VPROC_ANA_CON0, 1),
0517 MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
0518 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
0519 MT6358_VPROC_ANA_CON0, 2),
0520 MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
0521 buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f,
0522 MT6358_VCORE_VGPU_ANA_CON0, 2),
0523 MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
0524 buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f,
0525 MT6358_VS2_ANA_CON0, 8),
0526 MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
0527 buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
0528 MT6358_VMODEM_ANA_CON0, 8),
0529 MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
0530 buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f,
0531 MT6358_VS1_ANA_CON0, 8),
0532 MT6358_REG_FIXED("ldo_vrf12", VRF12,
0533 MT6358_LDO_VRF12_CON0, 0, 1200000),
0534 MT6358_REG_FIXED("ldo_vio18", VIO18,
0535 MT6358_LDO_VIO18_CON0, 0, 1800000),
0536 MT6358_REG_FIXED("ldo_vcamio", VCAMIO,
0537 MT6358_LDO_VCAMIO_CON0, 0, 1800000),
0538 MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
0539 MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
0540 MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
0541 MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
0542 MT6358_REG_FIXED("ldo_vaux18", VAUX18,
0543 MT6358_LDO_VAUX18_CON0, 0, 1800000),
0544 MT6358_REG_FIXED("ldo_vbif28", VBIF28,
0545 MT6358_LDO_VBIF28_CON0, 0, 2800000),
0546 MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
0547 MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
0548 MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
0549 MT6358_REG_FIXED("ldo_vaud28", VAUD28,
0550 MT6358_LDO_VAUD28_CON0, 0, 2800000),
0551 MT6358_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx,
0552 MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf),
0553 MT6358_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx,
0554 MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
0555 MT6358_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx,
0556 MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
0557 MT6358_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx,
0558 MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
0559 MT6358_LDO("ldo_vcamd", VCAMD, vcamd_voltages, vcamd_idx,
0560 MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00),
0561 MT6358_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx,
0562 MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
0563 MT6358_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx,
0564 MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
0565 MT6358_LDO("ldo_vcama1", VCAMA1, vcama_voltages, vcama_idx,
0566 MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00),
0567 MT6358_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx,
0568 MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
0569 MT6358_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages,
0570 vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0,
0571 0, MT6358_VCN33_ANA_CON0, 0x300),
0572 MT6358_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages,
0573 vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1,
0574 0, MT6358_VCN33_ANA_CON0, 0x300),
0575 MT6358_LDO("ldo_vcama2", VCAMA2, vcama_voltages, vcama_idx,
0576 MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00),
0577 MT6358_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx,
0578 MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
0579 MT6358_LDO("ldo_vldo28", VLDO28, vldo28_voltages, vldo28_idx,
0580 MT6358_LDO_VLDO28_CON0_0, 0,
0581 MT6358_VLDO28_ANA_CON0, 0x300),
0582 MT6358_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx,
0583 MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
0584 MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
0585 buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00,
0586 MT6358_LDO_VSRAM_CON0, 0x7f),
0587 MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
0588 buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00,
0589 MT6358_LDO_VSRAM_CON2, 0x7f),
0590 MT6358_LDO1("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000,
0591 1293750, 6250, buck_volt_range1,
0592 MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f,
0593 MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f),
0594 MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
0595 buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00,
0596 MT6358_LDO_VSRAM_CON3, 0x7f),
0597 MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
0598 buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00,
0599 MT6358_LDO_VSRAM_CON1, 0x7f),
0600 };
0601
0602
0603 static struct mt6358_regulator_info mt6366_regulators[] = {
0604 MT6366_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
0605 buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
0606 MT6358_VDRAM1_ANA_CON0, 8),
0607 MT6366_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
0608 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
0609 MT6358_VCORE_VGPU_ANA_CON0, 1),
0610 MT6366_BUCK("buck_vcore_sshub", VCORE_SSHUB, 500000, 1293750, 6250,
0611 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f,
0612 MT6358_VCORE_VGPU_ANA_CON0, 1),
0613 MT6366_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
0614 buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f,
0615 MT6358_VPA_ANA_CON0, 3),
0616 MT6366_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
0617 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
0618 MT6358_VPROC_ANA_CON0, 1),
0619 MT6366_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
0620 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
0621 MT6358_VPROC_ANA_CON0, 2),
0622 MT6366_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
0623 buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f,
0624 MT6358_VCORE_VGPU_ANA_CON0, 2),
0625 MT6366_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
0626 buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f,
0627 MT6358_VS2_ANA_CON0, 8),
0628 MT6366_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
0629 buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
0630 MT6358_VMODEM_ANA_CON0, 8),
0631 MT6366_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
0632 buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f,
0633 MT6358_VS1_ANA_CON0, 8),
0634 MT6366_REG_FIXED("ldo_vrf12", VRF12,
0635 MT6358_LDO_VRF12_CON0, 0, 1200000),
0636 MT6366_REG_FIXED("ldo_vio18", VIO18,
0637 MT6358_LDO_VIO18_CON0, 0, 1800000),
0638 MT6366_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
0639 MT6366_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
0640 MT6366_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
0641 MT6366_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
0642 MT6366_REG_FIXED("ldo_vaux18", VAUX18,
0643 MT6358_LDO_VAUX18_CON0, 0, 1800000),
0644 MT6366_REG_FIXED("ldo_vbif28", VBIF28,
0645 MT6358_LDO_VBIF28_CON0, 0, 2800000),
0646 MT6366_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
0647 MT6366_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
0648 MT6366_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
0649 MT6366_REG_FIXED("ldo_vaud28", VAUD28,
0650 MT6358_LDO_VAUD28_CON0, 0, 2800000),
0651 MT6366_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx,
0652 MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10),
0653 MT6366_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx,
0654 MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
0655 MT6366_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx,
0656 MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
0657 MT6366_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx,
0658 MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
0659 MT6366_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx,
0660 MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
0661 MT6366_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx,
0662 MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
0663 MT6366_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx,
0664 MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
0665 MT6366_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages,
0666 vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0,
0667 0, MT6358_VCN33_ANA_CON0, 0x300),
0668 MT6366_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages,
0669 vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1,
0670 0, MT6358_VCN33_ANA_CON0, 0x300),
0671 MT6366_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx,
0672 MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
0673 MT6366_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx,
0674 MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
0675 MT6366_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
0676 buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00,
0677 MT6358_LDO_VSRAM_CON0, 0x7f),
0678 MT6366_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
0679 buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00,
0680 MT6358_LDO_VSRAM_CON2, 0x7f),
0681 MT6366_LDO1("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000,
0682 1293750, 6250, buck_volt_range1,
0683 MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f,
0684 MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f),
0685 MT6366_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
0686 buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00,
0687 MT6358_LDO_VSRAM_CON3, 0x7f),
0688 MT6366_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
0689 buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00,
0690 MT6358_LDO_VSRAM_CON1, 0x7f),
0691 };
0692
0693 static int mt6358_regulator_probe(struct platform_device *pdev)
0694 {
0695 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
0696 struct regulator_config config = {};
0697 struct regulator_dev *rdev;
0698 struct mt6358_regulator_info *mt6358_info;
0699 int i, max_regulator;
0700
0701 if (mt6397->chip_id == MT6366_CHIP_ID) {
0702 max_regulator = MT6366_MAX_REGULATOR;
0703 mt6358_info = mt6366_regulators;
0704 } else {
0705 max_regulator = MT6358_MAX_REGULATOR;
0706 mt6358_info = mt6358_regulators;
0707 }
0708
0709 for (i = 0; i < max_regulator; i++) {
0710 config.dev = &pdev->dev;
0711 config.driver_data = &mt6358_info[i];
0712 config.regmap = mt6397->regmap;
0713
0714 rdev = devm_regulator_register(&pdev->dev,
0715 &mt6358_info[i].desc,
0716 &config);
0717 if (IS_ERR(rdev)) {
0718 dev_err(&pdev->dev, "failed to register %s\n",
0719 mt6358_info[i].desc.name);
0720 return PTR_ERR(rdev);
0721 }
0722 }
0723
0724 return 0;
0725 }
0726
0727 static const struct platform_device_id mt6358_platform_ids[] = {
0728 {"mt6358-regulator", 0},
0729 { },
0730 };
0731 MODULE_DEVICE_TABLE(platform, mt6358_platform_ids);
0732
0733 static struct platform_driver mt6358_regulator_driver = {
0734 .driver = {
0735 .name = "mt6358-regulator",
0736 },
0737 .probe = mt6358_regulator_probe,
0738 .id_table = mt6358_platform_ids,
0739 };
0740
0741 module_platform_driver(mt6358_regulator_driver);
0742
0743 MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>");
0744 MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6358 PMIC");
0745 MODULE_LICENSE("GPL");