drivers/regulator/mt6311-regulator.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2015 MediaTek Inc.
0004  * Author: Henry Chen <henryc.chen@mediatek.com>
0005  */
0006
0007 #ifndef __MT6311_REGULATOR_H__
0008 #define __MT6311_REGULATOR_H__
0009
0010 #define MT6311_SWCID              0x01
0011
0012 #define MT6311_TOP_INT_CON        0x18
0013 #define MT6311_TOP_INT_MON        0x19
0014
0015 #define MT6311_VDVFS11_CON0       0x87
0016 #define MT6311_VDVFS11_CON7       0x88
0017 #define MT6311_VDVFS11_CON8       0x89
0018 #define MT6311_VDVFS11_CON9       0x8A
0019 #define MT6311_VDVFS11_CON10      0x8B
0020 #define MT6311_VDVFS11_CON11      0x8C
0021 #define MT6311_VDVFS11_CON12      0x8D
0022 #define MT6311_VDVFS11_CON13      0x8E
0023 #define MT6311_VDVFS11_CON14      0x8F
0024 #define MT6311_VDVFS11_CON15      0x90
0025 #define MT6311_VDVFS11_CON16      0x91
0026 #define MT6311_VDVFS11_CON17      0x92
0027 #define MT6311_VDVFS11_CON18      0x93
0028 #define MT6311_VDVFS11_CON19      0x94
0029
0030 #define MT6311_LDO_CON0           0xCC
0031 #define MT6311_LDO_OCFB0          0xCD
0032 #define MT6311_LDO_CON2           0xCE
0033 #define MT6311_LDO_CON3           0xCF
0034 #define MT6311_LDO_CON4           0xD0
0035 #define MT6311_FQMTR_CON0         0xD1
0036 #define MT6311_FQMTR_CON1         0xD2
0037 #define MT6311_FQMTR_CON2         0xD3
0038 #define MT6311_FQMTR_CON3         0xD4
0039 #define MT6311_FQMTR_CON4         0xD5
0040
0041 #define MT6311_PMIC_RG_INT_POL_MASK                      0x1
0042 #define MT6311_PMIC_RG_INT_EN_MASK                       0x2
0043 #define MT6311_PMIC_RG_BUCK_OC_INT_STATUS_MASK           0x10
0044
0045 #define MT6311_PMIC_VDVFS11_EN_CTRL_MASK                 0x1
0046 #define MT6311_PMIC_VDVFS11_VOSEL_CTRL_MASK              0x2
0047 #define MT6311_PMIC_VDVFS11_EN_SEL_MASK                  0x3
0048 #define MT6311_PMIC_VDVFS11_VOSEL_SEL_MASK               0xc
0049 #define MT6311_PMIC_VDVFS11_EN_MASK                      0x1
0050 #define MT6311_PMIC_VDVFS11_VOSEL_MASK                   0x7F
0051 #define MT6311_PMIC_VDVFS11_VOSEL_ON_MASK                0x7F
0052 #define MT6311_PMIC_VDVFS11_VOSEL_SLEEP_MASK             0x7F
0053 #define MT6311_PMIC_NI_VDVFS11_VOSEL_MASK                0x7F
0054
0055 #define MT6311_PMIC_RG_VBIASN_EN_MASK                    0x1
0056
0057 #endif