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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Regulator Driver for Freescale MC13892 PMIC
0004 //
0005 // Copyright 2010 Yong Shen <yong.shen@linaro.org>
0006 //
0007 // Based on draft driver from Arnaud Patard <arnaud.patard@rtp-net.org>
0008 
0009 #include <linux/mfd/mc13892.h>
0010 #include <linux/regulator/machine.h>
0011 #include <linux/regulator/driver.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/kernel.h>
0014 #include <linux/slab.h>
0015 #include <linux/init.h>
0016 #include <linux/err.h>
0017 #include <linux/module.h>
0018 #include "mc13xxx.h"
0019 
0020 #define MC13892_REVISION            7
0021 
0022 #define MC13892_POWERCTL0           13
0023 #define MC13892_POWERCTL0_USEROFFSPI        3
0024 #define MC13892_POWERCTL0_VCOINCELLVSEL     20
0025 #define MC13892_POWERCTL0_VCOINCELLVSEL_M   (7<<20)
0026 #define MC13892_POWERCTL0_VCOINCELLEN       (1<<23)
0027 
0028 #define MC13892_SWITCHERS0_SWxHI        (1<<23)
0029 
0030 #define MC13892_SWITCHERS0          24
0031 #define MC13892_SWITCHERS0_SW1VSEL      0
0032 #define MC13892_SWITCHERS0_SW1VSEL_M        (0x1f<<0)
0033 #define MC13892_SWITCHERS0_SW1HI        (1<<23)
0034 #define MC13892_SWITCHERS0_SW1EN        0
0035 
0036 #define MC13892_SWITCHERS1          25
0037 #define MC13892_SWITCHERS1_SW2VSEL      0
0038 #define MC13892_SWITCHERS1_SW2VSEL_M        (0x1f<<0)
0039 #define MC13892_SWITCHERS1_SW2HI        (1<<23)
0040 #define MC13892_SWITCHERS1_SW2EN        0
0041 
0042 #define MC13892_SWITCHERS2          26
0043 #define MC13892_SWITCHERS2_SW3VSEL      0
0044 #define MC13892_SWITCHERS2_SW3VSEL_M        (0x1f<<0)
0045 #define MC13892_SWITCHERS2_SW3HI        (1<<23)
0046 #define MC13892_SWITCHERS2_SW3EN        0
0047 
0048 #define MC13892_SWITCHERS3          27
0049 #define MC13892_SWITCHERS3_SW4VSEL      0
0050 #define MC13892_SWITCHERS3_SW4VSEL_M        (0x1f<<0)
0051 #define MC13892_SWITCHERS3_SW4HI        (1<<23)
0052 #define MC13892_SWITCHERS3_SW4EN        0
0053 
0054 #define MC13892_SWITCHERS4          28
0055 #define MC13892_SWITCHERS4_SW1MODE      0
0056 #define MC13892_SWITCHERS4_SW1MODE_AUTO     (8<<0)
0057 #define MC13892_SWITCHERS4_SW1MODE_M        (0xf<<0)
0058 #define MC13892_SWITCHERS4_SW2MODE      10
0059 #define MC13892_SWITCHERS4_SW2MODE_AUTO     (8<<10)
0060 #define MC13892_SWITCHERS4_SW2MODE_M        (0xf<<10)
0061 
0062 #define MC13892_SWITCHERS5          29
0063 #define MC13892_SWITCHERS5_SW3MODE      0
0064 #define MC13892_SWITCHERS5_SW3MODE_AUTO     (8<<0)
0065 #define MC13892_SWITCHERS5_SW3MODE_M        (0xf<<0)
0066 #define MC13892_SWITCHERS5_SW4MODE      8
0067 #define MC13892_SWITCHERS5_SW4MODE_AUTO     (8<<8)
0068 #define MC13892_SWITCHERS5_SW4MODE_M        (0xf<<8)
0069 #define MC13892_SWITCHERS5_SWBSTEN      (1<<20)
0070 
0071 #define MC13892_REGULATORSETTING0       30
0072 #define MC13892_REGULATORSETTING0_VGEN1VSEL 0
0073 #define MC13892_REGULATORSETTING0_VDIGVSEL  4
0074 #define MC13892_REGULATORSETTING0_VGEN2VSEL 6
0075 #define MC13892_REGULATORSETTING0_VPLLVSEL  9
0076 #define MC13892_REGULATORSETTING0_VUSB2VSEL 11
0077 #define MC13892_REGULATORSETTING0_VGEN3VSEL 14
0078 #define MC13892_REGULATORSETTING0_VCAMVSEL  16
0079 
0080 #define MC13892_REGULATORSETTING0_VGEN1VSEL_M   (3<<0)
0081 #define MC13892_REGULATORSETTING0_VDIGVSEL_M    (3<<4)
0082 #define MC13892_REGULATORSETTING0_VGEN2VSEL_M   (7<<6)
0083 #define MC13892_REGULATORSETTING0_VPLLVSEL_M    (3<<9)
0084 #define MC13892_REGULATORSETTING0_VUSB2VSEL_M   (3<<11)
0085 #define MC13892_REGULATORSETTING0_VGEN3VSEL_M   (1<<14)
0086 #define MC13892_REGULATORSETTING0_VCAMVSEL_M    (3<<16)
0087 
0088 #define MC13892_REGULATORSETTING1       31
0089 #define MC13892_REGULATORSETTING1_VVIDEOVSEL    2
0090 #define MC13892_REGULATORSETTING1_VAUDIOVSEL    4
0091 #define MC13892_REGULATORSETTING1_VSDVSEL   6
0092 
0093 #define MC13892_REGULATORSETTING1_VVIDEOVSEL_M  (3<<2)
0094 #define MC13892_REGULATORSETTING1_VAUDIOVSEL_M  (3<<4)
0095 #define MC13892_REGULATORSETTING1_VSDVSEL_M (7<<6)
0096 
0097 #define MC13892_REGULATORMODE0          32
0098 #define MC13892_REGULATORMODE0_VGEN1EN      (1<<0)
0099 #define MC13892_REGULATORMODE0_VGEN1STDBY   (1<<1)
0100 #define MC13892_REGULATORMODE0_VGEN1MODE    (1<<2)
0101 #define MC13892_REGULATORMODE0_VIOHIEN      (1<<3)
0102 #define MC13892_REGULATORMODE0_VIOHISTDBY   (1<<4)
0103 #define MC13892_REGULATORMODE0_VIOHIMODE    (1<<5)
0104 #define MC13892_REGULATORMODE0_VDIGEN       (1<<9)
0105 #define MC13892_REGULATORMODE0_VDIGSTDBY    (1<<10)
0106 #define MC13892_REGULATORMODE0_VDIGMODE     (1<<11)
0107 #define MC13892_REGULATORMODE0_VGEN2EN      (1<<12)
0108 #define MC13892_REGULATORMODE0_VGEN2STDBY   (1<<13)
0109 #define MC13892_REGULATORMODE0_VGEN2MODE    (1<<14)
0110 #define MC13892_REGULATORMODE0_VPLLEN       (1<<15)
0111 #define MC13892_REGULATORMODE0_VPLLSTDBY    (1<<16)
0112 #define MC13892_REGULATORMODE0_VPLLMODE     (1<<17)
0113 #define MC13892_REGULATORMODE0_VUSB2EN      (1<<18)
0114 #define MC13892_REGULATORMODE0_VUSB2STDBY   (1<<19)
0115 #define MC13892_REGULATORMODE0_VUSB2MODE    (1<<20)
0116 
0117 #define MC13892_REGULATORMODE1          33
0118 #define MC13892_REGULATORMODE1_VGEN3EN      (1<<0)
0119 #define MC13892_REGULATORMODE1_VGEN3STDBY   (1<<1)
0120 #define MC13892_REGULATORMODE1_VGEN3MODE    (1<<2)
0121 #define MC13892_REGULATORMODE1_VCAMEN       (1<<6)
0122 #define MC13892_REGULATORMODE1_VCAMSTDBY    (1<<7)
0123 #define MC13892_REGULATORMODE1_VCAMMODE     (1<<8)
0124 #define MC13892_REGULATORMODE1_VCAMCONFIGEN (1<<9)
0125 #define MC13892_REGULATORMODE1_VVIDEOEN     (1<<12)
0126 #define MC13892_REGULATORMODE1_VVIDEOSTDBY  (1<<13)
0127 #define MC13892_REGULATORMODE1_VVIDEOMODE   (1<<14)
0128 #define MC13892_REGULATORMODE1_VAUDIOEN     (1<<15)
0129 #define MC13892_REGULATORMODE1_VAUDIOSTDBY  (1<<16)
0130 #define MC13892_REGULATORMODE1_VAUDIOMODE   (1<<17)
0131 #define MC13892_REGULATORMODE1_VSDEN        (1<<18)
0132 #define MC13892_REGULATORMODE1_VSDSTDBY     (1<<19)
0133 #define MC13892_REGULATORMODE1_VSDMODE      (1<<20)
0134 
0135 #define MC13892_POWERMISC           34
0136 #define MC13892_POWERMISC_GPO1EN        (1<<6)
0137 #define MC13892_POWERMISC_GPO2EN        (1<<8)
0138 #define MC13892_POWERMISC_GPO3EN        (1<<10)
0139 #define MC13892_POWERMISC_GPO4EN        (1<<12)
0140 #define MC13892_POWERMISC_PWGT1SPIEN        (1<<15)
0141 #define MC13892_POWERMISC_PWGT2SPIEN        (1<<16)
0142 #define MC13892_POWERMISC_GPO4ADINEN        (1<<21)
0143 
0144 #define MC13892_POWERMISC_PWGTSPI_M     (3 << 15)
0145 
0146 #define MC13892_USB1                50
0147 #define MC13892_USB1_VUSBEN         (1<<3)
0148 
0149 static const unsigned int mc13892_vcoincell[] = {
0150     2500000, 2700000, 2800000, 2900000, 3000000, 3100000,
0151     3200000, 3300000,
0152 };
0153 
0154 static const unsigned int mc13892_sw1[] = {
0155     600000,   625000,  650000,  675000,  700000,  725000,
0156     750000,   775000,  800000,  825000,  850000,  875000,
0157     900000,   925000,  950000,  975000, 1000000, 1025000,
0158     1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
0159     1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
0160     1350000, 1375000
0161 };
0162 
0163 /*
0164  * Note: this table is used to derive SWxVSEL by index into
0165  * the array. Offset the values by the index of 1100000uV
0166  * to get the actual register value for that voltage selector
0167  * if the HI bit is to be set as well.
0168  */
0169 #define MC13892_SWxHI_SEL_OFFSET        20
0170 
0171 static const unsigned int mc13892_sw[] = {
0172     600000,   625000,  650000,  675000,  700000,  725000,
0173     750000,   775000,  800000,  825000,  850000,  875000,
0174     900000,   925000,  950000,  975000, 1000000, 1025000,
0175     1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
0176     1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
0177     1350000, 1375000, 1400000, 1425000, 1450000, 1475000,
0178     1500000, 1525000, 1550000, 1575000, 1600000, 1625000,
0179     1650000, 1675000, 1700000, 1725000, 1750000, 1775000,
0180     1800000, 1825000, 1850000, 1875000
0181 };
0182 
0183 static const unsigned int mc13892_swbst[] = {
0184     5000000,
0185 };
0186 
0187 static const unsigned int mc13892_viohi[] = {
0188     2775000,
0189 };
0190 
0191 static const unsigned int mc13892_vpll[] = {
0192     1050000, 1250000, 1650000, 1800000,
0193 };
0194 
0195 static const unsigned int mc13892_vdig[] = {
0196     1050000, 1250000, 1650000, 1800000,
0197 };
0198 
0199 static const unsigned int mc13892_vsd[] = {
0200     1800000, 2000000, 2600000, 2700000,
0201     2800000, 2900000, 3000000, 3150000,
0202 };
0203 
0204 static const unsigned int mc13892_vusb2[] = {
0205     2400000, 2600000, 2700000, 2775000,
0206 };
0207 
0208 static const unsigned int mc13892_vvideo[] = {
0209     2700000, 2775000, 2500000, 2600000,
0210 };
0211 
0212 static const unsigned int mc13892_vaudio[] = {
0213     2300000, 2500000, 2775000, 3000000,
0214 };
0215 
0216 static const unsigned int mc13892_vcam[] = {
0217     2500000, 2600000, 2750000, 3000000,
0218 };
0219 
0220 static const unsigned int mc13892_vgen1[] = {
0221     1200000, 1500000, 2775000, 3150000,
0222 };
0223 
0224 static const unsigned int mc13892_vgen2[] = {
0225     1200000, 1500000, 1600000, 1800000,
0226     2700000, 2800000, 3000000, 3150000,
0227 };
0228 
0229 static const unsigned int mc13892_vgen3[] = {
0230     1800000, 2900000,
0231 };
0232 
0233 static const unsigned int mc13892_vusb[] = {
0234     3300000,
0235 };
0236 
0237 static const unsigned int mc13892_gpo[] = {
0238     2750000,
0239 };
0240 
0241 static const unsigned int mc13892_pwgtdrv[] = {
0242     5000000,
0243 };
0244 
0245 static const struct regulator_ops mc13892_gpo_regulator_ops;
0246 static const struct regulator_ops mc13892_sw_regulator_ops;
0247 
0248 
0249 #define MC13892_FIXED_DEFINE(name, node, reg, voltages)         \
0250     MC13xxx_FIXED_DEFINE(MC13892_, name, node, reg, voltages,   \
0251             mc13xxx_fixed_regulator_ops)
0252 
0253 #define MC13892_GPO_DEFINE(name, node, reg, voltages)           \
0254     MC13xxx_GPO_DEFINE(MC13892_, name, node, reg, voltages,     \
0255             mc13892_gpo_regulator_ops)
0256 
0257 #define MC13892_SW_DEFINE(name, node, reg, vsel_reg, voltages)      \
0258     MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages,   \
0259             mc13892_sw_regulator_ops)
0260 
0261 #define MC13892_DEFINE_REGU(name, node, reg, vsel_reg, voltages)    \
0262     MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages, \
0263             mc13xxx_regulator_ops)
0264 
0265 static struct mc13xxx_regulator mc13892_regulators[] = {
0266     MC13892_DEFINE_REGU(VCOINCELL, vcoincell, POWERCTL0, POWERCTL0, mc13892_vcoincell),
0267     MC13892_SW_DEFINE(SW1, sw1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
0268     MC13892_SW_DEFINE(SW2, sw2, SWITCHERS1, SWITCHERS1, mc13892_sw),
0269     MC13892_SW_DEFINE(SW3, sw3, SWITCHERS2, SWITCHERS2, mc13892_sw),
0270     MC13892_SW_DEFINE(SW4, sw4, SWITCHERS3, SWITCHERS3, mc13892_sw),
0271     MC13892_FIXED_DEFINE(SWBST, swbst, SWITCHERS5, mc13892_swbst),
0272     MC13892_FIXED_DEFINE(VIOHI, viohi, REGULATORMODE0, mc13892_viohi),
0273     MC13892_DEFINE_REGU(VPLL, vpll, REGULATORMODE0, REGULATORSETTING0,
0274         mc13892_vpll),
0275     MC13892_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0,
0276         mc13892_vdig),
0277     MC13892_DEFINE_REGU(VSD, vsd, REGULATORMODE1, REGULATORSETTING1,
0278         mc13892_vsd),
0279     MC13892_DEFINE_REGU(VUSB2, vusb2, REGULATORMODE0, REGULATORSETTING0,
0280         mc13892_vusb2),
0281     MC13892_DEFINE_REGU(VVIDEO, vvideo, REGULATORMODE1, REGULATORSETTING1,
0282         mc13892_vvideo),
0283     MC13892_DEFINE_REGU(VAUDIO, vaudio, REGULATORMODE1, REGULATORSETTING1,
0284         mc13892_vaudio),
0285     MC13892_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0,
0286         mc13892_vcam),
0287     MC13892_DEFINE_REGU(VGEN1, vgen1, REGULATORMODE0, REGULATORSETTING0,
0288         mc13892_vgen1),
0289     MC13892_DEFINE_REGU(VGEN2, vgen2, REGULATORMODE0, REGULATORSETTING0,
0290         mc13892_vgen2),
0291     MC13892_DEFINE_REGU(VGEN3, vgen3, REGULATORMODE1, REGULATORSETTING0,
0292         mc13892_vgen3),
0293     MC13892_FIXED_DEFINE(VUSB, vusb, USB1, mc13892_vusb),
0294     MC13892_GPO_DEFINE(GPO1, gpo1, POWERMISC, mc13892_gpo),
0295     MC13892_GPO_DEFINE(GPO2, gpo2, POWERMISC, mc13892_gpo),
0296     MC13892_GPO_DEFINE(GPO3, gpo3, POWERMISC, mc13892_gpo),
0297     MC13892_GPO_DEFINE(GPO4, gpo4, POWERMISC, mc13892_gpo),
0298     MC13892_GPO_DEFINE(PWGT1SPI, pwgt1spi, POWERMISC, mc13892_pwgtdrv),
0299     MC13892_GPO_DEFINE(PWGT2SPI, pwgt2spi, POWERMISC, mc13892_pwgtdrv),
0300 };
0301 
0302 static int mc13892_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
0303                  u32 val)
0304 {
0305     struct mc13xxx *mc13892 = priv->mc13xxx;
0306     int ret;
0307     u32 valread;
0308 
0309     BUG_ON(val & ~mask);
0310 
0311     mc13xxx_lock(priv->mc13xxx);
0312     ret = mc13xxx_reg_read(mc13892, MC13892_POWERMISC, &valread);
0313     if (ret)
0314         goto out;
0315 
0316     /* Update the stored state for Power Gates. */
0317     priv->powermisc_pwgt_state =
0318         (priv->powermisc_pwgt_state & ~mask) | val;
0319     priv->powermisc_pwgt_state &= MC13892_POWERMISC_PWGTSPI_M;
0320 
0321     /* Construct the new register value */
0322     valread = (valread & ~mask) | val;
0323     /* Overwrite the PWGTxEN with the stored version */
0324     valread = (valread & ~MC13892_POWERMISC_PWGTSPI_M) |
0325         priv->powermisc_pwgt_state;
0326 
0327     ret = mc13xxx_reg_write(mc13892, MC13892_POWERMISC, valread);
0328 out:
0329     mc13xxx_unlock(priv->mc13xxx);
0330     return ret;
0331 }
0332 
0333 static int mc13892_gpo_regulator_enable(struct regulator_dev *rdev)
0334 {
0335     struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
0336     int id = rdev_get_id(rdev);
0337     u32 en_val = mc13892_regulators[id].enable_bit;
0338     u32 mask = mc13892_regulators[id].enable_bit;
0339 
0340     dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
0341 
0342     /* Power Gate enable value is 0 */
0343     if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
0344         en_val = 0;
0345 
0346     if (id == MC13892_GPO4)
0347         mask |= MC13892_POWERMISC_GPO4ADINEN;
0348 
0349     return mc13892_powermisc_rmw(priv, mask, en_val);
0350 }
0351 
0352 static int mc13892_gpo_regulator_disable(struct regulator_dev *rdev)
0353 {
0354     struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
0355     int id = rdev_get_id(rdev);
0356     u32 dis_val = 0;
0357 
0358     dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
0359 
0360     /* Power Gate disable value is 1 */
0361     if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
0362         dis_val = mc13892_regulators[id].enable_bit;
0363 
0364     return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit,
0365         dis_val);
0366 }
0367 
0368 static int mc13892_gpo_regulator_is_enabled(struct regulator_dev *rdev)
0369 {
0370     struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
0371     int ret, id = rdev_get_id(rdev);
0372     unsigned int val;
0373 
0374     mc13xxx_lock(priv->mc13xxx);
0375     ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
0376     mc13xxx_unlock(priv->mc13xxx);
0377 
0378     if (ret)
0379         return ret;
0380 
0381     /* Power Gates state is stored in powermisc_pwgt_state
0382      * where the meaning of bits is negated */
0383     val = (val & ~MC13892_POWERMISC_PWGTSPI_M) |
0384         (priv->powermisc_pwgt_state ^ MC13892_POWERMISC_PWGTSPI_M);
0385 
0386     return (val & mc13892_regulators[id].enable_bit) != 0;
0387 }
0388 
0389 
0390 static const struct regulator_ops mc13892_gpo_regulator_ops = {
0391     .enable = mc13892_gpo_regulator_enable,
0392     .disable = mc13892_gpo_regulator_disable,
0393     .is_enabled = mc13892_gpo_regulator_is_enabled,
0394     .list_voltage = regulator_list_voltage_table,
0395     .set_voltage = mc13xxx_fixed_regulator_set_voltage,
0396 };
0397 
0398 static int mc13892_sw_regulator_get_voltage_sel(struct regulator_dev *rdev)
0399 {
0400     struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
0401     int ret, id = rdev_get_id(rdev);
0402     unsigned int val, selector;
0403 
0404     dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
0405 
0406     mc13xxx_lock(priv->mc13xxx);
0407     ret = mc13xxx_reg_read(priv->mc13xxx,
0408         mc13892_regulators[id].vsel_reg, &val);
0409     mc13xxx_unlock(priv->mc13xxx);
0410     if (ret)
0411         return ret;
0412 
0413     /*
0414      * Figure out if the HI bit is set inside the switcher mode register
0415      * since this means the selector value we return is at a different
0416      * offset into the selector table.
0417      *
0418      * According to the MC13892 documentation note 59 (Table 47) the SW1
0419      * buck switcher does not support output range programming therefore
0420      * the HI bit must always remain 0. So do not do anything strange if
0421      * our register is MC13892_SWITCHERS0.
0422      */
0423 
0424     selector = val & mc13892_regulators[id].vsel_mask;
0425 
0426     if ((mc13892_regulators[id].vsel_reg != MC13892_SWITCHERS0) &&
0427         (val & MC13892_SWITCHERS0_SWxHI)) {
0428         selector += MC13892_SWxHI_SEL_OFFSET;
0429     }
0430 
0431     dev_dbg(rdev_get_dev(rdev), "%s id: %d val: 0x%08x selector: %d\n",
0432             __func__, id, val, selector);
0433 
0434     return selector;
0435 }
0436 
0437 static int mc13892_sw_regulator_set_voltage_sel(struct regulator_dev *rdev,
0438                         unsigned selector)
0439 {
0440     struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
0441     int volt, mask, id = rdev_get_id(rdev);
0442     u32 reg_value;
0443     int ret;
0444 
0445     volt = rdev->desc->volt_table[selector];
0446     mask = mc13892_regulators[id].vsel_mask;
0447     reg_value = selector;
0448 
0449     /*
0450      * Don't mess with the HI bit or support HI voltage offsets for SW1.
0451      *
0452      * Since the get_voltage_sel callback has given a fudged value for
0453      * the selector offset, we need to back out that offset if HI is
0454      * to be set so we write the correct value to the register.
0455      *
0456      * The HI bit addition and selector offset handling COULD be more
0457      * complicated by shifting and masking off the voltage selector part
0458      * of the register then logical OR it back in, but since the selector
0459      * is at bits 4:0 there is very little point. This makes the whole
0460      * thing more readable and we do far less work.
0461      */
0462 
0463     if (mc13892_regulators[id].vsel_reg != MC13892_SWITCHERS0) {
0464         mask |= MC13892_SWITCHERS0_SWxHI;
0465 
0466         if (volt > 1375000) {
0467             reg_value -= MC13892_SWxHI_SEL_OFFSET;
0468             reg_value |= MC13892_SWITCHERS0_SWxHI;
0469         } else {
0470             reg_value &= ~MC13892_SWITCHERS0_SWxHI;
0471         }
0472     }
0473 
0474     mc13xxx_lock(priv->mc13xxx);
0475     ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].vsel_reg,
0476                   mask, reg_value);
0477     mc13xxx_unlock(priv->mc13xxx);
0478 
0479     return ret;
0480 }
0481 
0482 static const struct regulator_ops mc13892_sw_regulator_ops = {
0483     .list_voltage = regulator_list_voltage_table,
0484     .map_voltage = regulator_map_voltage_ascend,
0485     .set_voltage_sel = mc13892_sw_regulator_set_voltage_sel,
0486     .get_voltage_sel = mc13892_sw_regulator_get_voltage_sel,
0487 };
0488 
0489 static int mc13892_vcam_set_mode(struct regulator_dev *rdev, unsigned int mode)
0490 {
0491     unsigned int en_val = 0;
0492     struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
0493     int ret, id = rdev_get_id(rdev);
0494 
0495     if (mode == REGULATOR_MODE_FAST)
0496         en_val = MC13892_REGULATORMODE1_VCAMCONFIGEN;
0497 
0498     mc13xxx_lock(priv->mc13xxx);
0499     ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].reg,
0500         MC13892_REGULATORMODE1_VCAMCONFIGEN, en_val);
0501     mc13xxx_unlock(priv->mc13xxx);
0502 
0503     return ret;
0504 }
0505 
0506 static unsigned int mc13892_vcam_get_mode(struct regulator_dev *rdev)
0507 {
0508     struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
0509     int ret, id = rdev_get_id(rdev);
0510     unsigned int val;
0511 
0512     mc13xxx_lock(priv->mc13xxx);
0513     ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
0514     mc13xxx_unlock(priv->mc13xxx);
0515 
0516     if (ret)
0517         return ret;
0518 
0519     if (val & MC13892_REGULATORMODE1_VCAMCONFIGEN)
0520         return REGULATOR_MODE_FAST;
0521 
0522     return REGULATOR_MODE_NORMAL;
0523 }
0524 
0525 static struct regulator_ops mc13892_vcam_ops;
0526 
0527 static int mc13892_regulator_probe(struct platform_device *pdev)
0528 {
0529     struct mc13xxx_regulator_priv *priv;
0530     struct mc13xxx *mc13892 = dev_get_drvdata(pdev->dev.parent);
0531     struct mc13xxx_regulator_platform_data *pdata =
0532         dev_get_platdata(&pdev->dev);
0533     struct mc13xxx_regulator_init_data *mc13xxx_data;
0534     struct regulator_config config = { };
0535     int i, ret;
0536     int num_regulators = 0;
0537     u32 val;
0538 
0539     num_regulators = mc13xxx_get_num_regulators_dt(pdev);
0540 
0541     if (num_regulators <= 0 && pdata)
0542         num_regulators = pdata->num_regulators;
0543     if (num_regulators <= 0)
0544         return -EINVAL;
0545 
0546     priv = devm_kzalloc(&pdev->dev,
0547                 struct_size(priv, regulators, num_regulators),
0548                 GFP_KERNEL);
0549     if (!priv)
0550         return -ENOMEM;
0551 
0552     priv->num_regulators = num_regulators;
0553     priv->mc13xxx_regulators = mc13892_regulators;
0554     priv->mc13xxx = mc13892;
0555     platform_set_drvdata(pdev, priv);
0556 
0557     mc13xxx_lock(mc13892);
0558     ret = mc13xxx_reg_read(mc13892, MC13892_REVISION, &val);
0559     if (ret)
0560         goto err_unlock;
0561 
0562     /* enable switch auto mode (on 2.0A silicon only) */
0563     if ((val & 0x0000FFFF) == 0x45d0) {
0564         ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS4,
0565             MC13892_SWITCHERS4_SW1MODE_M |
0566             MC13892_SWITCHERS4_SW2MODE_M,
0567             MC13892_SWITCHERS4_SW1MODE_AUTO |
0568             MC13892_SWITCHERS4_SW2MODE_AUTO);
0569         if (ret)
0570             goto err_unlock;
0571 
0572         ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS5,
0573             MC13892_SWITCHERS5_SW3MODE_M |
0574             MC13892_SWITCHERS5_SW4MODE_M,
0575             MC13892_SWITCHERS5_SW3MODE_AUTO |
0576             MC13892_SWITCHERS5_SW4MODE_AUTO);
0577         if (ret)
0578             goto err_unlock;
0579     }
0580     mc13xxx_unlock(mc13892);
0581 
0582     /* update mc13892_vcam ops */
0583     memcpy(&mc13892_vcam_ops, mc13892_regulators[MC13892_VCAM].desc.ops,
0584                         sizeof(struct regulator_ops));
0585     mc13892_vcam_ops.set_mode = mc13892_vcam_set_mode;
0586     mc13892_vcam_ops.get_mode = mc13892_vcam_get_mode;
0587     mc13892_regulators[MC13892_VCAM].desc.ops = &mc13892_vcam_ops;
0588 
0589     mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13892_regulators,
0590                     ARRAY_SIZE(mc13892_regulators));
0591 
0592     for (i = 0; i < priv->num_regulators; i++) {
0593         struct regulator_init_data *init_data;
0594         struct regulator_desc *desc;
0595         struct device_node *node = NULL;
0596         int id;
0597 
0598         if (mc13xxx_data) {
0599             id = mc13xxx_data[i].id;
0600             init_data = mc13xxx_data[i].init_data;
0601             node = mc13xxx_data[i].node;
0602         } else {
0603             id = pdata->regulators[i].id;
0604             init_data = pdata->regulators[i].init_data;
0605         }
0606         desc = &mc13892_regulators[id].desc;
0607 
0608         config.dev = &pdev->dev;
0609         config.init_data = init_data;
0610         config.driver_data = priv;
0611         config.of_node = node;
0612 
0613         priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
0614                                   &config);
0615         if (IS_ERR(priv->regulators[i])) {
0616             dev_err(&pdev->dev, "failed to register regulator %s\n",
0617                 mc13892_regulators[i].desc.name);
0618             return PTR_ERR(priv->regulators[i]);
0619         }
0620     }
0621 
0622     return 0;
0623 
0624 err_unlock:
0625     mc13xxx_unlock(mc13892);
0626     return ret;
0627 }
0628 
0629 static struct platform_driver mc13892_regulator_driver = {
0630     .driver = {
0631         .name   = "mc13892-regulator",
0632     },
0633     .probe  = mc13892_regulator_probe,
0634 };
0635 
0636 static int __init mc13892_regulator_init(void)
0637 {
0638     return platform_driver_register(&mc13892_regulator_driver);
0639 }
0640 subsys_initcall(mc13892_regulator_init);
0641 
0642 static void __exit mc13892_regulator_exit(void)
0643 {
0644     platform_driver_unregister(&mc13892_regulator_driver);
0645 }
0646 module_exit(mc13892_regulator_exit);
0647 
0648 MODULE_LICENSE("GPL v2");
0649 MODULE_AUTHOR("Yong Shen <yong.shen@linaro.org>");
0650 MODULE_DESCRIPTION("Regulator Driver for Freescale MC13892 PMIC");
0651 MODULE_ALIAS("platform:mc13892-regulator");
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