drivers/regulator/mc13783-regulator.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Regulator Driver for Freescale MC13783 PMIC
0004 //
0005 // Copyright 2010 Yong Shen <yong.shen@linaro.org>
0006 // Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
0007 // Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
0008
0009 #include <linux/mfd/mc13783.h>
0010 #include <linux/regulator/machine.h>
0011 #include <linux/regulator/driver.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/kernel.h>
0014 #include <linux/slab.h>
0015 #include <linux/init.h>
0016 #include <linux/err.h>
0017 #include <linux/module.h>
0018 #include "mc13xxx.h"
0019
0020 #define MC13783_REG_SWITCHERS0          24
0021 /* Enable does not exist for SW1A */
0022 #define MC13783_REG_SWITCHERS0_SW1AEN           0
0023 #define MC13783_REG_SWITCHERS0_SW1AVSEL         0
0024 #define MC13783_REG_SWITCHERS0_SW1AVSEL_M       (63 << 0)
0025
0026 #define MC13783_REG_SWITCHERS1          25
0027 /* Enable does not exist for SW1B */
0028 #define MC13783_REG_SWITCHERS1_SW1BEN           0
0029 #define MC13783_REG_SWITCHERS1_SW1BVSEL         0
0030 #define MC13783_REG_SWITCHERS1_SW1BVSEL_M       (63 << 0)
0031
0032 #define MC13783_REG_SWITCHERS2          26
0033 /* Enable does not exist for SW2A */
0034 #define MC13783_REG_SWITCHERS2_SW2AEN           0
0035 #define MC13783_REG_SWITCHERS2_SW2AVSEL         0
0036 #define MC13783_REG_SWITCHERS2_SW2AVSEL_M       (63 << 0)
0037
0038 #define MC13783_REG_SWITCHERS3          27
0039 /* Enable does not exist for SW2B */
0040 #define MC13783_REG_SWITCHERS3_SW2BEN           0
0041 #define MC13783_REG_SWITCHERS3_SW2BVSEL         0
0042 #define MC13783_REG_SWITCHERS3_SW2BVSEL_M       (63 << 0)
0043
0044 #define MC13783_REG_SWITCHERS5          29
0045 #define MC13783_REG_SWITCHERS5_SW3EN            (1 << 20)
0046 #define MC13783_REG_SWITCHERS5_SW3VSEL          18
0047 #define MC13783_REG_SWITCHERS5_SW3VSEL_M        (3 << 18)
0048
0049 #define MC13783_REG_REGULATORSETTING0       30
0050 #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL     2
0051 #define MC13783_REG_REGULATORSETTING0_VDIGVSEL      4
0052 #define MC13783_REG_REGULATORSETTING0_VGENVSEL      6
0053 #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL    9
0054 #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL    11
0055 #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL     13
0056 #define MC13783_REG_REGULATORSETTING0_VSIMVSEL      14
0057 #define MC13783_REG_REGULATORSETTING0_VESIMVSEL     15
0058 #define MC13783_REG_REGULATORSETTING0_VCAMVSEL      16
0059
0060 #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M   (3 << 2)
0061 #define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M    (3 << 4)
0062 #define MC13783_REG_REGULATORSETTING0_VGENVSEL_M    (7 << 6)
0063 #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M  (3 << 9)
0064 #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M  (3 << 11)
0065 #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M   (1 << 13)
0066 #define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M    (1 << 14)
0067 #define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M   (1 << 15)
0068 #define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M    (7 << 16)
0069
0070 #define MC13783_REG_REGULATORSETTING1       31
0071 #define MC13783_REG_REGULATORSETTING1_VVIBVSEL      0
0072 #define MC13783_REG_REGULATORSETTING1_VRF1VSEL      2
0073 #define MC13783_REG_REGULATORSETTING1_VRF2VSEL      4
0074 #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL     6
0075 #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL     9
0076
0077 #define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M    (3 << 0)
0078 #define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M    (3 << 2)
0079 #define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M    (3 << 4)
0080 #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M   (7 << 6)
0081 #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M   (7 << 9)
0082
0083 #define MC13783_REG_REGULATORMODE0      32
0084 #define MC13783_REG_REGULATORMODE0_VAUDIOEN     (1 << 0)
0085 #define MC13783_REG_REGULATORMODE0_VIOHIEN      (1 << 3)
0086 #define MC13783_REG_REGULATORMODE0_VIOLOEN      (1 << 6)
0087 #define MC13783_REG_REGULATORMODE0_VDIGEN       (1 << 9)
0088 #define MC13783_REG_REGULATORMODE0_VGENEN       (1 << 12)
0089 #define MC13783_REG_REGULATORMODE0_VRFDIGEN     (1 << 15)
0090 #define MC13783_REG_REGULATORMODE0_VRFREFEN     (1 << 18)
0091 #define MC13783_REG_REGULATORMODE0_VRFCPEN      (1 << 21)
0092
0093 #define MC13783_REG_REGULATORMODE1      33
0094 #define MC13783_REG_REGULATORMODE1_VSIMEN       (1 << 0)
0095 #define MC13783_REG_REGULATORMODE1_VESIMEN      (1 << 3)
0096 #define MC13783_REG_REGULATORMODE1_VCAMEN       (1 << 6)
0097 #define MC13783_REG_REGULATORMODE1_VRFBGEN      (1 << 9)
0098 #define MC13783_REG_REGULATORMODE1_VVIBEN       (1 << 11)
0099 #define MC13783_REG_REGULATORMODE1_VRF1EN       (1 << 12)
0100 #define MC13783_REG_REGULATORMODE1_VRF2EN       (1 << 15)
0101 #define MC13783_REG_REGULATORMODE1_VMMC1EN      (1 << 18)
0102 #define MC13783_REG_REGULATORMODE1_VMMC2EN      (1 << 21)
0103
0104 #define MC13783_REG_POWERMISC           34
0105 #define MC13783_REG_POWERMISC_GPO1EN            (1 << 6)
0106 #define MC13783_REG_POWERMISC_GPO2EN            (1 << 8)
0107 #define MC13783_REG_POWERMISC_GPO3EN            (1 << 10)
0108 #define MC13783_REG_POWERMISC_GPO4EN            (1 << 12)
0109 #define MC13783_REG_POWERMISC_PWGT1SPIEN        (1 << 15)
0110 #define MC13783_REG_POWERMISC_PWGT2SPIEN        (1 << 16)
0111
0112 #define MC13783_REG_POWERMISC_PWGTSPI_M         (3 << 15)
0113
0114
0115 /* Voltage Values */
0116 static const int mc13783_sw1x_val[] = {
0117     900000, 925000, 950000, 975000,
0118     1000000, 1025000, 1050000, 1075000,
0119     1100000, 1125000, 1150000, 1175000,
0120     1200000, 1225000, 1250000, 1275000,
0121     1300000, 1325000, 1350000, 1375000,
0122     1400000, 1425000, 1450000, 1475000,
0123     1500000, 1525000, 1550000, 1575000,
0124     1600000, 1625000, 1650000, 1675000,
0125     1700000, 1700000, 1700000, 1700000,
0126     1800000, 1800000, 1800000, 1800000,
0127     1850000, 1850000, 1850000, 1850000,
0128     2000000, 2000000, 2000000, 2000000,
0129     2100000, 2100000, 2100000, 2100000,
0130     2200000, 2200000, 2200000, 2200000,
0131     2200000, 2200000, 2200000, 2200000,
0132     2200000, 2200000, 2200000, 2200000,
0133 };
0134
0135 static const int mc13783_sw2x_val[] = {
0136     900000, 925000, 950000, 975000,
0137     1000000, 1025000, 1050000, 1075000,
0138     1100000, 1125000, 1150000, 1175000,
0139     1200000, 1225000, 1250000, 1275000,
0140     1300000, 1325000, 1350000, 1375000,
0141     1400000, 1425000, 1450000, 1475000,
0142     1500000, 1525000, 1550000, 1575000,
0143     1600000, 1625000, 1650000, 1675000,
0144     1700000, 1700000, 1700000, 1700000,
0145     1800000, 1800000, 1800000, 1800000,
0146     1900000, 1900000, 1900000, 1900000,
0147     2000000, 2000000, 2000000, 2000000,
0148     2100000, 2100000, 2100000, 2100000,
0149     2200000, 2200000, 2200000, 2200000,
0150     2200000, 2200000, 2200000, 2200000,
0151     2200000, 2200000, 2200000, 2200000,
0152 };
0153
0154 static const unsigned int mc13783_sw3_val[] = {
0155     5000000, 5000000, 5000000, 5500000,
0156 };
0157
0158 static const unsigned int mc13783_vaudio_val[] = {
0159     2775000,
0160 };
0161
0162 static const unsigned int mc13783_viohi_val[] = {
0163     2775000,
0164 };
0165
0166 static const unsigned int mc13783_violo_val[] = {
0167     1200000, 1300000, 1500000, 1800000,
0168 };
0169
0170 static const unsigned int mc13783_vdig_val[] = {
0171     1200000, 1300000, 1500000, 1800000,
0172 };
0173
0174 static const unsigned int mc13783_vgen_val[] = {
0175     1200000, 1300000, 1500000, 1800000,
0176     1100000, 2000000, 2775000, 2400000,
0177 };
0178
0179 static const unsigned int mc13783_vrfdig_val[] = {
0180     1200000, 1500000, 1800000, 1875000,
0181 };
0182
0183 static const unsigned int mc13783_vrfref_val[] = {
0184     2475000, 2600000, 2700000, 2775000,
0185 };
0186
0187 static const unsigned int mc13783_vrfcp_val[] = {
0188     2700000, 2775000,
0189 };
0190
0191 static const unsigned int mc13783_vsim_val[] = {
0192     1800000, 2900000, 3000000,
0193 };
0194
0195 static const unsigned int mc13783_vesim_val[] = {
0196     1800000, 2900000,
0197 };
0198
0199 static const unsigned int mc13783_vcam_val[] = {
0200     1500000, 1800000, 2500000, 2550000,
0201     2600000, 2750000, 2800000, 3000000,
0202 };
0203
0204 static const unsigned int mc13783_vrfbg_val[] = {
0205     1250000,
0206 };
0207
0208 static const unsigned int mc13783_vvib_val[] = {
0209     1300000, 1800000, 2000000, 3000000,
0210 };
0211
0212 static const unsigned int mc13783_vmmc_val[] = {
0213     1600000, 1800000, 2000000, 2600000,
0214     2700000, 2800000, 2900000, 3000000,
0215 };
0216
0217 static const unsigned int mc13783_vrf_val[] = {
0218     1500000, 1875000, 2700000, 2775000,
0219 };
0220
0221 static const unsigned int mc13783_gpo_val[] = {
0222     3100000,
0223 };
0224
0225 static const unsigned int mc13783_pwgtdrv_val[] = {
0226     5500000,
0227 };
0228
0229 static const struct regulator_ops mc13783_gpo_regulator_ops;
0230
0231 #define MC13783_DEFINE(prefix, name, node, reg, vsel_reg, voltages) \
0232     MC13xxx_DEFINE(MC13783_REG_, name, node, reg, vsel_reg, voltages, \
0233             mc13xxx_regulator_ops)
0234
0235 #define MC13783_FIXED_DEFINE(prefix, name, node, reg, voltages)     \
0236     MC13xxx_FIXED_DEFINE(MC13783_REG_, name, node, reg, voltages,   \
0237             mc13xxx_fixed_regulator_ops)
0238
0239 #define MC13783_GPO_DEFINE(prefix, name, node, reg, voltages)       \
0240     MC13xxx_GPO_DEFINE(MC13783_REG_, name, node, reg, voltages, \
0241             mc13783_gpo_regulator_ops)
0242
0243 #define MC13783_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages) \
0244     MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
0245 #define MC13783_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages)   \
0246     MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
0247
0248 static struct mc13xxx_regulator mc13783_regulators[] = {
0249     MC13783_DEFINE_SW(SW1A, sw1a, SWITCHERS0, SWITCHERS0, mc13783_sw1x_val),
0250     MC13783_DEFINE_SW(SW1B, sw1b, SWITCHERS1, SWITCHERS1, mc13783_sw1x_val),
0251     MC13783_DEFINE_SW(SW2A, sw2a, SWITCHERS2, SWITCHERS2, mc13783_sw2x_val),
0252     MC13783_DEFINE_SW(SW2B, sw2b, SWITCHERS3, SWITCHERS3, mc13783_sw2x_val),
0253     MC13783_DEFINE_SW(SW3, sw3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),
0254
0255     MC13783_FIXED_DEFINE(REG, VAUDIO, vaudio, REGULATORMODE0, mc13783_vaudio_val),
0256     MC13783_FIXED_DEFINE(REG, VIOHI, viohi, REGULATORMODE0, mc13783_viohi_val),
0257     MC13783_DEFINE_REGU(VIOLO, violo, REGULATORMODE0, REGULATORSETTING0,
0258                 mc13783_violo_val),
0259     MC13783_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0,
0260                 mc13783_vdig_val),
0261     MC13783_DEFINE_REGU(VGEN, vgen, REGULATORMODE0, REGULATORSETTING0,
0262                 mc13783_vgen_val),
0263     MC13783_DEFINE_REGU(VRFDIG, vrfdig, REGULATORMODE0, REGULATORSETTING0,
0264                 mc13783_vrfdig_val),
0265     MC13783_DEFINE_REGU(VRFREF, vrfref, REGULATORMODE0, REGULATORSETTING0,
0266                 mc13783_vrfref_val),
0267     MC13783_DEFINE_REGU(VRFCP, vrfcp, REGULATORMODE0, REGULATORSETTING0,
0268                 mc13783_vrfcp_val),
0269     MC13783_DEFINE_REGU(VSIM, vsim, REGULATORMODE1, REGULATORSETTING0,
0270                 mc13783_vsim_val),
0271     MC13783_DEFINE_REGU(VESIM, vesim, REGULATORMODE1, REGULATORSETTING0,
0272                 mc13783_vesim_val),
0273     MC13783_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0,
0274                 mc13783_vcam_val),
0275     MC13783_FIXED_DEFINE(REG, VRFBG, vrfbg, REGULATORMODE1, mc13783_vrfbg_val),
0276     MC13783_DEFINE_REGU(VVIB, vvib, REGULATORMODE1, REGULATORSETTING1,
0277                 mc13783_vvib_val),
0278     MC13783_DEFINE_REGU(VRF1, vrf1, REGULATORMODE1, REGULATORSETTING1,
0279                 mc13783_vrf_val),
0280     MC13783_DEFINE_REGU(VRF2, vrf2, REGULATORMODE1, REGULATORSETTING1,
0281                 mc13783_vrf_val),
0282     MC13783_DEFINE_REGU(VMMC1, vmmc1, REGULATORMODE1, REGULATORSETTING1,
0283                 mc13783_vmmc_val),
0284     MC13783_DEFINE_REGU(VMMC2, vmmc2, REGULATORMODE1, REGULATORSETTING1,
0285                 mc13783_vmmc_val),
0286     MC13783_GPO_DEFINE(REG, GPO1, gpo1, POWERMISC, mc13783_gpo_val),
0287     MC13783_GPO_DEFINE(REG, GPO2, gpo1, POWERMISC, mc13783_gpo_val),
0288     MC13783_GPO_DEFINE(REG, GPO3, gpo1, POWERMISC, mc13783_gpo_val),
0289     MC13783_GPO_DEFINE(REG, GPO4, gpo1, POWERMISC, mc13783_gpo_val),
0290     MC13783_GPO_DEFINE(REG, PWGT1SPI, pwgt1spi, POWERMISC, mc13783_pwgtdrv_val),
0291     MC13783_GPO_DEFINE(REG, PWGT2SPI, pwgt2spi, POWERMISC, mc13783_pwgtdrv_val),
0292 };
0293
0294 static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
0295         u32 val)
0296 {
0297     struct mc13xxx *mc13783 = priv->mc13xxx;
0298     int ret;
0299     u32 valread;
0300
0301     BUG_ON(val & ~mask);
0302
0303     mc13xxx_lock(priv->mc13xxx);
0304     ret = mc13xxx_reg_read(mc13783, MC13783_REG_POWERMISC, &valread);
0305     if (ret)
0306         goto out;
0307
0308     /* Update the stored state for Power Gates. */
0309     priv->powermisc_pwgt_state =
0310                 (priv->powermisc_pwgt_state & ~mask) | val;
0311     priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M;
0312
0313     /* Construct the new register value */
0314     valread = (valread & ~mask) | val;
0315     /* Overwrite the PWGTxEN with the stored version */
0316     valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
0317                         priv->powermisc_pwgt_state;
0318
0319     ret = mc13xxx_reg_write(mc13783, MC13783_REG_POWERMISC, valread);
0320 out:
0321     mc13xxx_unlock(priv->mc13xxx);
0322     return ret;
0323 }
0324
0325 static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev)
0326 {
0327     struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
0328     struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
0329     int id = rdev_get_id(rdev);
0330     u32 en_val = mc13xxx_regulators[id].enable_bit;
0331
0332     dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
0333
0334     /* Power Gate enable value is 0 */
0335     if (id == MC13783_REG_PWGT1SPI ||
0336         id == MC13783_REG_PWGT2SPI)
0337         en_val = 0;
0338
0339     return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
0340                     en_val);
0341 }
0342
0343 static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev)
0344 {
0345     struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
0346     struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
0347     int id = rdev_get_id(rdev);
0348     u32 dis_val = 0;
0349
0350     dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
0351
0352     /* Power Gate disable value is 1 */
0353     if (id == MC13783_REG_PWGT1SPI ||
0354         id == MC13783_REG_PWGT2SPI)
0355         dis_val = mc13xxx_regulators[id].enable_bit;
0356
0357     return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
0358                     dis_val);
0359 }
0360
0361 static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev)
0362 {
0363     struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
0364     struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
0365     int ret, id = rdev_get_id(rdev);
0366     unsigned int val;
0367
0368     mc13xxx_lock(priv->mc13xxx);
0369     ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
0370     mc13xxx_unlock(priv->mc13xxx);
0371
0372     if (ret)
0373         return ret;
0374
0375     /* Power Gates state is stored in powermisc_pwgt_state
0376      * where the meaning of bits is negated */
0377     val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
0378           (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M);
0379
0380     return (val & mc13xxx_regulators[id].enable_bit) != 0;
0381 }
0382
0383 static const struct regulator_ops mc13783_gpo_regulator_ops = {
0384     .enable = mc13783_gpo_regulator_enable,
0385     .disable = mc13783_gpo_regulator_disable,
0386     .is_enabled = mc13783_gpo_regulator_is_enabled,
0387     .list_voltage = regulator_list_voltage_table,
0388     .set_voltage = mc13xxx_fixed_regulator_set_voltage,
0389 };
0390
0391 static int mc13783_regulator_probe(struct platform_device *pdev)
0392 {
0393     struct mc13xxx_regulator_priv *priv;
0394     struct mc13xxx *mc13783 = dev_get_drvdata(pdev->dev.parent);
0395     struct mc13xxx_regulator_platform_data *pdata =
0396         dev_get_platdata(&pdev->dev);
0397     struct mc13xxx_regulator_init_data *mc13xxx_data;
0398     struct regulator_config config = { };
0399     int i, num_regulators;
0400
0401     num_regulators = mc13xxx_get_num_regulators_dt(pdev);
0402
0403     if (num_regulators <= 0 && pdata)
0404         num_regulators = pdata->num_regulators;
0405     if (num_regulators <= 0)
0406         return -EINVAL;
0407
0408     priv = devm_kzalloc(&pdev->dev,
0409                 struct_size(priv, regulators, num_regulators),
0410                 GFP_KERNEL);
0411     if (!priv)
0412         return -ENOMEM;
0413
0414     priv->num_regulators = num_regulators;
0415     priv->mc13xxx_regulators = mc13783_regulators;
0416     priv->mc13xxx = mc13783;
0417     platform_set_drvdata(pdev, priv);
0418
0419     mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13783_regulators,
0420                     ARRAY_SIZE(mc13783_regulators));
0421
0422     for (i = 0; i < priv->num_regulators; i++) {
0423         struct regulator_init_data *init_data;
0424         struct regulator_desc *desc;
0425         struct device_node *node = NULL;
0426         int id;
0427
0428         if (mc13xxx_data) {
0429             id = mc13xxx_data[i].id;
0430             init_data = mc13xxx_data[i].init_data;
0431             node = mc13xxx_data[i].node;
0432         } else {
0433             id = pdata->regulators[i].id;
0434             init_data = pdata->regulators[i].init_data;
0435         }
0436         desc = &mc13783_regulators[id].desc;
0437
0438         config.dev = &pdev->dev;
0439         config.init_data = init_data;
0440         config.driver_data = priv;
0441         config.of_node = node;
0442
0443         priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
0444                                   &config);
0445         if (IS_ERR(priv->regulators[i])) {
0446             dev_err(&pdev->dev, "failed to register regulator %s\n",
0447                 mc13783_regulators[i].desc.name);
0448             return PTR_ERR(priv->regulators[i]);
0449         }
0450     }
0451
0452     return 0;
0453 }
0454
0455 static struct platform_driver mc13783_regulator_driver = {
0456     .driver = {
0457         .name   = "mc13783-regulator",
0458     },
0459     .probe      = mc13783_regulator_probe,
0460 };
0461
0462 static int __init mc13783_regulator_init(void)
0463 {
0464     return platform_driver_register(&mc13783_regulator_driver);
0465 }
0466 subsys_initcall(mc13783_regulator_init);
0467
0468 static void __exit mc13783_regulator_exit(void)
0469 {
0470     platform_driver_unregister(&mc13783_regulator_driver);
0471 }
0472 module_exit(mc13783_regulator_exit);
0473
0474 MODULE_LICENSE("GPL v2");
0475 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
0476 MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC");
0477 MODULE_ALIAS("platform:mc13783-regulator");