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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Maxim MAX77620 Regulator driver
0004  *
0005  * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  * Author: Mallikarjun Kasoju <mkasoju@nvidia.com>
0008  *  Laxman Dewangan <ldewangan@nvidia.com>
0009  */
0010 
0011 #include <linux/init.h>
0012 #include <linux/mfd/max77620.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regmap.h>
0017 #include <linux/regulator/driver.h>
0018 #include <linux/regulator/machine.h>
0019 #include <linux/regulator/of_regulator.h>
0020 
0021 #define max77620_rails(_name)   "max77620-"#_name
0022 
0023 /* Power Mode */
0024 #define MAX77620_POWER_MODE_NORMAL      3
0025 #define MAX77620_POWER_MODE_LPM         2
0026 #define MAX77620_POWER_MODE_GLPM        1
0027 #define MAX77620_POWER_MODE_DISABLE     0
0028 
0029 /* SD Slew Rate */
0030 #define MAX77620_SD_SR_13_75            0
0031 #define MAX77620_SD_SR_27_5         1
0032 #define MAX77620_SD_SR_55           2
0033 #define MAX77620_SD_SR_100          3
0034 
0035 enum max77620_regulators {
0036     MAX77620_REGULATOR_ID_SD0,
0037     MAX77620_REGULATOR_ID_SD1,
0038     MAX77620_REGULATOR_ID_SD2,
0039     MAX77620_REGULATOR_ID_SD3,
0040     MAX77620_REGULATOR_ID_SD4,
0041     MAX77620_REGULATOR_ID_LDO0,
0042     MAX77620_REGULATOR_ID_LDO1,
0043     MAX77620_REGULATOR_ID_LDO2,
0044     MAX77620_REGULATOR_ID_LDO3,
0045     MAX77620_REGULATOR_ID_LDO4,
0046     MAX77620_REGULATOR_ID_LDO5,
0047     MAX77620_REGULATOR_ID_LDO6,
0048     MAX77620_REGULATOR_ID_LDO7,
0049     MAX77620_REGULATOR_ID_LDO8,
0050     MAX77620_NUM_REGS,
0051 };
0052 
0053 /* Regulator types */
0054 enum max77620_regulator_type {
0055     MAX77620_REGULATOR_TYPE_SD,
0056     MAX77620_REGULATOR_TYPE_LDO_N,
0057     MAX77620_REGULATOR_TYPE_LDO_P,
0058 };
0059 
0060 struct max77620_regulator_info {
0061     u8 type;
0062     u8 fps_addr;
0063     u8 volt_addr;
0064     u8 cfg_addr;
0065     u8 power_mode_mask;
0066     u8 power_mode_shift;
0067     u8 remote_sense_addr;
0068     u8 remote_sense_mask;
0069     struct regulator_desc desc;
0070 };
0071 
0072 struct max77620_regulator_pdata {
0073     int active_fps_src;
0074     int active_fps_pd_slot;
0075     int active_fps_pu_slot;
0076     int suspend_fps_src;
0077     int suspend_fps_pd_slot;
0078     int suspend_fps_pu_slot;
0079     int current_mode;
0080     int power_ok;
0081     int ramp_rate_setting;
0082 };
0083 
0084 struct max77620_regulator {
0085     struct device *dev;
0086     struct regmap *rmap;
0087     struct max77620_regulator_info *rinfo[MAX77620_NUM_REGS];
0088     struct max77620_regulator_pdata reg_pdata[MAX77620_NUM_REGS];
0089     int enable_power_mode[MAX77620_NUM_REGS];
0090     int current_power_mode[MAX77620_NUM_REGS];
0091     int active_fps_src[MAX77620_NUM_REGS];
0092 };
0093 
0094 #define fps_src_name(fps_src)   \
0095     (fps_src == MAX77620_FPS_SRC_0 ? "FPS_SRC_0" :  \
0096     fps_src == MAX77620_FPS_SRC_1 ? "FPS_SRC_1" :   \
0097     fps_src == MAX77620_FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
0098 
0099 static int max77620_regulator_get_fps_src(struct max77620_regulator *pmic,
0100                       int id)
0101 {
0102     struct max77620_regulator_info *rinfo = pmic->rinfo[id];
0103     unsigned int val;
0104     int ret;
0105 
0106     ret = regmap_read(pmic->rmap, rinfo->fps_addr, &val);
0107     if (ret < 0) {
0108         dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
0109             rinfo->fps_addr, ret);
0110         return ret;
0111     }
0112 
0113     return (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
0114 }
0115 
0116 static int max77620_regulator_set_fps_src(struct max77620_regulator *pmic,
0117                       int fps_src, int id)
0118 {
0119     struct max77620_regulator_info *rinfo = pmic->rinfo[id];
0120     unsigned int val;
0121     int ret;
0122 
0123     if (!rinfo)
0124         return 0;
0125 
0126     switch (fps_src) {
0127     case MAX77620_FPS_SRC_0:
0128     case MAX77620_FPS_SRC_1:
0129     case MAX77620_FPS_SRC_2:
0130     case MAX77620_FPS_SRC_NONE:
0131         break;
0132 
0133     case MAX77620_FPS_SRC_DEF:
0134         ret = regmap_read(pmic->rmap, rinfo->fps_addr, &val);
0135         if (ret < 0) {
0136             dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
0137                 rinfo->fps_addr, ret);
0138             return ret;
0139         }
0140         ret = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
0141         pmic->active_fps_src[id] = ret;
0142         return 0;
0143 
0144     default:
0145         dev_err(pmic->dev, "Invalid FPS %d for regulator %d\n",
0146             fps_src, id);
0147         return -EINVAL;
0148     }
0149 
0150     ret = regmap_update_bits(pmic->rmap, rinfo->fps_addr,
0151                  MAX77620_FPS_SRC_MASK,
0152                  fps_src << MAX77620_FPS_SRC_SHIFT);
0153     if (ret < 0) {
0154         dev_err(pmic->dev, "Reg 0x%02x update failed %d\n",
0155             rinfo->fps_addr, ret);
0156         return ret;
0157     }
0158     pmic->active_fps_src[id] = fps_src;
0159 
0160     return 0;
0161 }
0162 
0163 static int max77620_regulator_set_fps_slots(struct max77620_regulator *pmic,
0164                         int id, bool is_suspend)
0165 {
0166     struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
0167     struct max77620_regulator_info *rinfo = pmic->rinfo[id];
0168     unsigned int val = 0;
0169     unsigned int mask = 0;
0170     int pu = rpdata->active_fps_pu_slot;
0171     int pd = rpdata->active_fps_pd_slot;
0172     int ret = 0;
0173 
0174     if (!rinfo)
0175         return 0;
0176 
0177     if (is_suspend) {
0178         pu = rpdata->suspend_fps_pu_slot;
0179         pd = rpdata->suspend_fps_pd_slot;
0180     }
0181 
0182     /* FPS power up period setting */
0183     if (pu >= 0) {
0184         val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT);
0185         mask |= MAX77620_FPS_PU_PERIOD_MASK;
0186     }
0187 
0188     /* FPS power down period setting */
0189     if (pd >= 0) {
0190         val |= (pd << MAX77620_FPS_PD_PERIOD_SHIFT);
0191         mask |= MAX77620_FPS_PD_PERIOD_MASK;
0192     }
0193 
0194     if (mask) {
0195         ret = regmap_update_bits(pmic->rmap, rinfo->fps_addr,
0196                      mask, val);
0197         if (ret < 0) {
0198             dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
0199                 rinfo->fps_addr, ret);
0200             return ret;
0201         }
0202     }
0203 
0204     return ret;
0205 }
0206 
0207 static int max77620_regulator_set_power_mode(struct max77620_regulator *pmic,
0208                          int power_mode, int id)
0209 {
0210     struct max77620_regulator_info *rinfo = pmic->rinfo[id];
0211     u8 mask = rinfo->power_mode_mask;
0212     u8 shift = rinfo->power_mode_shift;
0213     u8 addr;
0214     int ret;
0215 
0216     switch (rinfo->type) {
0217     case MAX77620_REGULATOR_TYPE_SD:
0218         addr = rinfo->cfg_addr;
0219         break;
0220     default:
0221         addr = rinfo->volt_addr;
0222         break;
0223     }
0224 
0225     ret = regmap_update_bits(pmic->rmap, addr, mask, power_mode << shift);
0226     if (ret < 0) {
0227         dev_err(pmic->dev, "Regulator %d mode set failed: %d\n",
0228             id, ret);
0229         return ret;
0230     }
0231     pmic->current_power_mode[id] = power_mode;
0232 
0233     return ret;
0234 }
0235 
0236 static int max77620_regulator_get_power_mode(struct max77620_regulator *pmic,
0237                          int id)
0238 {
0239     struct max77620_regulator_info *rinfo = pmic->rinfo[id];
0240     unsigned int val, addr;
0241     u8 mask = rinfo->power_mode_mask;
0242     u8 shift = rinfo->power_mode_shift;
0243     int ret;
0244 
0245     switch (rinfo->type) {
0246     case MAX77620_REGULATOR_TYPE_SD:
0247         addr = rinfo->cfg_addr;
0248         break;
0249     default:
0250         addr = rinfo->volt_addr;
0251         break;
0252     }
0253 
0254     ret = regmap_read(pmic->rmap, addr, &val);
0255     if (ret < 0) {
0256         dev_err(pmic->dev, "Regulator %d: Reg 0x%02x read failed: %d\n",
0257             id, addr, ret);
0258         return ret;
0259     }
0260 
0261     return (val & mask) >> shift;
0262 }
0263 
0264 static int max77620_read_slew_rate(struct max77620_regulator *pmic, int id)
0265 {
0266     struct max77620_regulator_info *rinfo = pmic->rinfo[id];
0267     unsigned int rval;
0268     int slew_rate;
0269     int ret;
0270 
0271     ret = regmap_read(pmic->rmap, rinfo->cfg_addr, &rval);
0272     if (ret < 0) {
0273         dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
0274             rinfo->cfg_addr, ret);
0275         return ret;
0276     }
0277 
0278     switch (rinfo->type) {
0279     case MAX77620_REGULATOR_TYPE_SD:
0280         slew_rate = (rval >> MAX77620_SD_SR_SHIFT) & 0x3;
0281         switch (slew_rate) {
0282         case 0:
0283             slew_rate = 13750;
0284             break;
0285         case 1:
0286             slew_rate = 27500;
0287             break;
0288         case 2:
0289             slew_rate = 55000;
0290             break;
0291         case 3:
0292             slew_rate = 100000;
0293             break;
0294         }
0295         rinfo->desc.ramp_delay = slew_rate;
0296         break;
0297     default:
0298         slew_rate = rval & 0x1;
0299         switch (slew_rate) {
0300         case 0:
0301             slew_rate = 100000;
0302             break;
0303         case 1:
0304             slew_rate = 5000;
0305             break;
0306         }
0307         rinfo->desc.ramp_delay = slew_rate;
0308         break;
0309     }
0310 
0311     return 0;
0312 }
0313 
0314 static int max77620_set_slew_rate(struct max77620_regulator *pmic, int id,
0315                   int slew_rate)
0316 {
0317     struct max77620_regulator_info *rinfo = pmic->rinfo[id];
0318     unsigned int val;
0319     int ret;
0320     u8 mask;
0321 
0322     if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
0323         if (slew_rate <= 13750)
0324             val = 0;
0325         else if (slew_rate <= 27500)
0326             val = 1;
0327         else if (slew_rate <= 55000)
0328             val = 2;
0329         else
0330             val = 3;
0331         val <<= MAX77620_SD_SR_SHIFT;
0332         mask = MAX77620_SD_SR_MASK;
0333     } else {
0334         if (slew_rate <= 5000)
0335             val = 1;
0336         else
0337             val = 0;
0338         mask = MAX77620_LDO_SLEW_RATE_MASK;
0339     }
0340 
0341     ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr, mask, val);
0342     if (ret < 0) {
0343         dev_err(pmic->dev, "Regulator %d slew rate set failed: %d\n",
0344             id, ret);
0345         return ret;
0346     }
0347 
0348     return 0;
0349 }
0350 
0351 static int max77620_config_power_ok(struct max77620_regulator *pmic, int id)
0352 {
0353     struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
0354     struct max77620_regulator_info *rinfo = pmic->rinfo[id];
0355     struct max77620_chip *chip = dev_get_drvdata(pmic->dev->parent);
0356     u8 val, mask;
0357     int ret;
0358 
0359     switch (chip->chip_id) {
0360     case MAX20024:
0361         if (rpdata->power_ok >= 0) {
0362             if (rinfo->type == MAX77620_REGULATOR_TYPE_SD)
0363                 mask = MAX20024_SD_CFG1_MPOK_MASK;
0364             else
0365                 mask = MAX20024_LDO_CFG2_MPOK_MASK;
0366 
0367             val = rpdata->power_ok ? mask : 0;
0368 
0369             ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr,
0370                          mask, val);
0371             if (ret < 0) {
0372                 dev_err(pmic->dev, "Reg 0x%02x update failed %d\n",
0373                     rinfo->cfg_addr, ret);
0374                 return ret;
0375             }
0376         }
0377         break;
0378 
0379     default:
0380         break;
0381     }
0382 
0383     return 0;
0384 }
0385 
0386 static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
0387 {
0388     struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
0389     int ret;
0390 
0391     max77620_config_power_ok(pmic, id);
0392 
0393     /* Update power mode */
0394     ret = max77620_regulator_get_power_mode(pmic, id);
0395     if (ret < 0)
0396         return ret;
0397 
0398     pmic->current_power_mode[id] = ret;
0399     pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
0400 
0401     if (rpdata->active_fps_src == MAX77620_FPS_SRC_DEF) {
0402         ret = max77620_regulator_get_fps_src(pmic, id);
0403         if (ret < 0)
0404             return ret;
0405         rpdata->active_fps_src = ret;
0406     }
0407 
0408      /* If rails are externally control of FPS then enable it always. */
0409     if (rpdata->active_fps_src == MAX77620_FPS_SRC_NONE) {
0410         ret = max77620_regulator_set_power_mode(pmic,
0411                     pmic->enable_power_mode[id], id);
0412         if (ret < 0)
0413             return ret;
0414     } else {
0415         if (pmic->current_power_mode[id] !=
0416              pmic->enable_power_mode[id]) {
0417             ret = max77620_regulator_set_power_mode(pmic,
0418                     pmic->enable_power_mode[id], id);
0419             if (ret < 0)
0420                 return ret;
0421         }
0422     }
0423 
0424     ret = max77620_regulator_set_fps_src(pmic, rpdata->active_fps_src, id);
0425     if (ret < 0)
0426         return ret;
0427 
0428     ret = max77620_regulator_set_fps_slots(pmic, id, false);
0429     if (ret < 0)
0430         return ret;
0431 
0432     if (rpdata->ramp_rate_setting) {
0433         ret = max77620_set_slew_rate(pmic, id,
0434                          rpdata->ramp_rate_setting);
0435         if (ret < 0)
0436             return ret;
0437     }
0438 
0439     return 0;
0440 }
0441 
0442 static int max77620_regulator_enable(struct regulator_dev *rdev)
0443 {
0444     struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
0445     int id = rdev_get_id(rdev);
0446 
0447     if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE)
0448         return 0;
0449 
0450     return max77620_regulator_set_power_mode(pmic,
0451             pmic->enable_power_mode[id], id);
0452 }
0453 
0454 static int max77620_regulator_disable(struct regulator_dev *rdev)
0455 {
0456     struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
0457     int id = rdev_get_id(rdev);
0458 
0459     if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE)
0460         return 0;
0461 
0462     return max77620_regulator_set_power_mode(pmic,
0463             MAX77620_POWER_MODE_DISABLE, id);
0464 }
0465 
0466 static int max77620_regulator_is_enabled(struct regulator_dev *rdev)
0467 {
0468     struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
0469     int id = rdev_get_id(rdev);
0470     int ret;
0471 
0472     if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE)
0473         return 1;
0474 
0475     ret = max77620_regulator_get_power_mode(pmic, id);
0476     if (ret < 0)
0477         return ret;
0478 
0479     if (ret != MAX77620_POWER_MODE_DISABLE)
0480         return 1;
0481 
0482     return 0;
0483 }
0484 
0485 static int max77620_regulator_set_mode(struct regulator_dev *rdev,
0486                        unsigned int mode)
0487 {
0488     struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
0489     int id = rdev_get_id(rdev);
0490     struct max77620_regulator_info *rinfo = pmic->rinfo[id];
0491     struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
0492     bool fpwm = false;
0493     int power_mode;
0494     int ret;
0495     u8 val;
0496 
0497     switch (mode) {
0498     case REGULATOR_MODE_FAST:
0499         fpwm = true;
0500         power_mode = MAX77620_POWER_MODE_NORMAL;
0501         break;
0502 
0503     case REGULATOR_MODE_NORMAL:
0504         power_mode = MAX77620_POWER_MODE_NORMAL;
0505         break;
0506 
0507     case REGULATOR_MODE_IDLE:
0508         power_mode = MAX77620_POWER_MODE_LPM;
0509         break;
0510 
0511     default:
0512         dev_err(pmic->dev, "Regulator %d mode %d is invalid\n",
0513             id, mode);
0514         return -EINVAL;
0515     }
0516 
0517     if (rinfo->type != MAX77620_REGULATOR_TYPE_SD)
0518         goto skip_fpwm;
0519 
0520     val = (fpwm) ? MAX77620_SD_FPWM_MASK : 0;
0521     ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr,
0522                  MAX77620_SD_FPWM_MASK, val);
0523     if (ret < 0) {
0524         dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
0525             rinfo->cfg_addr, ret);
0526         return ret;
0527     }
0528     rpdata->current_mode = mode;
0529 
0530 skip_fpwm:
0531     ret = max77620_regulator_set_power_mode(pmic, power_mode, id);
0532     if (ret < 0)
0533         return ret;
0534 
0535     pmic->enable_power_mode[id] = power_mode;
0536 
0537     return 0;
0538 }
0539 
0540 static unsigned int max77620_regulator_get_mode(struct regulator_dev *rdev)
0541 {
0542     struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
0543     int id = rdev_get_id(rdev);
0544     struct max77620_regulator_info *rinfo = pmic->rinfo[id];
0545     int fpwm = 0;
0546     int ret;
0547     int pm_mode, reg_mode;
0548     unsigned int val;
0549 
0550     ret = max77620_regulator_get_power_mode(pmic, id);
0551     if (ret < 0)
0552         return 0;
0553 
0554     pm_mode = ret;
0555 
0556     if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
0557         ret = regmap_read(pmic->rmap, rinfo->cfg_addr, &val);
0558         if (ret < 0) {
0559             dev_err(pmic->dev, "Reg 0x%02x read failed: %d\n",
0560                 rinfo->cfg_addr, ret);
0561             return ret;
0562         }
0563         fpwm = !!(val & MAX77620_SD_FPWM_MASK);
0564     }
0565 
0566     switch (pm_mode) {
0567     case MAX77620_POWER_MODE_NORMAL:
0568     case MAX77620_POWER_MODE_DISABLE:
0569         if (fpwm)
0570             reg_mode = REGULATOR_MODE_FAST;
0571         else
0572             reg_mode = REGULATOR_MODE_NORMAL;
0573         break;
0574     case MAX77620_POWER_MODE_LPM:
0575     case MAX77620_POWER_MODE_GLPM:
0576         reg_mode = REGULATOR_MODE_IDLE;
0577         break;
0578     default:
0579         return 0;
0580     }
0581 
0582     return reg_mode;
0583 }
0584 
0585 static int max77620_regulator_set_ramp_delay(struct regulator_dev *rdev,
0586                          int ramp_delay)
0587 {
0588     struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
0589     int id = rdev_get_id(rdev);
0590     struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
0591 
0592     /* Device specific ramp rate setting tells that platform has
0593      * different ramp rate from advertised value. In this case,
0594      * do not configure anything and just return success.
0595      */
0596     if (rpdata->ramp_rate_setting)
0597         return 0;
0598 
0599     return max77620_set_slew_rate(pmic, id, ramp_delay);
0600 }
0601 
0602 static int max77620_of_parse_cb(struct device_node *np,
0603                 const struct regulator_desc *desc,
0604                 struct regulator_config *config)
0605 {
0606     struct max77620_regulator *pmic = config->driver_data;
0607     struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[desc->id];
0608     u32 pval;
0609     int ret;
0610 
0611     ret = of_property_read_u32(np, "maxim,active-fps-source", &pval);
0612     rpdata->active_fps_src = (!ret) ? pval : MAX77620_FPS_SRC_DEF;
0613 
0614     ret = of_property_read_u32(np, "maxim,active-fps-power-up-slot", &pval);
0615     rpdata->active_fps_pu_slot = (!ret) ? pval : -1;
0616 
0617     ret = of_property_read_u32(
0618             np, "maxim,active-fps-power-down-slot", &pval);
0619     rpdata->active_fps_pd_slot = (!ret) ? pval : -1;
0620 
0621     ret = of_property_read_u32(np, "maxim,suspend-fps-source", &pval);
0622     rpdata->suspend_fps_src = (!ret) ? pval : -1;
0623 
0624     ret = of_property_read_u32(
0625             np, "maxim,suspend-fps-power-up-slot", &pval);
0626     rpdata->suspend_fps_pu_slot = (!ret) ? pval : -1;
0627 
0628     ret = of_property_read_u32(
0629             np, "maxim,suspend-fps-power-down-slot", &pval);
0630     rpdata->suspend_fps_pd_slot = (!ret) ? pval : -1;
0631 
0632     ret = of_property_read_u32(np, "maxim,power-ok-control", &pval);
0633     if (!ret)
0634         rpdata->power_ok = pval;
0635     else
0636         rpdata->power_ok = -1;
0637 
0638     ret = of_property_read_u32(np, "maxim,ramp-rate-setting", &pval);
0639     rpdata->ramp_rate_setting = (!ret) ? pval : 0;
0640 
0641     return max77620_init_pmic(pmic, desc->id);
0642 }
0643 
0644 static const struct regulator_ops max77620_regulator_ops = {
0645     .is_enabled = max77620_regulator_is_enabled,
0646     .enable = max77620_regulator_enable,
0647     .disable = max77620_regulator_disable,
0648     .list_voltage = regulator_list_voltage_linear,
0649     .map_voltage = regulator_map_voltage_linear,
0650     .get_voltage_sel = regulator_get_voltage_sel_regmap,
0651     .set_voltage_sel = regulator_set_voltage_sel_regmap,
0652     .set_mode = max77620_regulator_set_mode,
0653     .get_mode = max77620_regulator_get_mode,
0654     .set_ramp_delay = max77620_regulator_set_ramp_delay,
0655     .set_voltage_time_sel = regulator_set_voltage_time_sel,
0656     .set_active_discharge = regulator_set_active_discharge_regmap,
0657 };
0658 
0659 #define MAX77620_SD_CNF2_ROVS_EN_NONE   0
0660 #define RAIL_SD(_id, _name, _sname, _volt_mask, _min_uV, _max_uV,   \
0661         _step_uV, _rs_add, _rs_mask)                \
0662     [MAX77620_REGULATOR_ID_##_id] = {               \
0663         .type = MAX77620_REGULATOR_TYPE_SD,         \
0664         .volt_addr = MAX77620_REG_##_id,            \
0665         .cfg_addr = MAX77620_REG_##_id##_CFG,           \
0666         .fps_addr = MAX77620_REG_FPS_##_id,         \
0667         .remote_sense_addr = _rs_add,               \
0668         .remote_sense_mask = MAX77620_SD_CNF2_ROVS_EN_##_rs_mask, \
0669         .power_mode_mask = MAX77620_SD_POWER_MODE_MASK,     \
0670         .power_mode_shift = MAX77620_SD_POWER_MODE_SHIFT,   \
0671         .desc = {                       \
0672             .name = max77620_rails(_name),          \
0673             .of_match = of_match_ptr(#_name),       \
0674             .regulators_node = of_match_ptr("regulators"),  \
0675             .of_parse_cb = max77620_of_parse_cb,        \
0676             .supply_name = _sname,              \
0677             .id = MAX77620_REGULATOR_ID_##_id,      \
0678             .ops = &max77620_regulator_ops,         \
0679             .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
0680             .min_uV = _min_uV,              \
0681             .uV_step = _step_uV,                \
0682             .enable_time = 500,             \
0683             .vsel_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
0684             .vsel_reg = MAX77620_REG_##_id,         \
0685             .active_discharge_off = 0,          \
0686             .active_discharge_on = MAX77620_SD_CFG1_ADE_ENABLE, \
0687             .active_discharge_mask = MAX77620_SD_CFG1_ADE_MASK, \
0688             .active_discharge_reg = MAX77620_REG_##_id##_CFG, \
0689             .type = REGULATOR_VOLTAGE,          \
0690             .owner = THIS_MODULE,               \
0691         },                          \
0692     }
0693 
0694 #define RAIL_LDO(_id, _name, _sname, _type, _min_uV, _max_uV, _step_uV) \
0695     [MAX77620_REGULATOR_ID_##_id] = {               \
0696         .type = MAX77620_REGULATOR_TYPE_LDO_##_type,        \
0697         .volt_addr = MAX77620_REG_##_id##_CFG,          \
0698         .cfg_addr = MAX77620_REG_##_id##_CFG2,          \
0699         .fps_addr = MAX77620_REG_FPS_##_id,         \
0700         .remote_sense_addr = 0xFF,              \
0701         .power_mode_mask = MAX77620_LDO_POWER_MODE_MASK,    \
0702         .power_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT,  \
0703         .desc = {                       \
0704             .name = max77620_rails(_name),          \
0705             .of_match = of_match_ptr(#_name),       \
0706             .regulators_node = of_match_ptr("regulators"),  \
0707             .of_parse_cb = max77620_of_parse_cb,        \
0708             .supply_name = _sname,              \
0709             .id = MAX77620_REGULATOR_ID_##_id,      \
0710             .ops = &max77620_regulator_ops,         \
0711             .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
0712             .min_uV = _min_uV,              \
0713             .uV_step = _step_uV,                \
0714             .enable_time = 500,             \
0715             .vsel_mask = MAX77620_LDO_VOLT_MASK,        \
0716             .vsel_reg = MAX77620_REG_##_id##_CFG,       \
0717             .active_discharge_off = 0,          \
0718             .active_discharge_on = MAX77620_LDO_CFG2_ADE_ENABLE, \
0719             .active_discharge_mask = MAX77620_LDO_CFG2_ADE_MASK, \
0720             .active_discharge_reg = MAX77620_REG_##_id##_CFG2, \
0721             .type = REGULATOR_VOLTAGE,          \
0722             .owner = THIS_MODULE,               \
0723         },                          \
0724     }
0725 
0726 static struct max77620_regulator_info max77620_regs_info[MAX77620_NUM_REGS] = {
0727     RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 1400000, 12500, 0x22, SD0),
0728     RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 1550000, 12500, 0x22, SD1),
0729     RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
0730     RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
0731 
0732     RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
0733     RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
0734     RAIL_LDO(LDO2, ldo2, "in-ldo2",   P, 800000, 3950000, 50000),
0735     RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
0736     RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
0737     RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
0738     RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
0739     RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
0740     RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
0741 };
0742 
0743 static struct max77620_regulator_info max20024_regs_info[MAX77620_NUM_REGS] = {
0744     RAIL_SD(SD0, sd0, "in-sd0", SD0, 800000, 1587500, 12500, 0x22, SD0),
0745     RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 3387500, 12500, 0x22, SD1),
0746     RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
0747     RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
0748     RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
0749 
0750     RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
0751     RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
0752     RAIL_LDO(LDO2, ldo2, "in-ldo2",   P, 800000, 3950000, 50000),
0753     RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
0754     RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
0755     RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
0756     RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
0757     RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
0758     RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
0759 };
0760 
0761 static struct max77620_regulator_info max77663_regs_info[MAX77620_NUM_REGS] = {
0762     RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 3387500, 12500, 0xFF, NONE),
0763     RAIL_SD(SD1, sd1, "in-sd1", SD1, 800000, 1587500, 12500, 0xFF, NONE),
0764     RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
0765     RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
0766     RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
0767 
0768     RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
0769     RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
0770     RAIL_LDO(LDO2, ldo2, "in-ldo2",   P, 800000, 3950000, 50000),
0771     RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
0772     RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
0773     RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
0774     RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
0775     RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
0776     RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
0777 };
0778 
0779 static int max77620_regulator_probe(struct platform_device *pdev)
0780 {
0781     struct max77620_chip *max77620_chip = dev_get_drvdata(pdev->dev.parent);
0782     struct max77620_regulator_info *rinfo;
0783     struct device *dev = &pdev->dev;
0784     struct regulator_config config = { };
0785     struct max77620_regulator *pmic;
0786     int ret = 0;
0787     int id;
0788 
0789     pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
0790     if (!pmic)
0791         return -ENOMEM;
0792 
0793     platform_set_drvdata(pdev, pmic);
0794     pmic->dev = dev;
0795     pmic->rmap = max77620_chip->rmap;
0796     if (!dev->of_node)
0797         dev->of_node = pdev->dev.parent->of_node;
0798 
0799     switch (max77620_chip->chip_id) {
0800     case MAX77620:
0801         rinfo = max77620_regs_info;
0802         break;
0803     case MAX20024:
0804         rinfo = max20024_regs_info;
0805         break;
0806     case MAX77663:
0807         rinfo = max77663_regs_info;
0808         break;
0809     default:
0810         return -EINVAL;
0811     }
0812 
0813     config.regmap = pmic->rmap;
0814     config.dev = dev;
0815     config.driver_data = pmic;
0816 
0817     /*
0818      * Set of_node_reuse flag to prevent driver core from attempting to
0819      * claim any pinmux resources already claimed by the parent device.
0820      * Otherwise PMIC driver will fail to re-probe.
0821      */
0822     device_set_of_node_from_dev(&pdev->dev, pdev->dev.parent);
0823 
0824     for (id = 0; id < MAX77620_NUM_REGS; id++) {
0825         struct regulator_dev *rdev;
0826         struct regulator_desc *rdesc;
0827 
0828         if ((max77620_chip->chip_id == MAX77620) &&
0829             (id == MAX77620_REGULATOR_ID_SD4))
0830             continue;
0831 
0832         rdesc = &rinfo[id].desc;
0833         pmic->rinfo[id] = &rinfo[id];
0834         pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
0835         pmic->reg_pdata[id].active_fps_src = -1;
0836         pmic->reg_pdata[id].active_fps_pd_slot = -1;
0837         pmic->reg_pdata[id].active_fps_pu_slot = -1;
0838         pmic->reg_pdata[id].suspend_fps_src = -1;
0839         pmic->reg_pdata[id].suspend_fps_pd_slot = -1;
0840         pmic->reg_pdata[id].suspend_fps_pu_slot = -1;
0841         pmic->reg_pdata[id].power_ok = -1;
0842         pmic->reg_pdata[id].ramp_rate_setting = -1;
0843 
0844         ret = max77620_read_slew_rate(pmic, id);
0845         if (ret < 0)
0846             return ret;
0847 
0848         rdev = devm_regulator_register(dev, rdesc, &config);
0849         if (IS_ERR(rdev))
0850             return dev_err_probe(dev, PTR_ERR(rdev),
0851                          "Regulator registration %s failed\n",
0852                          rdesc->name);
0853     }
0854 
0855     return 0;
0856 }
0857 
0858 #ifdef CONFIG_PM_SLEEP
0859 static int max77620_regulator_suspend(struct device *dev)
0860 {
0861     struct max77620_regulator *pmic = dev_get_drvdata(dev);
0862     struct max77620_regulator_pdata *reg_pdata;
0863     int id;
0864 
0865     for (id = 0; id < MAX77620_NUM_REGS; id++) {
0866         reg_pdata = &pmic->reg_pdata[id];
0867 
0868         max77620_regulator_set_fps_slots(pmic, id, true);
0869         if (reg_pdata->suspend_fps_src < 0)
0870             continue;
0871 
0872         max77620_regulator_set_fps_src(pmic, reg_pdata->suspend_fps_src,
0873                            id);
0874     }
0875 
0876     return 0;
0877 }
0878 
0879 static int max77620_regulator_resume(struct device *dev)
0880 {
0881     struct max77620_regulator *pmic = dev_get_drvdata(dev);
0882     struct max77620_regulator_pdata *reg_pdata;
0883     int id;
0884 
0885     for (id = 0; id < MAX77620_NUM_REGS; id++) {
0886         reg_pdata = &pmic->reg_pdata[id];
0887 
0888         max77620_config_power_ok(pmic, id);
0889 
0890         max77620_regulator_set_fps_slots(pmic, id, false);
0891         if (reg_pdata->active_fps_src < 0)
0892             continue;
0893         max77620_regulator_set_fps_src(pmic, reg_pdata->active_fps_src,
0894                            id);
0895     }
0896 
0897     return 0;
0898 }
0899 #endif
0900 
0901 static const struct dev_pm_ops max77620_regulator_pm_ops = {
0902     SET_SYSTEM_SLEEP_PM_OPS(max77620_regulator_suspend,
0903                 max77620_regulator_resume)
0904 };
0905 
0906 static const struct platform_device_id max77620_regulator_devtype[] = {
0907     { .name = "max77620-pmic", },
0908     { .name = "max20024-pmic", },
0909     { .name = "max77663-pmic", },
0910     {},
0911 };
0912 MODULE_DEVICE_TABLE(platform, max77620_regulator_devtype);
0913 
0914 static struct platform_driver max77620_regulator_driver = {
0915     .probe = max77620_regulator_probe,
0916     .id_table = max77620_regulator_devtype,
0917     .driver = {
0918         .name = "max77620-pmic",
0919         .pm = &max77620_regulator_pm_ops,
0920     },
0921 };
0922 
0923 module_platform_driver(max77620_regulator_driver);
0924 
0925 MODULE_DESCRIPTION("MAX77620/MAX20024 regulator driver");
0926 MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>");
0927 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
0928 MODULE_LICENSE("GPL v2");
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