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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Motorola CPCAP PMIC regulator driver
0004  *
0005  * Based on cpcap-regulator.c from Motorola Linux kernel tree
0006  * Copyright (C) 2009-2011 Motorola, Inc.
0007  *
0008  * Rewritten for mainline kernel to use device tree and regmap
0009  * Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
0010  */
0011 
0012 #include <linux/err.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/regmap.h>
0017 #include <linux/regulator/driver.h>
0018 #include <linux/regulator/machine.h>
0019 #include <linux/regulator/of_regulator.h>
0020 #include <linux/mfd/motorola-cpcap.h>
0021 
0022 /*
0023  * Resource assignment register bits. These seem to control the state
0024  * idle modes adn are used at least for omap4.
0025  */
0026 
0027 /* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */
0028 #define CPCAP_BIT_VSDIO_SEL     BIT(15)
0029 #define CPCAP_BIT_VDIG_SEL      BIT(14)
0030 #define CPCAP_BIT_VCAM_SEL      BIT(13)
0031 #define CPCAP_BIT_SW6_SEL       BIT(12)
0032 #define CPCAP_BIT_SW5_SEL       BIT(11)
0033 #define CPCAP_BIT_SW4_SEL       BIT(10)
0034 #define CPCAP_BIT_SW3_SEL       BIT(9)
0035 #define CPCAP_BIT_SW2_SEL       BIT(8)
0036 #define CPCAP_BIT_SW1_SEL       BIT(7)
0037 
0038 /* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */
0039 #define CPCAP_BIT_VUSBINT2_SEL      BIT(15)
0040 #define CPCAP_BIT_VUSBINT1_SEL      BIT(14)
0041 #define CPCAP_BIT_VVIB_SEL      BIT(13)
0042 #define CPCAP_BIT_VWLAN1_SEL        BIT(12)
0043 #define CPCAP_BIT_VRF1_SEL      BIT(11)
0044 #define CPCAP_BIT_VHVIO_SEL     BIT(10)
0045 #define CPCAP_BIT_VDAC_SEL      BIT(9)
0046 #define CPCAP_BIT_VUSB_SEL      BIT(8)
0047 #define CPCAP_BIT_VSIM_SEL      BIT(7)
0048 #define CPCAP_BIT_VRFREF_SEL        BIT(6)
0049 #define CPCAP_BIT_VPLL_SEL      BIT(5)
0050 #define CPCAP_BIT_VFUSE_SEL     BIT(4)
0051 #define CPCAP_BIT_VCSI_SEL      BIT(3)
0052 #define CPCAP_BIT_SPARE_14_2        BIT(2)
0053 #define CPCAP_BIT_VWLAN2_SEL        BIT(1)
0054 #define CPCAP_BIT_VRF2_SEL      BIT(0)
0055 
0056 /* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */
0057 #define CPCAP_BIT_VAUDIO_SEL        BIT(0)
0058 
0059 /*
0060  * Enable register bits. At least CPCAP_BIT_AUDIO_LOW_PWR is generic,
0061  * and not limited to audio regulator. Let's use the Motorola kernel
0062  * naming for now until we have a better understanding of the other
0063  * enable register bits. No idea why BIT(3) is not defined.
0064  */
0065 #define CPCAP_BIT_AUDIO_LOW_PWR     BIT(6)
0066 #define CPCAP_BIT_AUD_LOWPWR_SPEED  BIT(5)
0067 #define CPCAP_BIT_VAUDIOPRISTBY     BIT(4)
0068 #define CPCAP_BIT_VAUDIO_MODE1      BIT(2)
0069 #define CPCAP_BIT_VAUDIO_MODE0      BIT(1)
0070 #define CPCAP_BIT_V_AUDIO_EN        BIT(0)
0071 
0072 #define CPCAP_BIT_AUDIO_NORMAL_MODE 0x00
0073 
0074 /*
0075  * Off mode configuration bit. Used currently only by SW5 on omap4. There's
0076  * the following comment in Motorola Linux kernel tree for it:
0077  *
0078  * When set in the regulator mode, the regulator assignment will be changed
0079  * to secondary when the regulator is disabled. The mode will be set back to
0080  * primary when the regulator is turned on.
0081  */
0082 #define CPCAP_REG_OFF_MODE_SEC      BIT(15)
0083 
0084 /*
0085  * SoC specific configuration for CPCAP regulator. There are at least three
0086  * different SoCs each with their own parameters: omap3, omap4 and tegra2.
0087  *
0088  * The assign_reg and assign_mask seem to allow toggling between primary
0089  * and secondary mode that at least omap4 uses for off mode.
0090  */
0091 struct cpcap_regulator {
0092     struct regulator_desc rdesc;
0093     const u16 assign_reg;
0094     const u16 assign_mask;
0095 };
0096 
0097 #define CPCAP_REG(_ID, reg, assignment_reg, assignment_mask, val_tbl,   \
0098         mode_mask, volt_mask, mode_val, off_val,        \
0099         volt_trans_time) {                  \
0100     .rdesc = {                          \
0101         .name = #_ID,                       \
0102         .of_match = of_match_ptr(#_ID),             \
0103         .ops = &cpcap_regulator_ops,                \
0104         .regulators_node = of_match_ptr("regulators"),      \
0105         .type = REGULATOR_VOLTAGE,              \
0106         .id = CPCAP_##_ID,                  \
0107         .owner = THIS_MODULE,                   \
0108         .n_voltages = ARRAY_SIZE(val_tbl),          \
0109         .volt_table = (val_tbl),                \
0110         .vsel_reg = (reg),                  \
0111         .vsel_mask = (volt_mask),               \
0112         .enable_reg = (reg),                    \
0113         .enable_mask = (mode_mask),             \
0114         .enable_val = (mode_val),               \
0115         .disable_val = (off_val),               \
0116         .ramp_delay = (volt_trans_time),            \
0117         .of_map_mode = cpcap_map_mode,              \
0118     },                              \
0119     .assign_reg = (assignment_reg),                 \
0120     .assign_mask = (assignment_mask),               \
0121 }
0122 
0123 struct cpcap_ddata {
0124     struct regmap *reg;
0125     struct device *dev;
0126     const struct cpcap_regulator *soc;
0127 };
0128 
0129 enum cpcap_regulator_id {
0130     CPCAP_SW1,
0131     CPCAP_SW2,
0132     CPCAP_SW3,
0133     CPCAP_SW4,
0134     CPCAP_SW5,
0135     CPCAP_SW6,
0136     CPCAP_VCAM,
0137     CPCAP_VCSI,
0138     CPCAP_VDAC,
0139     CPCAP_VDIG,
0140     CPCAP_VFUSE,
0141     CPCAP_VHVIO,
0142     CPCAP_VSDIO,
0143     CPCAP_VPLL,
0144     CPCAP_VRF1,
0145     CPCAP_VRF2,
0146     CPCAP_VRFREF,
0147     CPCAP_VWLAN1,
0148     CPCAP_VWLAN2,
0149     CPCAP_VSIM,
0150     CPCAP_VSIMCARD,
0151     CPCAP_VVIB,
0152     CPCAP_VUSB,
0153     CPCAP_VAUDIO,
0154     CPCAP_NR_REGULATORS,
0155 };
0156 
0157 /*
0158  * We need to also configure regulator idle mode for SoC off mode if
0159  * CPCAP_REG_OFF_MODE_SEC is set.
0160  */
0161 static int cpcap_regulator_enable(struct regulator_dev *rdev)
0162 {
0163     struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
0164     int error;
0165 
0166     error = regulator_enable_regmap(rdev);
0167     if (error)
0168         return error;
0169 
0170     if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
0171         error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
0172                        regulator->assign_mask,
0173                        regulator->assign_mask);
0174         if (error)
0175             regulator_disable_regmap(rdev);
0176     }
0177 
0178     return error;
0179 }
0180 
0181 /*
0182  * We need to also configure regulator idle mode for SoC off mode if
0183  * CPCAP_REG_OFF_MODE_SEC is set.
0184  */
0185 static int cpcap_regulator_disable(struct regulator_dev *rdev)
0186 {
0187     struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
0188     int error;
0189 
0190     if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
0191         error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
0192                        regulator->assign_mask, 0);
0193         if (error)
0194             return error;
0195     }
0196 
0197     error = regulator_disable_regmap(rdev);
0198     if (error && (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC)) {
0199         regmap_update_bits(rdev->regmap, regulator->assign_reg,
0200                    regulator->assign_mask,
0201                    regulator->assign_mask);
0202     }
0203 
0204     return error;
0205 }
0206 
0207 static unsigned int cpcap_map_mode(unsigned int mode)
0208 {
0209     switch (mode) {
0210     case CPCAP_BIT_AUDIO_NORMAL_MODE:
0211         return REGULATOR_MODE_NORMAL;
0212     case CPCAP_BIT_AUDIO_LOW_PWR:
0213         return REGULATOR_MODE_STANDBY;
0214     default:
0215         return REGULATOR_MODE_INVALID;
0216     }
0217 }
0218 
0219 static unsigned int cpcap_regulator_get_mode(struct regulator_dev *rdev)
0220 {
0221     int value;
0222 
0223     regmap_read(rdev->regmap, rdev->desc->enable_reg, &value);
0224 
0225     if (value & CPCAP_BIT_AUDIO_LOW_PWR)
0226         return REGULATOR_MODE_STANDBY;
0227 
0228     return REGULATOR_MODE_NORMAL;
0229 }
0230 
0231 static int cpcap_regulator_set_mode(struct regulator_dev *rdev,
0232                     unsigned int mode)
0233 {
0234     int value;
0235 
0236     switch (mode) {
0237     case REGULATOR_MODE_NORMAL:
0238         value = CPCAP_BIT_AUDIO_NORMAL_MODE;
0239         break;
0240     case REGULATOR_MODE_STANDBY:
0241         value = CPCAP_BIT_AUDIO_LOW_PWR;
0242         break;
0243     default:
0244         return -EINVAL;
0245     }
0246 
0247     return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
0248                   CPCAP_BIT_AUDIO_LOW_PWR, value);
0249 }
0250 
0251 static const struct regulator_ops cpcap_regulator_ops = {
0252     .enable = cpcap_regulator_enable,
0253     .disable = cpcap_regulator_disable,
0254     .is_enabled = regulator_is_enabled_regmap,
0255     .list_voltage = regulator_list_voltage_table,
0256     .map_voltage = regulator_map_voltage_iterate,
0257     .get_voltage_sel = regulator_get_voltage_sel_regmap,
0258     .set_voltage_sel = regulator_set_voltage_sel_regmap,
0259     .get_mode = cpcap_regulator_get_mode,
0260     .set_mode = cpcap_regulator_set_mode,
0261 };
0262 
0263 static const unsigned int unknown_val_tbl[] = { 0, };
0264 static const unsigned int sw2_sw4_val_tbl[] = { 612500, 625000, 637500,
0265                         650000, 662500, 675000,
0266                         687500, 700000, 712500,
0267                         725000, 737500, 750000,
0268                         762500, 775000, 787500,
0269                         800000, 812500, 825000,
0270                         837500, 850000, 862500,
0271                         875000, 887500, 900000,
0272                         912500, 925000, 937500,
0273                         950000, 962500, 975000,
0274                         987500, 1000000, 1012500,
0275                         1025000, 1037500, 1050000,
0276                         1062500, 1075000, 1087500,
0277                         1100000, 1112500, 1125000,
0278                         1137500, 1150000, 1162500,
0279                         1175000, 1187500, 1200000,
0280                         1212500, 1225000, 1237500,
0281                         1250000, 1262500, 1275000,
0282                         1287500, 1300000, 1312500,
0283                         1325000, 1337500, 1350000,
0284                         1362500, 1375000, 1387500,
0285                         1400000, 1412500, 1425000,
0286                         1437500, 1450000, 1462500, };
0287 static const unsigned int sw5_val_tbl[] = { 0, 5050000, };
0288 static const unsigned int vcam_val_tbl[] = { 2600000, 2700000, 2800000,
0289                          2900000, };
0290 static const unsigned int vcsi_val_tbl[] = { 1200000, 1800000, };
0291 static const unsigned int vdac_val_tbl[] = { 1200000, 1500000, 1800000,
0292                          2500000,};
0293 static const unsigned int vdig_val_tbl[] = { 1200000, 1350000, 1500000,
0294                          1875000, };
0295 static const unsigned int vfuse_val_tbl[] = { 1500000, 1600000, 1700000,
0296                           1800000, 1900000, 2000000,
0297                           2100000, 2200000, 2300000,
0298                           2400000, 2500000, 2600000,
0299                           2700000, 3150000, };
0300 static const unsigned int vhvio_val_tbl[] = { 2775000, };
0301 static const unsigned int vsdio_val_tbl[] = { 1500000, 1600000, 1800000,
0302                           2600000, 2700000, 2800000,
0303                           2900000, 3000000, };
0304 static const unsigned int vpll_val_tbl[] = { 1200000, 1300000, 1400000,
0305                          1800000, };
0306 /* Quirk: 2775000 is before 2500000 for vrf1 regulator */
0307 static const unsigned int vrf1_val_tbl[] = { 2775000, 2500000, };
0308 static const unsigned int vrf2_val_tbl[] = { 0, 2775000, };
0309 static const unsigned int vrfref_val_tbl[] = { 2500000, 2775000, };
0310 static const unsigned int vwlan1_val_tbl[] = { 1800000, 1900000, };
0311 static const unsigned int vwlan2_val_tbl[] = { 2775000, 3000000, 3300000,
0312                            3300000, };
0313 static const unsigned int vsim_val_tbl[] = { 1800000, 2900000, };
0314 static const unsigned int vsimcard_val_tbl[] = { 1800000, 2900000, };
0315 static const unsigned int vvib_val_tbl[] = { 1300000, 1800000, 2000000,
0316                          3000000, };
0317 static const unsigned int vusb_val_tbl[] = { 0, 3300000, };
0318 static const unsigned int vaudio_val_tbl[] = { 0, 2775000, };
0319 
0320 /*
0321  * SoC specific configuration for omap4. The data below is comes from Motorola
0322  * Linux kernel tree. It's basically the values of cpcap_regltr_data,
0323  * cpcap_regulator_mode_values and cpcap_regulator_off_mode_values, see
0324  * CPCAP_REG macro above.
0325  *
0326  * SW1 to SW4 and SW6 seems to be unused for mapphone. Note that VSIM and
0327  * VSIMCARD have a shared resource assignment bit.
0328  */
0329 static const struct cpcap_regulator omap4_regulators[] = {
0330     CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
0331           CPCAP_BIT_SW1_SEL, unknown_val_tbl,
0332           0, 0, 0, 0, 0),
0333     CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
0334           CPCAP_BIT_SW2_SEL, unknown_val_tbl,
0335           0, 0, 0, 0, 0),
0336     CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
0337           CPCAP_BIT_SW3_SEL, unknown_val_tbl,
0338           0, 0, 0, 0, 0),
0339     CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
0340           CPCAP_BIT_SW4_SEL, unknown_val_tbl,
0341           0, 0, 0, 0, 0),
0342     CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
0343           CPCAP_BIT_SW5_SEL, sw5_val_tbl,
0344           0x28, 0, 0x20 | CPCAP_REG_OFF_MODE_SEC, 0, 0),
0345     CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
0346           CPCAP_BIT_SW6_SEL, unknown_val_tbl,
0347           0, 0, 0, 0, 0),
0348     CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
0349           CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
0350           0x87, 0x30, 0x3, 0, 420),
0351     CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
0352           CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
0353           0x47, 0x10, 0x43, 0x41, 350),
0354     CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
0355           CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
0356           0x87, 0x30, 0x3, 0, 420),
0357     CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
0358           CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
0359           0x87, 0x30, 0x82, 0, 420),
0360     CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
0361           CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
0362           0x80, 0xf, 0x80, 0, 420),
0363     CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
0364           CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
0365           0x17, 0, 0, 0x12, 0),
0366     CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
0367           CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
0368           0x87, 0x38, 0x82, 0, 420),
0369     CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
0370           CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
0371           0x43, 0x18, 0x2, 0, 420),
0372     CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
0373           CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
0374           0xac, 0x2, 0x4, 0, 10),
0375     CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
0376           CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
0377           0x23, 0x8, 0, 0, 10),
0378     CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
0379           CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
0380           0x23, 0x8, 0, 0, 420),
0381     CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
0382           CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
0383           0x47, 0x10, 0, 0, 420),
0384     CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
0385           CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
0386           0x20c, 0xc0, 0x20c, 0, 420),
0387     CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
0388           0xffff, vsim_val_tbl,
0389           0x23, 0x8, 0x3, 0, 420),
0390     CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
0391           0xffff, vsimcard_val_tbl,
0392           0x1e80, 0x8, 0x1e00, 0, 420),
0393     CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
0394           CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
0395           0x1, 0xc, 0x1, 0, 500),
0396     CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
0397           CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
0398           0x11c, 0x40, 0xc, 0, 0),
0399     CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
0400           CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
0401           0x16, 0x1, 0x4, 0, 0),
0402     { /* sentinel */ },
0403 };
0404 
0405 static const struct cpcap_regulator xoom_regulators[] = {
0406     CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
0407           CPCAP_BIT_SW1_SEL, unknown_val_tbl,
0408           0, 0, 0, 0, 0),
0409     CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
0410           CPCAP_BIT_SW2_SEL, sw2_sw4_val_tbl,
0411           0xf00, 0x7f, 0x800, 0, 120),
0412     CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
0413           CPCAP_BIT_SW3_SEL, unknown_val_tbl,
0414           0, 0, 0, 0, 0),
0415     CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
0416           CPCAP_BIT_SW4_SEL, sw2_sw4_val_tbl,
0417           0xf00, 0x7f, 0x900, 0, 100),
0418     CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
0419           CPCAP_BIT_SW5_SEL, sw5_val_tbl,
0420           0x2a, 0, 0x22, 0, 0),
0421     CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
0422           CPCAP_BIT_SW6_SEL, unknown_val_tbl,
0423           0, 0, 0, 0, 0),
0424     CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
0425           CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
0426           0x87, 0x30, 0x7, 0, 420),
0427     CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
0428           CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
0429           0x47, 0x10, 0x7, 0, 350),
0430     CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
0431           CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
0432           0x87, 0x30, 0x3, 0, 420),
0433     CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
0434           CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
0435           0x87, 0x30, 0x5, 0, 420),
0436     CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
0437           CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
0438           0x80, 0xf, 0x80, 0, 420),
0439     CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
0440           CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
0441           0x17, 0, 0x2, 0, 0),
0442     CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
0443           CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
0444           0x87, 0x38, 0x2, 0, 420),
0445     CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
0446           CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
0447           0x43, 0x18, 0x1, 0, 420),
0448     CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
0449           CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
0450           0xac, 0x2, 0xc, 0, 10),
0451     CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
0452           CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
0453           0x23, 0x8, 0x3, 0, 10),
0454     CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
0455           CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
0456           0x23, 0x8, 0x3, 0, 420),
0457     CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
0458           CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
0459           0x47, 0x10, 0x5, 0, 420),
0460     CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
0461           CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
0462           0x20c, 0xc0, 0x8, 0, 420),
0463     CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
0464           0xffff, vsim_val_tbl,
0465           0x23, 0x8, 0x3, 0, 420),
0466     CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
0467           0xffff, vsimcard_val_tbl,
0468           0x1e80, 0x8, 0x1e00, 0, 420),
0469     CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
0470           CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
0471           0x1, 0xc, 0, 0x1, 500),
0472     CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
0473           CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
0474           0x11c, 0x40, 0xc, 0, 0),
0475     CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
0476           CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
0477           0x16, 0x1, 0x4, 0, 0),
0478     { /* sentinel */ },
0479 };
0480 
0481 static const struct of_device_id cpcap_regulator_id_table[] = {
0482     {
0483         .compatible = "motorola,cpcap-regulator",
0484     },
0485     {
0486         .compatible = "motorola,mapphone-cpcap-regulator",
0487         .data = omap4_regulators,
0488     },
0489     {
0490         .compatible = "motorola,xoom-cpcap-regulator",
0491         .data = xoom_regulators,
0492     },
0493     {},
0494 };
0495 MODULE_DEVICE_TABLE(of, cpcap_regulator_id_table);
0496 
0497 static int cpcap_regulator_probe(struct platform_device *pdev)
0498 {
0499     struct cpcap_ddata *ddata;
0500     const struct cpcap_regulator *match_data;
0501     struct regulator_config config;
0502     int i;
0503 
0504     match_data = of_device_get_match_data(&pdev->dev);
0505     if (!match_data) {
0506         dev_err(&pdev->dev, "no configuration data found\n");
0507 
0508         return -ENODEV;
0509     }
0510 
0511     ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
0512     if (!ddata)
0513         return -ENOMEM;
0514 
0515     ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
0516     if (!ddata->reg)
0517         return -ENODEV;
0518 
0519     ddata->dev = &pdev->dev;
0520     ddata->soc = match_data;
0521     platform_set_drvdata(pdev, ddata);
0522 
0523     memset(&config, 0, sizeof(config));
0524     config.dev = &pdev->dev;
0525     config.regmap = ddata->reg;
0526 
0527     for (i = 0; i < CPCAP_NR_REGULATORS; i++) {
0528         const struct cpcap_regulator *regulator = &ddata->soc[i];
0529         struct regulator_dev *rdev;
0530 
0531         if (!regulator->rdesc.name)
0532             break;
0533 
0534         if (regulator->rdesc.volt_table == unknown_val_tbl)
0535             continue;
0536 
0537         config.driver_data = (void *)regulator;
0538         rdev = devm_regulator_register(&pdev->dev,
0539                            &regulator->rdesc,
0540                            &config);
0541         if (IS_ERR(rdev)) {
0542             dev_err(&pdev->dev, "failed to register regulator %s\n",
0543                 regulator->rdesc.name);
0544 
0545             return PTR_ERR(rdev);
0546         }
0547     }
0548 
0549     return 0;
0550 }
0551 
0552 static struct platform_driver cpcap_regulator_driver = {
0553     .probe      = cpcap_regulator_probe,
0554     .driver     = {
0555         .name   = "cpcap-regulator",
0556         .of_match_table = of_match_ptr(cpcap_regulator_id_table),
0557     },
0558 };
0559 
0560 module_platform_driver(cpcap_regulator_driver);
0561 
0562 MODULE_ALIAS("platform:cpcap-regulator");
0563 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
0564 MODULE_DESCRIPTION("CPCAP regulator driver");
0565 MODULE_LICENSE("GPL v2");
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