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OSCL-LXR
 
 

     

0001 /*
0002  * AXP20x regulators driver.
0003  *
0004  * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
0005  *
0006  * This file is subject to the terms and conditions of the GNU General
0007  * Public License. See the file "COPYING" in the main directory of this
0008  * archive for more details.
0009  *
0010  * This program is distributed in the hope that it will be useful,
0011  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0012  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0013  * GNU General Public License for more details.
0014  */
0015 
0016 #include <linux/bitops.h>
0017 #include <linux/delay.h>
0018 #include <linux/err.h>
0019 #include <linux/init.h>
0020 #include <linux/mfd/axp20x.h>
0021 #include <linux/module.h>
0022 #include <linux/of.h>
0023 #include <linux/of_device.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/regmap.h>
0026 #include <linux/regulator/driver.h>
0027 #include <linux/regulator/machine.h>
0028 #include <linux/regulator/of_regulator.h>
0029 
0030 #define AXP20X_GPIO0_FUNC_MASK      GENMASK(3, 0)
0031 #define AXP20X_GPIO1_FUNC_MASK      GENMASK(3, 0)
0032 
0033 #define AXP20X_IO_ENABLED       0x03
0034 #define AXP20X_IO_DISABLED      0x07
0035 
0036 #define AXP20X_WORKMODE_DCDC2_MASK  BIT_MASK(2)
0037 #define AXP20X_WORKMODE_DCDC3_MASK  BIT_MASK(1)
0038 
0039 #define AXP20X_FREQ_DCDC_MASK       GENMASK(3, 0)
0040 
0041 #define AXP20X_VBUS_IPSOUT_MGMT_MASK    BIT_MASK(2)
0042 
0043 #define AXP20X_DCDC2_V_OUT_MASK     GENMASK(5, 0)
0044 #define AXP20X_DCDC3_V_OUT_MASK     GENMASK(7, 0)
0045 #define AXP20X_LDO2_V_OUT_MASK      GENMASK(7, 4)
0046 #define AXP20X_LDO3_V_OUT_MASK      GENMASK(6, 0)
0047 #define AXP20X_LDO4_V_OUT_MASK      GENMASK(3, 0)
0048 #define AXP20X_LDO5_V_OUT_MASK      GENMASK(7, 4)
0049 
0050 #define AXP20X_PWR_OUT_EXTEN_MASK   BIT_MASK(0)
0051 #define AXP20X_PWR_OUT_DCDC3_MASK   BIT_MASK(1)
0052 #define AXP20X_PWR_OUT_LDO2_MASK    BIT_MASK(2)
0053 #define AXP20X_PWR_OUT_LDO4_MASK    BIT_MASK(3)
0054 #define AXP20X_PWR_OUT_DCDC2_MASK   BIT_MASK(4)
0055 #define AXP20X_PWR_OUT_LDO3_MASK    BIT_MASK(6)
0056 
0057 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK    BIT_MASK(0)
0058 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
0059     ((x) << 0)
0060 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK     BIT_MASK(1)
0061 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
0062     ((x) << 1)
0063 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK      BIT_MASK(2)
0064 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN       BIT(2)
0065 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK       BIT_MASK(3)
0066 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN        BIT(3)
0067 
0068 #define AXP20X_LDO4_V_OUT_1250mV_START  0x0
0069 #define AXP20X_LDO4_V_OUT_1250mV_STEPS  0
0070 #define AXP20X_LDO4_V_OUT_1250mV_END    \
0071     (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
0072 #define AXP20X_LDO4_V_OUT_1300mV_START  0x1
0073 #define AXP20X_LDO4_V_OUT_1300mV_STEPS  7
0074 #define AXP20X_LDO4_V_OUT_1300mV_END    \
0075     (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
0076 #define AXP20X_LDO4_V_OUT_2500mV_START  0x9
0077 #define AXP20X_LDO4_V_OUT_2500mV_STEPS  0
0078 #define AXP20X_LDO4_V_OUT_2500mV_END    \
0079     (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
0080 #define AXP20X_LDO4_V_OUT_2700mV_START  0xa
0081 #define AXP20X_LDO4_V_OUT_2700mV_STEPS  1
0082 #define AXP20X_LDO4_V_OUT_2700mV_END    \
0083     (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
0084 #define AXP20X_LDO4_V_OUT_3000mV_START  0xc
0085 #define AXP20X_LDO4_V_OUT_3000mV_STEPS  3
0086 #define AXP20X_LDO4_V_OUT_3000mV_END    \
0087     (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
0088 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES  16
0089 
0090 #define AXP22X_IO_ENABLED       0x03
0091 #define AXP22X_IO_DISABLED      0x04
0092 
0093 #define AXP22X_WORKMODE_DCDCX_MASK(x)   BIT_MASK(x)
0094 
0095 #define AXP22X_MISC_N_VBUSEN_FUNC   BIT(4)
0096 
0097 #define AXP22X_DCDC1_V_OUT_MASK     GENMASK(4, 0)
0098 #define AXP22X_DCDC2_V_OUT_MASK     GENMASK(5, 0)
0099 #define AXP22X_DCDC3_V_OUT_MASK     GENMASK(5, 0)
0100 #define AXP22X_DCDC4_V_OUT_MASK     GENMASK(5, 0)
0101 #define AXP22X_DCDC5_V_OUT_MASK     GENMASK(4, 0)
0102 #define AXP22X_DC5LDO_V_OUT_MASK    GENMASK(2, 0)
0103 #define AXP22X_ALDO1_V_OUT_MASK     GENMASK(4, 0)
0104 #define AXP22X_ALDO2_V_OUT_MASK     GENMASK(4, 0)
0105 #define AXP22X_ALDO3_V_OUT_MASK     GENMASK(4, 0)
0106 #define AXP22X_DLDO1_V_OUT_MASK     GENMASK(4, 0)
0107 #define AXP22X_DLDO2_V_OUT_MASK     GENMASK(4, 0)
0108 #define AXP22X_DLDO3_V_OUT_MASK     GENMASK(4, 0)
0109 #define AXP22X_DLDO4_V_OUT_MASK     GENMASK(4, 0)
0110 #define AXP22X_ELDO1_V_OUT_MASK     GENMASK(4, 0)
0111 #define AXP22X_ELDO2_V_OUT_MASK     GENMASK(4, 0)
0112 #define AXP22X_ELDO3_V_OUT_MASK     GENMASK(4, 0)
0113 #define AXP22X_LDO_IO0_V_OUT_MASK   GENMASK(4, 0)
0114 #define AXP22X_LDO_IO1_V_OUT_MASK   GENMASK(4, 0)
0115 
0116 #define AXP22X_PWR_OUT_DC5LDO_MASK  BIT_MASK(0)
0117 #define AXP22X_PWR_OUT_DCDC1_MASK   BIT_MASK(1)
0118 #define AXP22X_PWR_OUT_DCDC2_MASK   BIT_MASK(2)
0119 #define AXP22X_PWR_OUT_DCDC3_MASK   BIT_MASK(3)
0120 #define AXP22X_PWR_OUT_DCDC4_MASK   BIT_MASK(4)
0121 #define AXP22X_PWR_OUT_DCDC5_MASK   BIT_MASK(5)
0122 #define AXP22X_PWR_OUT_ALDO1_MASK   BIT_MASK(6)
0123 #define AXP22X_PWR_OUT_ALDO2_MASK   BIT_MASK(7)
0124 
0125 #define AXP22X_PWR_OUT_SW_MASK      BIT_MASK(6)
0126 #define AXP22X_PWR_OUT_DC1SW_MASK   BIT_MASK(7)
0127 
0128 #define AXP22X_PWR_OUT_ELDO1_MASK   BIT_MASK(0)
0129 #define AXP22X_PWR_OUT_ELDO2_MASK   BIT_MASK(1)
0130 #define AXP22X_PWR_OUT_ELDO3_MASK   BIT_MASK(2)
0131 #define AXP22X_PWR_OUT_DLDO1_MASK   BIT_MASK(3)
0132 #define AXP22X_PWR_OUT_DLDO2_MASK   BIT_MASK(4)
0133 #define AXP22X_PWR_OUT_DLDO3_MASK   BIT_MASK(5)
0134 #define AXP22X_PWR_OUT_DLDO4_MASK   BIT_MASK(6)
0135 #define AXP22X_PWR_OUT_ALDO3_MASK   BIT_MASK(7)
0136 
0137 #define AXP803_PWR_OUT_DCDC1_MASK   BIT_MASK(0)
0138 #define AXP803_PWR_OUT_DCDC2_MASK   BIT_MASK(1)
0139 #define AXP803_PWR_OUT_DCDC3_MASK   BIT_MASK(2)
0140 #define AXP803_PWR_OUT_DCDC4_MASK   BIT_MASK(3)
0141 #define AXP803_PWR_OUT_DCDC5_MASK   BIT_MASK(4)
0142 #define AXP803_PWR_OUT_DCDC6_MASK   BIT_MASK(5)
0143 
0144 #define AXP803_PWR_OUT_FLDO1_MASK   BIT_MASK(2)
0145 #define AXP803_PWR_OUT_FLDO2_MASK   BIT_MASK(3)
0146 
0147 #define AXP803_DCDC1_V_OUT_MASK     GENMASK(4, 0)
0148 #define AXP803_DCDC2_V_OUT_MASK     GENMASK(6, 0)
0149 #define AXP803_DCDC3_V_OUT_MASK     GENMASK(6, 0)
0150 #define AXP803_DCDC4_V_OUT_MASK     GENMASK(6, 0)
0151 #define AXP803_DCDC5_V_OUT_MASK     GENMASK(6, 0)
0152 #define AXP803_DCDC6_V_OUT_MASK     GENMASK(6, 0)
0153 
0154 #define AXP803_FLDO1_V_OUT_MASK     GENMASK(3, 0)
0155 #define AXP803_FLDO2_V_OUT_MASK     GENMASK(3, 0)
0156 
0157 #define AXP803_DCDC23_POLYPHASE_DUAL    BIT(6)
0158 #define AXP803_DCDC56_POLYPHASE_DUAL    BIT(5)
0159 
0160 #define AXP803_DCDC234_500mV_START  0x00
0161 #define AXP803_DCDC234_500mV_STEPS  70
0162 #define AXP803_DCDC234_500mV_END    \
0163     (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
0164 #define AXP803_DCDC234_1220mV_START 0x47
0165 #define AXP803_DCDC234_1220mV_STEPS 4
0166 #define AXP803_DCDC234_1220mV_END   \
0167     (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
0168 #define AXP803_DCDC234_NUM_VOLTAGES 76
0169 
0170 #define AXP803_DCDC5_800mV_START    0x00
0171 #define AXP803_DCDC5_800mV_STEPS    32
0172 #define AXP803_DCDC5_800mV_END      \
0173     (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
0174 #define AXP803_DCDC5_1140mV_START   0x21
0175 #define AXP803_DCDC5_1140mV_STEPS   35
0176 #define AXP803_DCDC5_1140mV_END     \
0177     (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
0178 #define AXP803_DCDC5_NUM_VOLTAGES   69
0179 
0180 #define AXP803_DCDC6_600mV_START    0x00
0181 #define AXP803_DCDC6_600mV_STEPS    50
0182 #define AXP803_DCDC6_600mV_END      \
0183     (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
0184 #define AXP803_DCDC6_1120mV_START   0x33
0185 #define AXP803_DCDC6_1120mV_STEPS   20
0186 #define AXP803_DCDC6_1120mV_END     \
0187     (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
0188 #define AXP803_DCDC6_NUM_VOLTAGES   72
0189 
0190 #define AXP803_DLDO2_700mV_START    0x00
0191 #define AXP803_DLDO2_700mV_STEPS    26
0192 #define AXP803_DLDO2_700mV_END      \
0193     (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
0194 #define AXP803_DLDO2_3400mV_START   0x1b
0195 #define AXP803_DLDO2_3400mV_STEPS   4
0196 #define AXP803_DLDO2_3400mV_END     \
0197     (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
0198 #define AXP803_DLDO2_NUM_VOLTAGES   32
0199 
0200 #define AXP806_DCDCA_V_CTRL_MASK    GENMASK(6, 0)
0201 #define AXP806_DCDCB_V_CTRL_MASK    GENMASK(4, 0)
0202 #define AXP806_DCDCC_V_CTRL_MASK    GENMASK(6, 0)
0203 #define AXP806_DCDCD_V_CTRL_MASK    GENMASK(5, 0)
0204 #define AXP806_DCDCE_V_CTRL_MASK    GENMASK(4, 0)
0205 #define AXP806_ALDO1_V_CTRL_MASK    GENMASK(4, 0)
0206 #define AXP806_ALDO2_V_CTRL_MASK    GENMASK(4, 0)
0207 #define AXP806_ALDO3_V_CTRL_MASK    GENMASK(4, 0)
0208 #define AXP806_BLDO1_V_CTRL_MASK    GENMASK(3, 0)
0209 #define AXP806_BLDO2_V_CTRL_MASK    GENMASK(3, 0)
0210 #define AXP806_BLDO3_V_CTRL_MASK    GENMASK(3, 0)
0211 #define AXP806_BLDO4_V_CTRL_MASK    GENMASK(3, 0)
0212 #define AXP806_CLDO1_V_CTRL_MASK    GENMASK(4, 0)
0213 #define AXP806_CLDO2_V_CTRL_MASK    GENMASK(4, 0)
0214 #define AXP806_CLDO3_V_CTRL_MASK    GENMASK(4, 0)
0215 
0216 #define AXP806_PWR_OUT_DCDCA_MASK   BIT_MASK(0)
0217 #define AXP806_PWR_OUT_DCDCB_MASK   BIT_MASK(1)
0218 #define AXP806_PWR_OUT_DCDCC_MASK   BIT_MASK(2)
0219 #define AXP806_PWR_OUT_DCDCD_MASK   BIT_MASK(3)
0220 #define AXP806_PWR_OUT_DCDCE_MASK   BIT_MASK(4)
0221 #define AXP806_PWR_OUT_ALDO1_MASK   BIT_MASK(5)
0222 #define AXP806_PWR_OUT_ALDO2_MASK   BIT_MASK(6)
0223 #define AXP806_PWR_OUT_ALDO3_MASK   BIT_MASK(7)
0224 #define AXP806_PWR_OUT_BLDO1_MASK   BIT_MASK(0)
0225 #define AXP806_PWR_OUT_BLDO2_MASK   BIT_MASK(1)
0226 #define AXP806_PWR_OUT_BLDO3_MASK   BIT_MASK(2)
0227 #define AXP806_PWR_OUT_BLDO4_MASK   BIT_MASK(3)
0228 #define AXP806_PWR_OUT_CLDO1_MASK   BIT_MASK(4)
0229 #define AXP806_PWR_OUT_CLDO2_MASK   BIT_MASK(5)
0230 #define AXP806_PWR_OUT_CLDO3_MASK   BIT_MASK(6)
0231 #define AXP806_PWR_OUT_SW_MASK      BIT_MASK(7)
0232 
0233 #define AXP806_DCDCAB_POLYPHASE_DUAL    0x40
0234 #define AXP806_DCDCABC_POLYPHASE_TRI    0x80
0235 #define AXP806_DCDCABC_POLYPHASE_MASK   GENMASK(7, 6)
0236 
0237 #define AXP806_DCDCDE_POLYPHASE_DUAL    BIT(5)
0238 
0239 #define AXP806_DCDCA_600mV_START    0x00
0240 #define AXP806_DCDCA_600mV_STEPS    50
0241 #define AXP806_DCDCA_600mV_END      \
0242     (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
0243 #define AXP806_DCDCA_1120mV_START   0x33
0244 #define AXP806_DCDCA_1120mV_STEPS   20
0245 #define AXP806_DCDCA_1120mV_END     \
0246     (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
0247 #define AXP806_DCDCA_NUM_VOLTAGES   72
0248 
0249 #define AXP806_DCDCD_600mV_START    0x00
0250 #define AXP806_DCDCD_600mV_STEPS    45
0251 #define AXP806_DCDCD_600mV_END      \
0252     (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
0253 #define AXP806_DCDCD_1600mV_START   0x2e
0254 #define AXP806_DCDCD_1600mV_STEPS   17
0255 #define AXP806_DCDCD_1600mV_END     \
0256     (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
0257 #define AXP806_DCDCD_NUM_VOLTAGES   64
0258 
0259 #define AXP809_DCDC4_600mV_START    0x00
0260 #define AXP809_DCDC4_600mV_STEPS    47
0261 #define AXP809_DCDC4_600mV_END      \
0262     (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
0263 #define AXP809_DCDC4_1800mV_START   0x30
0264 #define AXP809_DCDC4_1800mV_STEPS   8
0265 #define AXP809_DCDC4_1800mV_END     \
0266     (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
0267 #define AXP809_DCDC4_NUM_VOLTAGES   57
0268 
0269 #define AXP813_DCDC7_V_OUT_MASK     GENMASK(6, 0)
0270 
0271 #define AXP813_PWR_OUT_DCDC7_MASK   BIT_MASK(6)
0272 
0273 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg,    \
0274             _vmask, _ereg, _emask, _enable_val, _disable_val)       \
0275     [_family##_##_id] = {                           \
0276         .name       = (_match),                 \
0277         .supply_name    = (_supply),                    \
0278         .of_match   = of_match_ptr(_match),             \
0279         .regulators_node = of_match_ptr("regulators"),          \
0280         .type       = REGULATOR_VOLTAGE,                \
0281         .id     = _family##_##_id,              \
0282         .n_voltages = (((_max) - (_min)) / (_step) + 1),        \
0283         .owner      = THIS_MODULE,                  \
0284         .min_uV     = (_min) * 1000,                \
0285         .uV_step    = (_step) * 1000,               \
0286         .vsel_reg   = (_vreg),                  \
0287         .vsel_mask  = (_vmask),                 \
0288         .enable_reg = (_ereg),                  \
0289         .enable_mask    = (_emask),                 \
0290         .enable_val = (_enable_val),                \
0291         .disable_val    = (_disable_val),               \
0292         .ops        = &axp20x_ops,                  \
0293     }
0294 
0295 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg,   \
0296          _vmask, _ereg, _emask)                     \
0297     [_family##_##_id] = {                           \
0298         .name       = (_match),                 \
0299         .supply_name    = (_supply),                    \
0300         .of_match   = of_match_ptr(_match),             \
0301         .regulators_node = of_match_ptr("regulators"),          \
0302         .type       = REGULATOR_VOLTAGE,                \
0303         .id     = _family##_##_id,              \
0304         .n_voltages = (((_max) - (_min)) / (_step) + 1),        \
0305         .owner      = THIS_MODULE,                  \
0306         .min_uV     = (_min) * 1000,                \
0307         .uV_step    = (_step) * 1000,               \
0308         .vsel_reg   = (_vreg),                  \
0309         .vsel_mask  = (_vmask),                 \
0310         .enable_reg = (_ereg),                  \
0311         .enable_mask    = (_emask),                 \
0312         .ops        = &axp20x_ops,                  \
0313     }
0314 
0315 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask)       \
0316     [_family##_##_id] = {                           \
0317         .name       = (_match),                 \
0318         .supply_name    = (_supply),                    \
0319         .of_match   = of_match_ptr(_match),             \
0320         .regulators_node = of_match_ptr("regulators"),          \
0321         .type       = REGULATOR_VOLTAGE,                \
0322         .id     = _family##_##_id,              \
0323         .owner      = THIS_MODULE,                  \
0324         .enable_reg = (_ereg),                  \
0325         .enable_mask    = (_emask),                 \
0326         .ops        = &axp20x_ops_sw,               \
0327     }
0328 
0329 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt)            \
0330     [_family##_##_id] = {                           \
0331         .name       = (_match),                 \
0332         .supply_name    = (_supply),                    \
0333         .of_match   = of_match_ptr(_match),             \
0334         .regulators_node = of_match_ptr("regulators"),          \
0335         .type       = REGULATOR_VOLTAGE,                \
0336         .id     = _family##_##_id,              \
0337         .n_voltages = 1,                        \
0338         .owner      = THIS_MODULE,                  \
0339         .min_uV     = (_volt) * 1000,               \
0340         .ops        = &axp20x_ops_fixed             \
0341     }
0342 
0343 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages,    \
0344             _vreg, _vmask, _ereg, _emask)               \
0345     [_family##_##_id] = {                           \
0346         .name       = (_match),                 \
0347         .supply_name    = (_supply),                    \
0348         .of_match   = of_match_ptr(_match),             \
0349         .regulators_node = of_match_ptr("regulators"),          \
0350         .type       = REGULATOR_VOLTAGE,                \
0351         .id     = _family##_##_id,              \
0352         .n_voltages = (_n_voltages),                \
0353         .owner      = THIS_MODULE,                  \
0354         .vsel_reg   = (_vreg),                  \
0355         .vsel_mask  = (_vmask),                 \
0356         .enable_reg = (_ereg),                  \
0357         .enable_mask    = (_emask),                 \
0358         .linear_ranges  = (_ranges),                    \
0359         .n_linear_ranges = ARRAY_SIZE(_ranges),             \
0360         .ops        = &axp20x_ops_range,                \
0361     }
0362 
0363 static const int axp209_dcdc2_ldo3_slew_rates[] = {
0364     1600,
0365      800,
0366 };
0367 
0368 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
0369 {
0370     struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
0371     int id = rdev_get_id(rdev);
0372     u8 reg, mask, enable, cfg = 0xff;
0373     const int *slew_rates;
0374     int rate_count = 0;
0375 
0376     switch (axp20x->variant) {
0377     case AXP209_ID:
0378         if (id == AXP20X_DCDC2) {
0379             slew_rates = axp209_dcdc2_ldo3_slew_rates;
0380             rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
0381             reg = AXP20X_DCDC2_LDO3_V_RAMP;
0382             mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
0383                    AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
0384             enable = (ramp > 0) ?
0385                  AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0;
0386             break;
0387         }
0388 
0389         if (id == AXP20X_LDO3) {
0390             slew_rates = axp209_dcdc2_ldo3_slew_rates;
0391             rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
0392             reg = AXP20X_DCDC2_LDO3_V_RAMP;
0393             mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
0394                    AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
0395             enable = (ramp > 0) ?
0396                  AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0;
0397             break;
0398         }
0399 
0400         if (rate_count > 0)
0401             break;
0402 
0403         fallthrough;
0404     default:
0405         /* Not supported for this regulator */
0406         return -ENOTSUPP;
0407     }
0408 
0409     if (ramp == 0) {
0410         cfg = enable;
0411     } else {
0412         int i;
0413 
0414         for (i = 0; i < rate_count; i++) {
0415             if (ramp > slew_rates[i])
0416                 break;
0417 
0418             if (id == AXP20X_DCDC2)
0419                 cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i);
0420             else
0421                 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
0422         }
0423 
0424         if (cfg == 0xff) {
0425             dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
0426             return -EINVAL;
0427         }
0428 
0429         cfg |= enable;
0430     }
0431 
0432     return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
0433 }
0434 
0435 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
0436 {
0437     struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
0438     int id = rdev_get_id(rdev);
0439 
0440     switch (axp20x->variant) {
0441     case AXP209_ID:
0442         if ((id == AXP20X_LDO3) &&
0443             rdev->constraints && rdev->constraints->soft_start) {
0444             int v_out;
0445             int ret;
0446 
0447             /*
0448              * On some boards, the LDO3 can be overloaded when
0449              * turning on, causing the entire PMIC to shutdown
0450              * without warning. Turning it on at the minimal voltage
0451              * and then setting the voltage to the requested value
0452              * works reliably.
0453              */
0454             if (regulator_is_enabled_regmap(rdev))
0455                 break;
0456 
0457             v_out = regulator_get_voltage_sel_regmap(rdev);
0458             if (v_out < 0)
0459                 return v_out;
0460 
0461             if (v_out == 0)
0462                 break;
0463 
0464             ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
0465             /*
0466              * A small pause is needed between
0467              * setting the voltage and enabling the LDO to give the
0468              * internal state machine time to process the request.
0469              */
0470             usleep_range(1000, 5000);
0471             ret |= regulator_enable_regmap(rdev);
0472             ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
0473 
0474             return ret;
0475         }
0476         break;
0477     default:
0478         /* No quirks */
0479         break;
0480     }
0481 
0482     return regulator_enable_regmap(rdev);
0483 };
0484 
0485 static const struct regulator_ops axp20x_ops_fixed = {
0486     .list_voltage       = regulator_list_voltage_linear,
0487 };
0488 
0489 static const struct regulator_ops axp20x_ops_range = {
0490     .set_voltage_sel    = regulator_set_voltage_sel_regmap,
0491     .get_voltage_sel    = regulator_get_voltage_sel_regmap,
0492     .list_voltage       = regulator_list_voltage_linear_range,
0493     .enable         = regulator_enable_regmap,
0494     .disable        = regulator_disable_regmap,
0495     .is_enabled     = regulator_is_enabled_regmap,
0496 };
0497 
0498 static const struct regulator_ops axp20x_ops = {
0499     .set_voltage_sel    = regulator_set_voltage_sel_regmap,
0500     .get_voltage_sel    = regulator_get_voltage_sel_regmap,
0501     .list_voltage       = regulator_list_voltage_linear,
0502     .enable         = axp20x_regulator_enable_regmap,
0503     .disable        = regulator_disable_regmap,
0504     .is_enabled     = regulator_is_enabled_regmap,
0505     .set_ramp_delay     = axp20x_set_ramp_delay,
0506 };
0507 
0508 static const struct regulator_ops axp20x_ops_sw = {
0509     .enable         = regulator_enable_regmap,
0510     .disable        = regulator_disable_regmap,
0511     .is_enabled     = regulator_is_enabled_regmap,
0512 };
0513 
0514 static const struct linear_range axp20x_ldo4_ranges[] = {
0515     REGULATOR_LINEAR_RANGE(1250000,
0516                    AXP20X_LDO4_V_OUT_1250mV_START,
0517                    AXP20X_LDO4_V_OUT_1250mV_END,
0518                    0),
0519     REGULATOR_LINEAR_RANGE(1300000,
0520                    AXP20X_LDO4_V_OUT_1300mV_START,
0521                    AXP20X_LDO4_V_OUT_1300mV_END,
0522                    100000),
0523     REGULATOR_LINEAR_RANGE(2500000,
0524                    AXP20X_LDO4_V_OUT_2500mV_START,
0525                    AXP20X_LDO4_V_OUT_2500mV_END,
0526                    0),
0527     REGULATOR_LINEAR_RANGE(2700000,
0528                    AXP20X_LDO4_V_OUT_2700mV_START,
0529                    AXP20X_LDO4_V_OUT_2700mV_END,
0530                    100000),
0531     REGULATOR_LINEAR_RANGE(3000000,
0532                    AXP20X_LDO4_V_OUT_3000mV_START,
0533                    AXP20X_LDO4_V_OUT_3000mV_END,
0534                    100000),
0535 };
0536 
0537 static const struct regulator_desc axp20x_regulators[] = {
0538     AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
0539          AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
0540          AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
0541     AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
0542          AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
0543          AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
0544     AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
0545     AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
0546          AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK,
0547          AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
0548     AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
0549          AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
0550          AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
0551     AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
0552             axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
0553             AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK,
0554             AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
0555     AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
0556             AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
0557             AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
0558             AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
0559 };
0560 
0561 static const struct regulator_desc axp22x_regulators[] = {
0562     AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
0563          AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
0564          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
0565     AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
0566          AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
0567          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
0568     AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
0569          AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
0570          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
0571     AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
0572          AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
0573          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
0574     AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
0575          AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
0576          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
0577     /* secondary switchable output of DCDC1 */
0578     AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
0579             AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
0580     /* LDO regulator internally chained to DCDC5 */
0581     AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
0582          AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
0583          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
0584     AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
0585          AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
0586          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
0587     AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
0588          AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
0589          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
0590     AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
0591          AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
0592          AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
0593     AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
0594          AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
0595          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
0596     AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
0597          AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
0598          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
0599     AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
0600          AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
0601          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
0602     AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
0603          AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
0604          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
0605     AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
0606          AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
0607          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
0608     AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
0609          AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
0610          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
0611     AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
0612          AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
0613          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
0614     /* Note the datasheet only guarantees reliable operation up to
0615      * 3.3V, this needs to be enforced via dts provided constraints */
0616     AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
0617             AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
0618             AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
0619             AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
0620     /* Note the datasheet only guarantees reliable operation up to
0621      * 3.3V, this needs to be enforced via dts provided constraints */
0622     AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
0623             AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
0624             AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
0625             AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
0626     AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
0627 };
0628 
0629 static const struct regulator_desc axp22x_drivevbus_regulator = {
0630     .name       = "drivevbus",
0631     .supply_name    = "drivevbus",
0632     .of_match   = of_match_ptr("drivevbus"),
0633     .regulators_node = of_match_ptr("regulators"),
0634     .type       = REGULATOR_VOLTAGE,
0635     .owner      = THIS_MODULE,
0636     .enable_reg = AXP20X_VBUS_IPSOUT_MGMT,
0637     .enable_mask    = AXP20X_VBUS_IPSOUT_MGMT_MASK,
0638     .ops        = &axp20x_ops_sw,
0639 };
0640 
0641 /* DCDC ranges shared with AXP813 */
0642 static const struct linear_range axp803_dcdc234_ranges[] = {
0643     REGULATOR_LINEAR_RANGE(500000,
0644                    AXP803_DCDC234_500mV_START,
0645                    AXP803_DCDC234_500mV_END,
0646                    10000),
0647     REGULATOR_LINEAR_RANGE(1220000,
0648                    AXP803_DCDC234_1220mV_START,
0649                    AXP803_DCDC234_1220mV_END,
0650                    20000),
0651 };
0652 
0653 static const struct linear_range axp803_dcdc5_ranges[] = {
0654     REGULATOR_LINEAR_RANGE(800000,
0655                    AXP803_DCDC5_800mV_START,
0656                    AXP803_DCDC5_800mV_END,
0657                    10000),
0658     REGULATOR_LINEAR_RANGE(1140000,
0659                    AXP803_DCDC5_1140mV_START,
0660                    AXP803_DCDC5_1140mV_END,
0661                    20000),
0662 };
0663 
0664 static const struct linear_range axp803_dcdc6_ranges[] = {
0665     REGULATOR_LINEAR_RANGE(600000,
0666                    AXP803_DCDC6_600mV_START,
0667                    AXP803_DCDC6_600mV_END,
0668                    10000),
0669     REGULATOR_LINEAR_RANGE(1120000,
0670                    AXP803_DCDC6_1120mV_START,
0671                    AXP803_DCDC6_1120mV_END,
0672                    20000),
0673 };
0674 
0675 /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */
0676 static const struct linear_range axp803_dldo2_ranges[] = {
0677     REGULATOR_LINEAR_RANGE(700000,
0678                    AXP803_DLDO2_700mV_START,
0679                    AXP803_DLDO2_700mV_END,
0680                    100000),
0681     REGULATOR_LINEAR_RANGE(3400000,
0682                    AXP803_DLDO2_3400mV_START,
0683                    AXP803_DLDO2_3400mV_END,
0684                    200000),
0685 };
0686 
0687 static const struct regulator_desc axp803_regulators[] = {
0688     AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
0689          AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
0690          AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
0691     AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
0692             axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
0693             AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
0694             AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
0695     AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
0696             axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
0697             AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
0698             AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
0699     AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
0700             axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
0701             AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
0702             AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
0703     AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
0704             axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
0705             AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
0706             AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
0707     AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
0708             axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
0709             AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
0710             AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
0711     /* secondary switchable output of DCDC1 */
0712     AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
0713             AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
0714     AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
0715          AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
0716          AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
0717     AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
0718          AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
0719          AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
0720     AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
0721          AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
0722          AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
0723     AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
0724          AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
0725          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
0726     AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
0727             axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
0728             AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
0729             AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
0730     AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
0731          AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
0732          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
0733     AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
0734          AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
0735          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
0736     AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
0737          AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
0738          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
0739     AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
0740          AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
0741          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
0742     AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
0743          AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
0744          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
0745     AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
0746          AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
0747          AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
0748     AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
0749          AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
0750          AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
0751     AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
0752             AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
0753             AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
0754             AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
0755     AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
0756             AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
0757             AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
0758             AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
0759     AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
0760 };
0761 
0762 static const struct linear_range axp806_dcdca_ranges[] = {
0763     REGULATOR_LINEAR_RANGE(600000,
0764                    AXP806_DCDCA_600mV_START,
0765                    AXP806_DCDCA_600mV_END,
0766                    10000),
0767     REGULATOR_LINEAR_RANGE(1120000,
0768                    AXP806_DCDCA_1120mV_START,
0769                    AXP806_DCDCA_1120mV_END,
0770                    20000),
0771 };
0772 
0773 static const struct linear_range axp806_dcdcd_ranges[] = {
0774     REGULATOR_LINEAR_RANGE(600000,
0775                    AXP806_DCDCD_600mV_START,
0776                    AXP806_DCDCD_600mV_END,
0777                    20000),
0778     REGULATOR_LINEAR_RANGE(1600000,
0779                    AXP806_DCDCD_1600mV_START,
0780                    AXP806_DCDCD_1600mV_END,
0781                    100000),
0782 };
0783 
0784 static const struct regulator_desc axp806_regulators[] = {
0785     AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
0786             axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
0787             AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
0788             AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
0789     AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
0790          AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
0791          AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
0792     AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
0793             axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
0794             AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
0795             AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
0796     AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
0797             axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
0798             AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
0799             AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
0800     AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
0801          AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
0802          AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
0803     AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
0804          AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
0805          AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
0806     AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
0807          AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
0808          AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
0809     AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
0810          AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
0811          AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
0812     AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
0813          AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
0814          AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
0815     AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
0816          AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
0817          AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
0818     AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
0819          AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
0820          AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
0821     AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
0822          AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
0823          AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
0824     AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
0825          AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
0826          AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
0827     AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
0828             axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
0829             AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
0830             AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
0831     AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
0832          AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
0833          AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
0834     AXP_DESC_SW(AXP806, SW, "sw", "swin",
0835             AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
0836 };
0837 
0838 static const struct linear_range axp809_dcdc4_ranges[] = {
0839     REGULATOR_LINEAR_RANGE(600000,
0840                    AXP809_DCDC4_600mV_START,
0841                    AXP809_DCDC4_600mV_END,
0842                    20000),
0843     REGULATOR_LINEAR_RANGE(1800000,
0844                    AXP809_DCDC4_1800mV_START,
0845                    AXP809_DCDC4_1800mV_END,
0846                    100000),
0847 };
0848 
0849 static const struct regulator_desc axp809_regulators[] = {
0850     AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
0851          AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
0852          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
0853     AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
0854          AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
0855          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
0856     AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
0857          AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
0858          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
0859     AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
0860             axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
0861             AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
0862             AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
0863     AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
0864          AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
0865          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
0866     /* secondary switchable output of DCDC1 */
0867     AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
0868             AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
0869     /* LDO regulator internally chained to DCDC5 */
0870     AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
0871          AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
0872          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
0873     AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
0874          AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
0875          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
0876     AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
0877          AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
0878          AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
0879     AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
0880          AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
0881          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
0882     AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
0883             axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
0884             AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
0885             AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
0886     AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
0887          AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
0888          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
0889     AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
0890          AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
0891          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
0892     AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
0893          AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
0894          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
0895     AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
0896          AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
0897          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
0898     /*
0899      * Note the datasheet only guarantees reliable operation up to
0900      * 3.3V, this needs to be enforced via dts provided constraints
0901      */
0902     AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
0903             AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
0904             AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
0905             AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
0906     /*
0907      * Note the datasheet only guarantees reliable operation up to
0908      * 3.3V, this needs to be enforced via dts provided constraints
0909      */
0910     AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
0911             AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
0912             AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
0913             AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
0914     AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
0915     AXP_DESC_SW(AXP809, SW, "sw", "swin",
0916             AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
0917 };
0918 
0919 static const struct regulator_desc axp813_regulators[] = {
0920     AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
0921          AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
0922          AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
0923     AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
0924             axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
0925             AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
0926             AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
0927     AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
0928             axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
0929             AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
0930             AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
0931     AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
0932             axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
0933             AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
0934             AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
0935     AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
0936             axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
0937             AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
0938             AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
0939     AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
0940             axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
0941             AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
0942             AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
0943     AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
0944             axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
0945             AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
0946             AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
0947     AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
0948          AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
0949          AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
0950     AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
0951          AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
0952          AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
0953     AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
0954          AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
0955          AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
0956     AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
0957          AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
0958          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
0959     AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
0960             axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
0961             AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
0962             AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
0963     AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
0964          AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
0965          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
0966     AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
0967          AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
0968          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
0969     AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
0970          AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
0971          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
0972     AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
0973          AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
0974          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
0975     AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
0976          AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
0977          AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
0978     /* to do / check ... */
0979     AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
0980          AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
0981          AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
0982     AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
0983          AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
0984          AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
0985     /*
0986      * TODO: FLDO3 = {DCDC5, FLDOIN} / 2
0987      *
0988      * This means FLDO3 effectively switches supplies at runtime,
0989      * something the regulator subsystem does not support.
0990      */
0991     AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
0992     AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
0993             AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
0994             AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
0995             AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
0996     AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
0997             AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
0998             AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
0999             AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1000     AXP_DESC_SW(AXP813, SW, "sw", "swin",
1001             AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
1002 };
1003 
1004 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
1005 {
1006     struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1007     unsigned int reg = AXP20X_DCDC_FREQ;
1008     u32 min, max, def, step;
1009 
1010     switch (axp20x->variant) {
1011     case AXP202_ID:
1012     case AXP209_ID:
1013         min = 750;
1014         max = 1875;
1015         def = 1500;
1016         step = 75;
1017         break;
1018     case AXP803_ID:
1019     case AXP813_ID:
1020         /*
1021          * AXP803/AXP813 DCDC work frequency setting has the same
1022          * range and step as AXP22X, but at a different register.
1023          * (See include/linux/mfd/axp20x.h)
1024          */
1025         reg = AXP803_DCDC_FREQ_CTRL;
1026         fallthrough;    /* to the check below */
1027     case AXP806_ID:
1028         /*
1029          * AXP806 also have DCDC work frequency setting register at a
1030          * different position.
1031          */
1032         if (axp20x->variant == AXP806_ID)
1033             reg = AXP806_DCDC_FREQ_CTRL;
1034         fallthrough;
1035     case AXP221_ID:
1036     case AXP223_ID:
1037     case AXP809_ID:
1038         min = 1800;
1039         max = 4050;
1040         def = 3000;
1041         step = 150;
1042         break;
1043     default:
1044         dev_err(&pdev->dev,
1045             "Setting DCDC frequency for unsupported AXP variant\n");
1046         return -EINVAL;
1047     }
1048 
1049     if (dcdcfreq == 0)
1050         dcdcfreq = def;
1051 
1052     if (dcdcfreq < min) {
1053         dcdcfreq = min;
1054         dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
1055              min);
1056     }
1057 
1058     if (dcdcfreq > max) {
1059         dcdcfreq = max;
1060         dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
1061              max);
1062     }
1063 
1064     dcdcfreq = (dcdcfreq - min) / step;
1065 
1066     return regmap_update_bits(axp20x->regmap, reg,
1067                   AXP20X_FREQ_DCDC_MASK, dcdcfreq);
1068 }
1069 
1070 static int axp20x_regulator_parse_dt(struct platform_device *pdev)
1071 {
1072     struct device_node *np, *regulators;
1073     int ret = 0;
1074     u32 dcdcfreq = 0;
1075 
1076     np = of_node_get(pdev->dev.parent->of_node);
1077     if (!np)
1078         return 0;
1079 
1080     regulators = of_get_child_by_name(np, "regulators");
1081     if (!regulators) {
1082         dev_warn(&pdev->dev, "regulators node not found\n");
1083     } else {
1084         of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
1085         ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
1086         if (ret < 0) {
1087             dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
1088         }
1089         of_node_put(regulators);
1090     }
1091 
1092     of_node_put(np);
1093     return ret;
1094 }
1095 
1096 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
1097 {
1098     struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
1099     unsigned int reg = AXP20X_DCDC_MODE;
1100     unsigned int mask;
1101 
1102     switch (axp20x->variant) {
1103     case AXP202_ID:
1104     case AXP209_ID:
1105         if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
1106             return -EINVAL;
1107 
1108         mask = AXP20X_WORKMODE_DCDC2_MASK;
1109         if (id == AXP20X_DCDC3)
1110             mask = AXP20X_WORKMODE_DCDC3_MASK;
1111 
1112         workmode <<= ffs(mask) - 1;
1113         break;
1114 
1115     case AXP806_ID:
1116         /*
1117          * AXP806 DCDC regulator IDs have the same range as AXP22X.
1118          * (See include/linux/mfd/axp20x.h)
1119          */
1120         reg = AXP806_DCDC_MODE_CTRL2;
1121         fallthrough;    /* to the check below */
1122     case AXP221_ID:
1123     case AXP223_ID:
1124     case AXP809_ID:
1125         if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
1126             return -EINVAL;
1127 
1128         mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
1129         workmode <<= id - AXP22X_DCDC1;
1130         break;
1131 
1132     case AXP803_ID:
1133         if (id < AXP803_DCDC1 || id > AXP803_DCDC6)
1134             return -EINVAL;
1135 
1136         mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);
1137         workmode <<= id - AXP803_DCDC1;
1138         break;
1139 
1140     case AXP813_ID:
1141         if (id < AXP813_DCDC1 || id > AXP813_DCDC7)
1142             return -EINVAL;
1143 
1144         mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);
1145         workmode <<= id - AXP813_DCDC1;
1146         break;
1147 
1148     default:
1149         /* should not happen */
1150         WARN_ON(1);
1151         return -EINVAL;
1152     }
1153 
1154     return regmap_update_bits(rdev->regmap, reg, mask, workmode);
1155 }
1156 
1157 /*
1158  * This function checks whether a regulator is part of a poly-phase
1159  * output setup based on the registers settings. Returns true if it is.
1160  */
1161 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
1162 {
1163     u32 reg = 0;
1164 
1165     /*
1166      * Currently in our supported AXP variants, only AXP803, AXP806,
1167      * and AXP813 have polyphase regulators.
1168      */
1169     switch (axp20x->variant) {
1170     case AXP803_ID:
1171     case AXP813_ID:
1172         regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, &reg);
1173 
1174         switch (id) {
1175         case AXP803_DCDC3:
1176             return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
1177         case AXP803_DCDC6:
1178             return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
1179         }
1180         break;
1181 
1182     case AXP806_ID:
1183         regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, &reg);
1184 
1185         switch (id) {
1186         case AXP806_DCDCB:
1187             return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1188                 AXP806_DCDCAB_POLYPHASE_DUAL) ||
1189                 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1190                 AXP806_DCDCABC_POLYPHASE_TRI));
1191         case AXP806_DCDCC:
1192             return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1193                 AXP806_DCDCABC_POLYPHASE_TRI);
1194         case AXP806_DCDCE:
1195             return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
1196         }
1197         break;
1198 
1199     default:
1200         return false;
1201     }
1202 
1203     return false;
1204 }
1205 
1206 static int axp20x_regulator_probe(struct platform_device *pdev)
1207 {
1208     struct regulator_dev *rdev;
1209     struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1210     const struct regulator_desc *regulators;
1211     struct regulator_config config = {
1212         .dev = pdev->dev.parent,
1213         .regmap = axp20x->regmap,
1214         .driver_data = axp20x,
1215     };
1216     int ret, i, nregulators;
1217     u32 workmode;
1218     const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
1219     const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
1220     bool drivevbus = false;
1221 
1222     switch (axp20x->variant) {
1223     case AXP202_ID:
1224     case AXP209_ID:
1225         regulators = axp20x_regulators;
1226         nregulators = AXP20X_REG_ID_MAX;
1227         break;
1228     case AXP221_ID:
1229     case AXP223_ID:
1230         regulators = axp22x_regulators;
1231         nregulators = AXP22X_REG_ID_MAX;
1232         drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1233                           "x-powers,drive-vbus-en");
1234         break;
1235     case AXP803_ID:
1236         regulators = axp803_regulators;
1237         nregulators = AXP803_REG_ID_MAX;
1238         drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1239                           "x-powers,drive-vbus-en");
1240         break;
1241     case AXP806_ID:
1242         regulators = axp806_regulators;
1243         nregulators = AXP806_REG_ID_MAX;
1244         break;
1245     case AXP809_ID:
1246         regulators = axp809_regulators;
1247         nregulators = AXP809_REG_ID_MAX;
1248         break;
1249     case AXP813_ID:
1250         regulators = axp813_regulators;
1251         nregulators = AXP813_REG_ID_MAX;
1252         drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1253                           "x-powers,drive-vbus-en");
1254         break;
1255     default:
1256         dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
1257             axp20x->variant);
1258         return -EINVAL;
1259     }
1260 
1261     /* This only sets the dcdc freq. Ignore any errors */
1262     axp20x_regulator_parse_dt(pdev);
1263 
1264     for (i = 0; i < nregulators; i++) {
1265         const struct regulator_desc *desc = &regulators[i];
1266         struct regulator_desc *new_desc;
1267 
1268         /*
1269          * If this regulator is a slave in a poly-phase setup,
1270          * skip it, as its controls are bound to the master
1271          * regulator and won't work.
1272          */
1273         if (axp20x_is_polyphase_slave(axp20x, i))
1274             continue;
1275 
1276         /* Support for AXP813's FLDO3 is not implemented */
1277         if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)
1278             continue;
1279 
1280         /*
1281          * Regulators DC1SW and DC5LDO are connected internally,
1282          * so we have to handle their supply names separately.
1283          *
1284          * We always register the regulators in proper sequence,
1285          * so the supply names are correctly read. See the last
1286          * part of this loop to see where we save the DT defined
1287          * name.
1288          */
1289         if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
1290             (regulators == axp803_regulators && i == AXP803_DC1SW) ||
1291             (regulators == axp809_regulators && i == AXP809_DC1SW)) {
1292             new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1293                         GFP_KERNEL);
1294             if (!new_desc)
1295                 return -ENOMEM;
1296 
1297             *new_desc = regulators[i];
1298             new_desc->supply_name = dcdc1_name;
1299             desc = new_desc;
1300         }
1301 
1302         if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
1303             (regulators == axp809_regulators && i == AXP809_DC5LDO)) {
1304             new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1305                         GFP_KERNEL);
1306             if (!new_desc)
1307                 return -ENOMEM;
1308 
1309             *new_desc = regulators[i];
1310             new_desc->supply_name = dcdc5_name;
1311             desc = new_desc;
1312         }
1313 
1314         rdev = devm_regulator_register(&pdev->dev, desc, &config);
1315         if (IS_ERR(rdev)) {
1316             dev_err(&pdev->dev, "Failed to register %s\n",
1317                 regulators[i].name);
1318 
1319             return PTR_ERR(rdev);
1320         }
1321 
1322         ret = of_property_read_u32(rdev->dev.of_node,
1323                        "x-powers,dcdc-workmode",
1324                        &workmode);
1325         if (!ret) {
1326             if (axp20x_set_dcdc_workmode(rdev, i, workmode))
1327                 dev_err(&pdev->dev, "Failed to set workmode on %s\n",
1328                     rdev->desc->name);
1329         }
1330 
1331         /*
1332          * Save AXP22X DCDC1 / DCDC5 regulator names for later.
1333          */
1334         if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
1335             (regulators == axp809_regulators && i == AXP809_DCDC1))
1336             of_property_read_string(rdev->dev.of_node,
1337                         "regulator-name",
1338                         &dcdc1_name);
1339 
1340         if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
1341             (regulators == axp809_regulators && i == AXP809_DCDC5))
1342             of_property_read_string(rdev->dev.of_node,
1343                         "regulator-name",
1344                         &dcdc5_name);
1345     }
1346 
1347     if (drivevbus) {
1348         /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
1349         regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
1350                    AXP22X_MISC_N_VBUSEN_FUNC, 0);
1351         rdev = devm_regulator_register(&pdev->dev,
1352                            &axp22x_drivevbus_regulator,
1353                            &config);
1354         if (IS_ERR(rdev)) {
1355             dev_err(&pdev->dev, "Failed to register drivevbus\n");
1356             return PTR_ERR(rdev);
1357         }
1358     }
1359 
1360     return 0;
1361 }
1362 
1363 static struct platform_driver axp20x_regulator_driver = {
1364     .probe  = axp20x_regulator_probe,
1365     .driver = {
1366         .name       = "axp20x-regulator",
1367     },
1368 };
1369 
1370 module_platform_driver(axp20x_regulator_driver);
1371 
1372 MODULE_LICENSE("GPL v2");
1373 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1374 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
1375 MODULE_ALIAS("platform:axp20x-regulator");
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