Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
0004 
0005 #include <linux/slab.h>
0006 #include <linux/device.h>
0007 #include <linux/module.h>
0008 #include <linux/mfd/syscon.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/regmap.h>
0015 #include <linux/regulator/driver.h>
0016 #include <linux/regulator/of_regulator.h>
0017 #include <linux/regulator/machine.h>
0018 
0019 #define LDO_RAMP_UP_UNIT_IN_CYCLES      64 /* 64 cycles per step */
0020 #define LDO_RAMP_UP_FREQ_IN_MHZ         24 /* cycle based on 24M OSC */
0021 
0022 #define LDO_POWER_GATE          0x00
0023 #define LDO_FET_FULL_ON         0x1f
0024 
0025 struct anatop_regulator {
0026     u32 delay_reg;
0027     int delay_bit_shift;
0028     int delay_bit_width;
0029     struct regulator_desc rdesc;
0030     bool bypass;
0031     int sel;
0032 };
0033 
0034 static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
0035     unsigned int old_sel,
0036     unsigned int new_sel)
0037 {
0038     struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
0039     u32 val;
0040     int ret = 0;
0041 
0042     /* check whether need to care about LDO ramp up speed */
0043     if (anatop_reg->delay_bit_width && new_sel > old_sel) {
0044         /*
0045          * the delay for LDO ramp up time is
0046          * based on the register setting, we need
0047          * to calculate how many steps LDO need to
0048          * ramp up, and how much delay needed. (us)
0049          */
0050         regmap_read(reg->regmap, anatop_reg->delay_reg, &val);
0051         val = (val >> anatop_reg->delay_bit_shift) &
0052             ((1 << anatop_reg->delay_bit_width) - 1);
0053         ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
0054             val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
0055     }
0056 
0057     return ret;
0058 }
0059 
0060 static int anatop_regmap_enable(struct regulator_dev *reg)
0061 {
0062     struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
0063     int sel;
0064 
0065     sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
0066     return regulator_set_voltage_sel_regmap(reg, sel);
0067 }
0068 
0069 static int anatop_regmap_disable(struct regulator_dev *reg)
0070 {
0071     return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
0072 }
0073 
0074 static int anatop_regmap_is_enabled(struct regulator_dev *reg)
0075 {
0076     return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
0077 }
0078 
0079 static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
0080                           unsigned selector)
0081 {
0082     struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
0083     int ret;
0084 
0085     if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
0086         anatop_reg->sel = selector;
0087         return 0;
0088     }
0089 
0090     ret = regulator_set_voltage_sel_regmap(reg, selector);
0091     if (!ret)
0092         anatop_reg->sel = selector;
0093     return ret;
0094 }
0095 
0096 static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
0097 {
0098     struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
0099 
0100     if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
0101         return anatop_reg->sel;
0102 
0103     return regulator_get_voltage_sel_regmap(reg);
0104 }
0105 
0106 static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable)
0107 {
0108     struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
0109     int sel;
0110 
0111     sel = regulator_get_voltage_sel_regmap(reg);
0112     if (sel == LDO_FET_FULL_ON)
0113         WARN_ON(!anatop_reg->bypass);
0114     else if (sel != LDO_POWER_GATE)
0115         WARN_ON(anatop_reg->bypass);
0116 
0117     *enable = anatop_reg->bypass;
0118     return 0;
0119 }
0120 
0121 static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
0122 {
0123     struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
0124     int sel;
0125 
0126     if (enable == anatop_reg->bypass)
0127         return 0;
0128 
0129     sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
0130     anatop_reg->bypass = enable;
0131 
0132     return regulator_set_voltage_sel_regmap(reg, sel);
0133 }
0134 
0135 static struct regulator_ops anatop_rops = {
0136     .set_voltage_sel = regulator_set_voltage_sel_regmap,
0137     .get_voltage_sel = regulator_get_voltage_sel_regmap,
0138     .list_voltage = regulator_list_voltage_linear,
0139     .map_voltage = regulator_map_voltage_linear,
0140 };
0141 
0142 static const struct regulator_ops anatop_core_rops = {
0143     .enable = anatop_regmap_enable,
0144     .disable = anatop_regmap_disable,
0145     .is_enabled = anatop_regmap_is_enabled,
0146     .set_voltage_sel = anatop_regmap_core_set_voltage_sel,
0147     .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
0148     .get_voltage_sel = anatop_regmap_core_get_voltage_sel,
0149     .list_voltage = regulator_list_voltage_linear,
0150     .map_voltage = regulator_map_voltage_linear,
0151     .get_bypass = anatop_regmap_get_bypass,
0152     .set_bypass = anatop_regmap_set_bypass,
0153 };
0154 
0155 static int anatop_regulator_probe(struct platform_device *pdev)
0156 {
0157     struct device *dev = &pdev->dev;
0158     struct device_node *np = dev->of_node;
0159     struct device_node *anatop_np;
0160     struct regulator_desc *rdesc;
0161     struct regulator_dev *rdev;
0162     struct anatop_regulator *sreg;
0163     struct regulator_init_data *initdata;
0164     struct regulator_config config = { };
0165     struct regmap *regmap;
0166     u32 control_reg;
0167     u32 vol_bit_shift;
0168     u32 vol_bit_width;
0169     u32 min_bit_val;
0170     u32 min_voltage;
0171     u32 max_voltage;
0172     int ret = 0;
0173     u32 val;
0174 
0175     sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
0176     if (!sreg)
0177         return -ENOMEM;
0178 
0179     rdesc = &sreg->rdesc;
0180     rdesc->type = REGULATOR_VOLTAGE;
0181     rdesc->owner = THIS_MODULE;
0182 
0183     of_property_read_string(np, "regulator-name", &rdesc->name);
0184     if (!rdesc->name) {
0185         dev_err(dev, "failed to get a regulator-name\n");
0186         return -EINVAL;
0187     }
0188 
0189     initdata = of_get_regulator_init_data(dev, np, rdesc);
0190     if (!initdata)
0191         return -ENOMEM;
0192 
0193     initdata->supply_regulator = "vin";
0194 
0195     anatop_np = of_get_parent(np);
0196     if (!anatop_np)
0197         return -ENODEV;
0198     regmap = syscon_node_to_regmap(anatop_np);
0199     of_node_put(anatop_np);
0200     if (IS_ERR(regmap))
0201         return PTR_ERR(regmap);
0202 
0203     ret = of_property_read_u32(np, "anatop-reg-offset", &control_reg);
0204     if (ret) {
0205         dev_err(dev, "no anatop-reg-offset property set\n");
0206         return ret;
0207     }
0208     ret = of_property_read_u32(np, "anatop-vol-bit-width", &vol_bit_width);
0209     if (ret) {
0210         dev_err(dev, "no anatop-vol-bit-width property set\n");
0211         return ret;
0212     }
0213     ret = of_property_read_u32(np, "anatop-vol-bit-shift", &vol_bit_shift);
0214     if (ret) {
0215         dev_err(dev, "no anatop-vol-bit-shift property set\n");
0216         return ret;
0217     }
0218     ret = of_property_read_u32(np, "anatop-min-bit-val", &min_bit_val);
0219     if (ret) {
0220         dev_err(dev, "no anatop-min-bit-val property set\n");
0221         return ret;
0222     }
0223     ret = of_property_read_u32(np, "anatop-min-voltage", &min_voltage);
0224     if (ret) {
0225         dev_err(dev, "no anatop-min-voltage property set\n");
0226         return ret;
0227     }
0228     ret = of_property_read_u32(np, "anatop-max-voltage", &max_voltage);
0229     if (ret) {
0230         dev_err(dev, "no anatop-max-voltage property set\n");
0231         return ret;
0232     }
0233 
0234     /* read LDO ramp up setting, only for core reg */
0235     of_property_read_u32(np, "anatop-delay-reg-offset",
0236                  &sreg->delay_reg);
0237     of_property_read_u32(np, "anatop-delay-bit-width",
0238                  &sreg->delay_bit_width);
0239     of_property_read_u32(np, "anatop-delay-bit-shift",
0240                  &sreg->delay_bit_shift);
0241 
0242     rdesc->n_voltages = (max_voltage - min_voltage) / 25000 + 1
0243                 + min_bit_val;
0244     rdesc->min_uV = min_voltage;
0245     rdesc->uV_step = 25000;
0246     rdesc->linear_min_sel = min_bit_val;
0247     rdesc->vsel_reg = control_reg;
0248     rdesc->vsel_mask = ((1 << vol_bit_width) - 1) << vol_bit_shift;
0249     rdesc->min_dropout_uV = 125000;
0250 
0251     config.dev = &pdev->dev;
0252     config.init_data = initdata;
0253     config.driver_data = sreg;
0254     config.of_node = pdev->dev.of_node;
0255     config.regmap = regmap;
0256 
0257     /* Only core regulators have the ramp up delay configuration. */
0258     if (control_reg && sreg->delay_bit_width) {
0259         rdesc->ops = &anatop_core_rops;
0260 
0261         ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
0262         if (ret) {
0263             dev_err(dev, "failed to read initial state\n");
0264             return ret;
0265         }
0266 
0267         sreg->sel = (val & rdesc->vsel_mask) >> vol_bit_shift;
0268         if (sreg->sel == LDO_FET_FULL_ON) {
0269             sreg->sel = 0;
0270             sreg->bypass = true;
0271         }
0272 
0273         /*
0274          * In case vddpu was disabled by the bootloader, we need to set
0275          * a sane default until imx6-cpufreq was probed and changes the
0276          * voltage to the correct value. In this case we set 1.25V.
0277          */
0278         if (!sreg->sel && !strcmp(rdesc->name, "vddpu"))
0279             sreg->sel = 22;
0280 
0281         /* set the default voltage of the pcie phy to be 1.100v */
0282         if (!sreg->sel && !strcmp(rdesc->name, "vddpcie"))
0283             sreg->sel = 0x10;
0284 
0285         if (!sreg->bypass && !sreg->sel) {
0286             dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
0287             return -EINVAL;
0288         }
0289     } else {
0290         u32 enable_bit;
0291 
0292         rdesc->ops = &anatop_rops;
0293 
0294         if (!of_property_read_u32(np, "anatop-enable-bit",
0295                       &enable_bit)) {
0296             anatop_rops.enable  = regulator_enable_regmap;
0297             anatop_rops.disable = regulator_disable_regmap;
0298             anatop_rops.is_enabled = regulator_is_enabled_regmap;
0299 
0300             rdesc->enable_reg = control_reg;
0301             rdesc->enable_mask = BIT(enable_bit);
0302         }
0303     }
0304 
0305     /* register regulator */
0306     rdev = devm_regulator_register(dev, rdesc, &config);
0307     if (IS_ERR(rdev)) {
0308         ret = PTR_ERR(rdev);
0309         if (ret == -EPROBE_DEFER)
0310             dev_dbg(dev, "failed to register %s, deferring...\n",
0311                 rdesc->name);
0312         else
0313             dev_err(dev, "failed to register %s\n", rdesc->name);
0314         return ret;
0315     }
0316 
0317     platform_set_drvdata(pdev, rdev);
0318 
0319     return 0;
0320 }
0321 
0322 static const struct of_device_id of_anatop_regulator_match_tbl[] = {
0323     { .compatible = "fsl,anatop-regulator", },
0324     { /* end */ }
0325 };
0326 MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);
0327 
0328 static struct platform_driver anatop_regulator_driver = {
0329     .driver = {
0330         .name   = "anatop_regulator",
0331         .of_match_table = of_anatop_regulator_match_tbl,
0332     },
0333     .probe  = anatop_regulator_probe,
0334 };
0335 
0336 static int __init anatop_regulator_init(void)
0337 {
0338     return platform_driver_register(&anatop_regulator_driver);
0339 }
0340 postcore_initcall(anatop_regulator_init);
0341 
0342 static void __exit anatop_regulator_exit(void)
0343 {
0344     platform_driver_unregister(&anatop_regulator_driver);
0345 }
0346 module_exit(anatop_regulator_exit);
0347 
0348 MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
0349 MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
0350 MODULE_DESCRIPTION("ANATOP Regulator driver");
0351 MODULE_LICENSE("GPL v2");
0352 MODULE_ALIAS("platform:anatop_regulator");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!