drivers/pwm/pwm-xilinx.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2021 Sean Anderson <sean.anderson@seco.com>
0004  *
0005  * Limitations:
0006  * - When changing both duty cycle and period, we may end up with one cycle
0007  *   with the old duty cycle and the new period. This is because the counters
0008  *   may only be reloaded by first stopping them, or by letting them be
0009  *   automatically reloaded at the end of a cycle. If this automatic reload
0010  *   happens after we set TLR0 but before we set TLR1 then we will have a
0011  *   bad cycle. This could probably be fixed by reading TCR0 just before
0012  *   reprogramming, but I think it would add complexity for little gain.
0013  * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
0014  *   possible by stopping the counters at an appropriate point in the cycle,
0015  *   but this is not (yet) implemented.
0016  * - Only produces "normal" output.
0017  * - Always produces low output if disabled.
0018  */
0019
0020 #include <clocksource/timer-xilinx.h>
0021 #include <linux/clk.h>
0022 #include <linux/clk-provider.h>
0023 #include <linux/device.h>
0024 #include <linux/module.h>
0025 #include <linux/of.h>
0026 #include <linux/platform_device.h>
0027 #include <linux/pwm.h>
0028 #include <linux/regmap.h>
0029
0030 /*
0031  * The following functions are "common" to drivers for this device, and may be
0032  * exported at a future date.
0033  */
0034 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
0035                 u64 cycles)
0036 {
0037     WARN_ON(cycles < 2 || cycles - 2 > priv->max);
0038
0039     if (tcsr & TCSR_UDT)
0040         return cycles - 2;
0041     return priv->max - cycles + 2;
0042 }
0043
0044 unsigned int xilinx_timer_get_period(struct xilinx_timer_priv *priv,
0045                      u32 tlr, u32 tcsr)
0046 {
0047     u64 cycles;
0048
0049     if (tcsr & TCSR_UDT)
0050         cycles = tlr + 2;
0051     else
0052         cycles = (u64)priv->max - tlr + 2;
0053
0054     /* cycles has a max of 2^32 + 2, so we can't overflow */
0055     return DIV64_U64_ROUND_UP(cycles * NSEC_PER_SEC,
0056                   clk_get_rate(priv->clk));
0057 }
0058
0059 /*
0060  * The idea here is to capture whether the PWM is actually running (e.g.
0061  * because we or the bootloader set it up) and we need to be careful to ensure
0062  * we don't cause a glitch. According to the data sheet, to enable the PWM we
0063  * need to
0064  *
0065  * - Set both timers to generate mode (MDT=1)
0066  * - Set both timers to PWM mode (PWMA=1)
0067  * - Enable the generate out signals (GENT=1)
0068  *
0069  * In addition,
0070  *
0071  * - The timer must be running (ENT=1)
0072  * - The timer must auto-reload TLR into TCR (ARHT=1)
0073  * - We must not be in the process of loading TLR into TCR (LOAD=0)
0074  * - Cascade mode must be disabled (CASC=0)
0075  *
0076  * If any of these differ from usual, then the PWM is either disabled, or is
0077  * running in a mode that this driver does not support.
0078  */
0079 #define TCSR_PWM_SET (TCSR_GENT | TCSR_ARHT | TCSR_ENT | TCSR_PWMA)
0080 #define TCSR_PWM_CLEAR (TCSR_MDT | TCSR_LOAD)
0081 #define TCSR_PWM_MASK (TCSR_PWM_SET | TCSR_PWM_CLEAR)
0082
0083 struct xilinx_pwm_device {
0084     struct pwm_chip chip;
0085     struct xilinx_timer_priv priv;
0086 };
0087
0088 static inline struct xilinx_timer_priv
0089 *xilinx_pwm_chip_to_priv(struct pwm_chip *chip)
0090 {
0091     return &container_of(chip, struct xilinx_pwm_device, chip)->priv;
0092 }
0093
0094 static bool xilinx_timer_pwm_enabled(u32 tcsr0, u32 tcsr1)
0095 {
0096     return ((TCSR_PWM_MASK | TCSR_CASC) & tcsr0) == TCSR_PWM_SET &&
0097         (TCSR_PWM_MASK & tcsr1) == TCSR_PWM_SET;
0098 }
0099
0100 static int xilinx_pwm_apply(struct pwm_chip *chip, struct pwm_device *unused,
0101                 const struct pwm_state *state)
0102 {
0103     struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip);
0104     u32 tlr0, tlr1, tcsr0, tcsr1;
0105     u64 period_cycles, duty_cycles;
0106     unsigned long rate;
0107
0108     if (state->polarity != PWM_POLARITY_NORMAL)
0109         return -EINVAL;
0110
0111     /*
0112      * To be representable by TLR, cycles must be between 2 and
0113      * priv->max + 2. To enforce this we can reduce the cycles, but we may
0114      * not increase them. Caveat emptor: while this does result in more
0115      * predictable rounding, it may also result in a completely different
0116      * duty cycle (% high time) than what was requested.
0117      */
0118     rate = clk_get_rate(priv->clk);
0119     /* Avoid overflow */
0120     period_cycles = min_t(u64, state->period, U32_MAX * NSEC_PER_SEC);
0121     period_cycles = mul_u64_u32_div(period_cycles, rate, NSEC_PER_SEC);
0122     period_cycles = min_t(u64, period_cycles, priv->max + 2);
0123     if (period_cycles < 2)
0124         return -ERANGE;
0125
0126     /* Same thing for duty cycles */
0127     duty_cycles = min_t(u64, state->duty_cycle, U32_MAX * NSEC_PER_SEC);
0128     duty_cycles = mul_u64_u32_div(duty_cycles, rate, NSEC_PER_SEC);
0129     duty_cycles = min_t(u64, duty_cycles, priv->max + 2);
0130
0131     /*
0132      * If we specify 100% duty cycle, we will get 0% instead, so decrease
0133      * the duty cycle count by one.
0134      */
0135     if (duty_cycles >= period_cycles)
0136         duty_cycles = period_cycles - 1;
0137
0138     /* Round down to 0% duty cycle for unrepresentable duty cycles */
0139     if (duty_cycles < 2)
0140         duty_cycles = period_cycles;
0141
0142     regmap_read(priv->map, TCSR0, &tcsr0);
0143     regmap_read(priv->map, TCSR1, &tcsr1);
0144     tlr0 = xilinx_timer_tlr_cycles(priv, tcsr0, period_cycles);
0145     tlr1 = xilinx_timer_tlr_cycles(priv, tcsr1, duty_cycles);
0146     regmap_write(priv->map, TLR0, tlr0);
0147     regmap_write(priv->map, TLR1, tlr1);
0148
0149     if (state->enabled) {
0150         /*
0151          * If the PWM is already running, then the counters will be
0152          * reloaded at the end of the current cycle.
0153          */
0154         if (!xilinx_timer_pwm_enabled(tcsr0, tcsr1)) {
0155             /* Load TLR into TCR */
0156             regmap_write(priv->map, TCSR0, tcsr0 | TCSR_LOAD);
0157             regmap_write(priv->map, TCSR1, tcsr1 | TCSR_LOAD);
0158             /* Enable timers all at once with ENALL */
0159             tcsr0 = (TCSR_PWM_SET & ~TCSR_ENT) | (tcsr0 & TCSR_UDT);
0160             tcsr1 = TCSR_PWM_SET | TCSR_ENALL | (tcsr1 & TCSR_UDT);
0161             regmap_write(priv->map, TCSR0, tcsr0);
0162             regmap_write(priv->map, TCSR1, tcsr1);
0163         }
0164     } else {
0165         regmap_write(priv->map, TCSR0, 0);
0166         regmap_write(priv->map, TCSR1, 0);
0167     }
0168
0169     return 0;
0170 }
0171
0172 static void xilinx_pwm_get_state(struct pwm_chip *chip,
0173                  struct pwm_device *unused,
0174                  struct pwm_state *state)
0175 {
0176     struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip);
0177     u32 tlr0, tlr1, tcsr0, tcsr1;
0178
0179     regmap_read(priv->map, TLR0, &tlr0);
0180     regmap_read(priv->map, TLR1, &tlr1);
0181     regmap_read(priv->map, TCSR0, &tcsr0);
0182     regmap_read(priv->map, TCSR1, &tcsr1);
0183     state->period = xilinx_timer_get_period(priv, tlr0, tcsr0);
0184     state->duty_cycle = xilinx_timer_get_period(priv, tlr1, tcsr1);
0185     state->enabled = xilinx_timer_pwm_enabled(tcsr0, tcsr1);
0186     state->polarity = PWM_POLARITY_NORMAL;
0187
0188     /*
0189      * 100% duty cycle results in constant low output. This may be (very)
0190      * wrong if rate > 1 GHz, so fix this if you have such hardware :)
0191      */
0192     if (state->period == state->duty_cycle)
0193         state->duty_cycle = 0;
0194 }
0195
0196 static const struct pwm_ops xilinx_pwm_ops = {
0197     .apply = xilinx_pwm_apply,
0198     .get_state = xilinx_pwm_get_state,
0199     .owner = THIS_MODULE,
0200 };
0201
0202 static const struct regmap_config xilinx_pwm_regmap_config = {
0203     .reg_bits = 32,
0204     .reg_stride = 4,
0205     .val_bits = 32,
0206     .val_format_endian = REGMAP_ENDIAN_LITTLE,
0207     .max_register = TCR1,
0208 };
0209
0210 static int xilinx_pwm_probe(struct platform_device *pdev)
0211 {
0212     int ret;
0213     struct device *dev = &pdev->dev;
0214     struct device_node *np = dev->of_node;
0215     struct xilinx_timer_priv *priv;
0216     struct xilinx_pwm_device *xilinx_pwm;
0217     u32 pwm_cells, one_timer, width;
0218     void __iomem *regs;
0219
0220     /* If there are no PWM cells, this binding is for a timer */
0221     ret = of_property_read_u32(np, "#pwm-cells", &pwm_cells);
0222     if (ret == -EINVAL)
0223         return -ENODEV;
0224     if (ret)
0225         return dev_err_probe(dev, ret, "could not read #pwm-cells\n");
0226
0227     xilinx_pwm = devm_kzalloc(dev, sizeof(*xilinx_pwm), GFP_KERNEL);
0228     if (!xilinx_pwm)
0229         return -ENOMEM;
0230     platform_set_drvdata(pdev, xilinx_pwm);
0231     priv = &xilinx_pwm->priv;
0232
0233     regs = devm_platform_ioremap_resource(pdev, 0);
0234     if (IS_ERR(regs))
0235         return PTR_ERR(regs);
0236
0237     priv->map = devm_regmap_init_mmio(dev, regs,
0238                       &xilinx_pwm_regmap_config);
0239     if (IS_ERR(priv->map))
0240         return dev_err_probe(dev, PTR_ERR(priv->map),
0241                      "Could not create regmap\n");
0242
0243     ret = of_property_read_u32(np, "xlnx,one-timer-only", &one_timer);
0244     if (ret)
0245         return dev_err_probe(dev, ret,
0246                      "Could not read xlnx,one-timer-only\n");
0247
0248     if (one_timer)
0249         return dev_err_probe(dev, -EINVAL,
0250                      "Two timers required for PWM mode\n");
0251
0252     ret = of_property_read_u32(np, "xlnx,count-width", &width);
0253     if (ret == -EINVAL)
0254         width = 32;
0255     else if (ret)
0256         return dev_err_probe(dev, ret,
0257                      "Could not read xlnx,count-width\n");
0258
0259     if (width != 8 && width != 16 && width != 32)
0260         return dev_err_probe(dev, -EINVAL,
0261                      "Invalid counter width %d\n", width);
0262     priv->max = BIT_ULL(width) - 1;
0263
0264     /*
0265      * The polarity of the Generate Out signals must be active high for PWM
0266      * mode to work. We could determine this from the device tree, but
0267      * alas, such properties are not allowed to be used.
0268      */
0269
0270     priv->clk = devm_clk_get(dev, "s_axi_aclk");
0271     if (IS_ERR(priv->clk))
0272         return dev_err_probe(dev, PTR_ERR(priv->clk),
0273                      "Could not get clock\n");
0274
0275     ret = clk_prepare_enable(priv->clk);
0276     if (ret)
0277         return dev_err_probe(dev, ret, "Clock enable failed\n");
0278     clk_rate_exclusive_get(priv->clk);
0279
0280     xilinx_pwm->chip.dev = dev;
0281     xilinx_pwm->chip.ops = &xilinx_pwm_ops;
0282     xilinx_pwm->chip.npwm = 1;
0283     ret = pwmchip_add(&xilinx_pwm->chip);
0284     if (ret) {
0285         clk_rate_exclusive_put(priv->clk);
0286         clk_disable_unprepare(priv->clk);
0287         return dev_err_probe(dev, ret, "Could not register PWM chip\n");
0288     }
0289
0290     return 0;
0291 }
0292
0293 static int xilinx_pwm_remove(struct platform_device *pdev)
0294 {
0295     struct xilinx_pwm_device *xilinx_pwm = platform_get_drvdata(pdev);
0296
0297     pwmchip_remove(&xilinx_pwm->chip);
0298     clk_rate_exclusive_put(xilinx_pwm->priv.clk);
0299     clk_disable_unprepare(xilinx_pwm->priv.clk);
0300     return 0;
0301 }
0302
0303 static const struct of_device_id xilinx_pwm_of_match[] = {
0304     { .compatible = "xlnx,xps-timer-1.00.a", },
0305     {},
0306 };
0307 MODULE_DEVICE_TABLE(of, xilinx_pwm_of_match);
0308
0309 static struct platform_driver xilinx_pwm_driver = {
0310     .probe = xilinx_pwm_probe,
0311     .remove = xilinx_pwm_remove,
0312     .driver = {
0313         .name = "xilinx-pwm",
0314         .of_match_table = of_match_ptr(xilinx_pwm_of_match),
0315     },
0316 };
0317 module_platform_driver(xilinx_pwm_driver);
0318
0319 MODULE_ALIAS("platform:xilinx-pwm");
0320 MODULE_DESCRIPTION("PWM driver for Xilinx LogiCORE IP AXI Timer");
0321 MODULE_LICENSE("GPL");