drivers/pwm/pwm-vt8500.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * drivers/pwm/pwm-vt8500.c
0004  *
0005  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
0006  * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
0007  */
0008
0009 #include <linux/module.h>
0010 #include <linux/kernel.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/slab.h>
0013 #include <linux/err.h>
0014 #include <linux/io.h>
0015 #include <linux/pwm.h>
0016 #include <linux/delay.h>
0017 #include <linux/clk.h>
0018
0019 #include <asm/div64.h>
0020
0021 #include <linux/of.h>
0022 #include <linux/of_device.h>
0023 #include <linux/of_address.h>
0024
0025 /*
0026  * SoC architecture allocates register space for 4 PWMs but only
0027  * 2 are currently implemented.
0028  */
0029 #define VT8500_NR_PWMS  2
0030
0031 #define REG_CTRL(pwm)       (((pwm) << 4) + 0x00)
0032 #define REG_SCALAR(pwm)     (((pwm) << 4) + 0x04)
0033 #define REG_PERIOD(pwm)     (((pwm) << 4) + 0x08)
0034 #define REG_DUTY(pwm)       (((pwm) << 4) + 0x0C)
0035 #define REG_STATUS      0x40
0036
0037 #define CTRL_ENABLE     BIT(0)
0038 #define CTRL_INVERT     BIT(1)
0039 #define CTRL_AUTOLOAD       BIT(2)
0040 #define CTRL_STOP_IMM       BIT(3)
0041 #define CTRL_LOAD_PRESCALE  BIT(4)
0042 #define CTRL_LOAD_PERIOD    BIT(5)
0043
0044 #define STATUS_CTRL_UPDATE  BIT(0)
0045 #define STATUS_SCALAR_UPDATE    BIT(1)
0046 #define STATUS_PERIOD_UPDATE    BIT(2)
0047 #define STATUS_DUTY_UPDATE  BIT(3)
0048 #define STATUS_ALL_UPDATE   0x0F
0049
0050 struct vt8500_chip {
0051     struct pwm_chip chip;
0052     void __iomem *base;
0053     struct clk *clk;
0054 };
0055
0056 #define to_vt8500_chip(chip)    container_of(chip, struct vt8500_chip, chip)
0057
0058 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
0059 static inline void vt8500_pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
0060 {
0061     int loops = msecs_to_loops(10);
0062     u32 mask = bitmask << (nr << 8);
0063
0064     while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
0065         cpu_relax();
0066
0067     if (unlikely(!loops))
0068         dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
0069              mask);
0070 }
0071
0072 static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
0073         u64 duty_ns, u64 period_ns)
0074 {
0075     struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
0076     unsigned long long c;
0077     unsigned long period_cycles, prescale, pv, dc;
0078     int err;
0079     u32 val;
0080
0081     err = clk_enable(vt8500->clk);
0082     if (err < 0) {
0083         dev_err(chip->dev, "failed to enable clock\n");
0084         return err;
0085     }
0086
0087     c = clk_get_rate(vt8500->clk);
0088     c = c * period_ns;
0089     do_div(c, 1000000000);
0090     period_cycles = c;
0091
0092     if (period_cycles < 1)
0093         period_cycles = 1;
0094     prescale = (period_cycles - 1) / 4096;
0095     pv = period_cycles / (prescale + 1) - 1;
0096     if (pv > 4095)
0097         pv = 4095;
0098
0099     if (prescale > 1023) {
0100         clk_disable(vt8500->clk);
0101         return -EINVAL;
0102     }
0103
0104     c = (unsigned long long)pv * duty_ns;
0105
0106     dc = div64_u64(c, period_ns);
0107
0108     writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
0109     vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);
0110
0111     writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
0112     vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);
0113
0114     writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
0115     vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);
0116
0117     val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
0118     val |= CTRL_AUTOLOAD;
0119     writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
0120     vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
0121
0122     clk_disable(vt8500->clk);
0123     return 0;
0124 }
0125
0126 static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
0127 {
0128     struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
0129     int err;
0130     u32 val;
0131
0132     err = clk_enable(vt8500->clk);
0133     if (err < 0) {
0134         dev_err(chip->dev, "failed to enable clock\n");
0135         return err;
0136     }
0137
0138     val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
0139     val |= CTRL_ENABLE;
0140     writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
0141     vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
0142
0143     return 0;
0144 }
0145
0146 static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
0147 {
0148     struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
0149     u32 val;
0150
0151     val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
0152     val &= ~CTRL_ENABLE;
0153     writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
0154     vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
0155
0156     clk_disable(vt8500->clk);
0157 }
0158
0159 static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
0160                    struct pwm_device *pwm,
0161                    enum pwm_polarity polarity)
0162 {
0163     struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
0164     u32 val;
0165
0166     val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
0167
0168     if (polarity == PWM_POLARITY_INVERSED)
0169         val |= CTRL_INVERT;
0170     else
0171         val &= ~CTRL_INVERT;
0172
0173     writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
0174     vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
0175
0176     return 0;
0177 }
0178
0179 static int vt8500_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0180                 const struct pwm_state *state)
0181 {
0182     int err;
0183     bool enabled = pwm->state.enabled;
0184
0185     if (state->polarity != pwm->state.polarity) {
0186         /*
0187          * Changing the polarity of a running PWM is only allowed when
0188          * the PWM driver implements ->apply().
0189          */
0190         if (enabled) {
0191             vt8500_pwm_disable(chip, pwm);
0192
0193             enabled = false;
0194         }
0195
0196         err = vt8500_pwm_set_polarity(chip, pwm, state->polarity);
0197         if (err)
0198             return err;
0199     }
0200
0201     if (!state->enabled) {
0202         if (enabled)
0203             vt8500_pwm_disable(chip, pwm);
0204
0205         return 0;
0206     }
0207
0208     /*
0209      * We cannot skip calling ->config even if state->period ==
0210      * pwm->state.period && state->duty_cycle == pwm->state.duty_cycle
0211      * because we might have exited early in the last call to
0212      * pwm_apply_state because of !state->enabled and so the two values in
0213      * pwm->state might not be configured in hardware.
0214      */
0215     err = vt8500_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
0216     if (err)
0217         return err;
0218
0219     if (!enabled)
0220         err = vt8500_pwm_enable(chip, pwm);
0221
0222     return err;
0223 }
0224
0225 static const struct pwm_ops vt8500_pwm_ops = {
0226     .apply = vt8500_pwm_apply,
0227     .owner = THIS_MODULE,
0228 };
0229
0230 static const struct of_device_id vt8500_pwm_dt_ids[] = {
0231     { .compatible = "via,vt8500-pwm", },
0232     { /* Sentinel */ }
0233 };
0234 MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);
0235
0236 static int vt8500_pwm_probe(struct platform_device *pdev)
0237 {
0238     struct vt8500_chip *vt8500;
0239     struct device_node *np = pdev->dev.of_node;
0240     int ret;
0241
0242     if (!np) {
0243         dev_err(&pdev->dev, "invalid devicetree node\n");
0244         return -EINVAL;
0245     }
0246
0247     vt8500 = devm_kzalloc(&pdev->dev, sizeof(*vt8500), GFP_KERNEL);
0248     if (vt8500 == NULL)
0249         return -ENOMEM;
0250
0251     vt8500->chip.dev = &pdev->dev;
0252     vt8500->chip.ops = &vt8500_pwm_ops;
0253     vt8500->chip.npwm = VT8500_NR_PWMS;
0254
0255     vt8500->clk = devm_clk_get(&pdev->dev, NULL);
0256     if (IS_ERR(vt8500->clk)) {
0257         dev_err(&pdev->dev, "clock source not specified\n");
0258         return PTR_ERR(vt8500->clk);
0259     }
0260
0261     vt8500->base = devm_platform_ioremap_resource(pdev, 0);
0262     if (IS_ERR(vt8500->base))
0263         return PTR_ERR(vt8500->base);
0264
0265     ret = clk_prepare(vt8500->clk);
0266     if (ret < 0) {
0267         dev_err(&pdev->dev, "failed to prepare clock\n");
0268         return ret;
0269     }
0270
0271     ret = pwmchip_add(&vt8500->chip);
0272     if (ret < 0) {
0273         dev_err(&pdev->dev, "failed to add PWM chip\n");
0274         clk_unprepare(vt8500->clk);
0275         return ret;
0276     }
0277
0278     platform_set_drvdata(pdev, vt8500);
0279     return ret;
0280 }
0281
0282 static int vt8500_pwm_remove(struct platform_device *pdev)
0283 {
0284     struct vt8500_chip *vt8500 = platform_get_drvdata(pdev);
0285
0286     pwmchip_remove(&vt8500->chip);
0287
0288     clk_unprepare(vt8500->clk);
0289
0290     return 0;
0291 }
0292
0293 static struct platform_driver vt8500_pwm_driver = {
0294     .probe      = vt8500_pwm_probe,
0295     .remove     = vt8500_pwm_remove,
0296     .driver     = {
0297         .name   = "vt8500-pwm",
0298         .of_match_table = vt8500_pwm_dt_ids,
0299     },
0300 };
0301 module_platform_driver(vt8500_pwm_driver);
0302
0303 MODULE_DESCRIPTION("VT8500 PWM Driver");
0304 MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
0305 MODULE_LICENSE("GPL v2");