drivers/pwm/pwm-tiehrpwm.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * EHRPWM PWM driver
0004  *
0005  * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
0006  */
0007
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/pwm.h>
0011 #include <linux/io.h>
0012 #include <linux/err.h>
0013 #include <linux/clk.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/of_device.h>
0016
0017 /* EHRPWM registers and bits definitions */
0018
0019 /* Time base module registers */
0020 #define TBCTL           0x00
0021 #define TBPRD           0x0A
0022
0023 #define TBCTL_PRDLD_MASK    BIT(3)
0024 #define TBCTL_PRDLD_SHDW    0
0025 #define TBCTL_PRDLD_IMDT    BIT(3)
0026 #define TBCTL_CLKDIV_MASK   (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
0027                 BIT(8) | BIT(7))
0028 #define TBCTL_CTRMODE_MASK  (BIT(1) | BIT(0))
0029 #define TBCTL_CTRMODE_UP    0
0030 #define TBCTL_CTRMODE_DOWN  BIT(0)
0031 #define TBCTL_CTRMODE_UPDOWN    BIT(1)
0032 #define TBCTL_CTRMODE_FREEZE    (BIT(1) | BIT(0))
0033
0034 #define TBCTL_HSPCLKDIV_SHIFT   7
0035 #define TBCTL_CLKDIV_SHIFT  10
0036
0037 #define CLKDIV_MAX      7
0038 #define HSPCLKDIV_MAX       7
0039 #define PERIOD_MAX      0xFFFF
0040
0041 /* compare module registers */
0042 #define CMPA            0x12
0043 #define CMPB            0x14
0044
0045 /* Action qualifier module registers */
0046 #define AQCTLA          0x16
0047 #define AQCTLB          0x18
0048 #define AQSFRC          0x1A
0049 #define AQCSFRC         0x1C
0050
0051 #define AQCTL_CBU_MASK      (BIT(9) | BIT(8))
0052 #define AQCTL_CBU_FRCLOW    BIT(8)
0053 #define AQCTL_CBU_FRCHIGH   BIT(9)
0054 #define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8))
0055 #define AQCTL_CAU_MASK      (BIT(5) | BIT(4))
0056 #define AQCTL_CAU_FRCLOW    BIT(4)
0057 #define AQCTL_CAU_FRCHIGH   BIT(5)
0058 #define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4))
0059 #define AQCTL_PRD_MASK      (BIT(3) | BIT(2))
0060 #define AQCTL_PRD_FRCLOW    BIT(2)
0061 #define AQCTL_PRD_FRCHIGH   BIT(3)
0062 #define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2))
0063 #define AQCTL_ZRO_MASK      (BIT(1) | BIT(0))
0064 #define AQCTL_ZRO_FRCLOW    BIT(0)
0065 #define AQCTL_ZRO_FRCHIGH   BIT(1)
0066 #define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0))
0067
0068 #define AQCTL_CHANA_POLNORMAL   (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \
0069                 AQCTL_ZRO_FRCHIGH)
0070 #define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \
0071                 AQCTL_ZRO_FRCLOW)
0072 #define AQCTL_CHANB_POLNORMAL   (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \
0073                 AQCTL_ZRO_FRCHIGH)
0074 #define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \
0075                 AQCTL_ZRO_FRCLOW)
0076
0077 #define AQSFRC_RLDCSF_MASK  (BIT(7) | BIT(6))
0078 #define AQSFRC_RLDCSF_ZRO   0
0079 #define AQSFRC_RLDCSF_PRD   BIT(6)
0080 #define AQSFRC_RLDCSF_ZROPRD    BIT(7)
0081 #define AQSFRC_RLDCSF_IMDT  (BIT(7) | BIT(6))
0082
0083 #define AQCSFRC_CSFB_MASK   (BIT(3) | BIT(2))
0084 #define AQCSFRC_CSFB_FRCDIS 0
0085 #define AQCSFRC_CSFB_FRCLOW BIT(2)
0086 #define AQCSFRC_CSFB_FRCHIGH    BIT(3)
0087 #define AQCSFRC_CSFB_DISSWFRC   (BIT(3) | BIT(2))
0088 #define AQCSFRC_CSFA_MASK   (BIT(1) | BIT(0))
0089 #define AQCSFRC_CSFA_FRCDIS 0
0090 #define AQCSFRC_CSFA_FRCLOW BIT(0)
0091 #define AQCSFRC_CSFA_FRCHIGH    BIT(1)
0092 #define AQCSFRC_CSFA_DISSWFRC   (BIT(1) | BIT(0))
0093
0094 #define NUM_PWM_CHANNEL     2   /* EHRPWM channels */
0095
0096 struct ehrpwm_context {
0097     u16 tbctl;
0098     u16 tbprd;
0099     u16 cmpa;
0100     u16 cmpb;
0101     u16 aqctla;
0102     u16 aqctlb;
0103     u16 aqsfrc;
0104     u16 aqcsfrc;
0105 };
0106
0107 struct ehrpwm_pwm_chip {
0108     struct pwm_chip chip;
0109     unsigned long clk_rate;
0110     void __iomem *mmio_base;
0111     unsigned long period_cycles[NUM_PWM_CHANNEL];
0112     enum pwm_polarity polarity[NUM_PWM_CHANNEL];
0113     struct clk *tbclk;
0114     struct ehrpwm_context ctx;
0115 };
0116
0117 static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip)
0118 {
0119     return container_of(chip, struct ehrpwm_pwm_chip, chip);
0120 }
0121
0122 static inline u16 ehrpwm_read(void __iomem *base, unsigned int offset)
0123 {
0124     return readw(base + offset);
0125 }
0126
0127 static inline void ehrpwm_write(void __iomem *base, unsigned int offset,
0128                 u16 value)
0129 {
0130     writew(value, base + offset);
0131 }
0132
0133 static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask,
0134               u16 value)
0135 {
0136     unsigned short val;
0137
0138     val = readw(base + offset);
0139     val &= ~mask;
0140     val |= value & mask;
0141     writew(val, base + offset);
0142 }
0143
0144 /**
0145  * set_prescale_div -   Set up the prescaler divider function
0146  * @rqst_prescaler: prescaler value min
0147  * @prescale_div:   prescaler value set
0148  * @tb_clk_div:     Time Base Control prescaler bits
0149  */
0150 static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div,
0151                 u16 *tb_clk_div)
0152 {
0153     unsigned int clkdiv, hspclkdiv;
0154
0155     for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) {
0156         for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) {
0157             /*
0158              * calculations for prescaler value :
0159              * prescale_div = HSPCLKDIVIDER * CLKDIVIDER.
0160              * HSPCLKDIVIDER =  2 ** hspclkdiv
0161              * CLKDIVIDER = (1),        if clkdiv == 0 *OR*
0162              *      (2 * clkdiv),   if clkdiv != 0
0163              *
0164              * Configure prescale_div value such that period
0165              * register value is less than 65535.
0166              */
0167
0168             *prescale_div = (1 << clkdiv) *
0169                     (hspclkdiv ? (hspclkdiv * 2) : 1);
0170             if (*prescale_div > rqst_prescaler) {
0171                 *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) |
0172                     (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT);
0173                 return 0;
0174             }
0175         }
0176     }
0177
0178     return 1;
0179 }
0180
0181 static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan)
0182 {
0183     u16 aqctl_val, aqctl_mask;
0184     unsigned int aqctl_reg;
0185
0186     /*
0187      * Configure PWM output to HIGH/LOW level on counter
0188      * reaches compare register value and LOW/HIGH level
0189      * on counter value reaches period register value and
0190      * zero value on counter
0191      */
0192     if (chan == 1) {
0193         aqctl_reg = AQCTLB;
0194         aqctl_mask = AQCTL_CBU_MASK;
0195
0196         if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
0197             aqctl_val = AQCTL_CHANB_POLINVERSED;
0198         else
0199             aqctl_val = AQCTL_CHANB_POLNORMAL;
0200     } else {
0201         aqctl_reg = AQCTLA;
0202         aqctl_mask = AQCTL_CAU_MASK;
0203
0204         if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
0205             aqctl_val = AQCTL_CHANA_POLINVERSED;
0206         else
0207             aqctl_val = AQCTL_CHANA_POLNORMAL;
0208     }
0209
0210     aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK;
0211     ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
0212 }
0213
0214 /*
0215  * period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE
0216  * duty_ns   = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE
0217  */
0218 static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
0219                  u64 duty_ns, u64 period_ns)
0220 {
0221     struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
0222     u32 period_cycles, duty_cycles;
0223     u16 ps_divval, tb_divval;
0224     unsigned int i, cmp_reg;
0225     unsigned long long c;
0226
0227     if (period_ns > NSEC_PER_SEC)
0228         return -ERANGE;
0229
0230     c = pc->clk_rate;
0231     c = c * period_ns;
0232     do_div(c, NSEC_PER_SEC);
0233     period_cycles = (unsigned long)c;
0234
0235     if (period_cycles < 1) {
0236         period_cycles = 1;
0237         duty_cycles = 1;
0238     } else {
0239         c = pc->clk_rate;
0240         c = c * duty_ns;
0241         do_div(c, NSEC_PER_SEC);
0242         duty_cycles = (unsigned long)c;
0243     }
0244
0245     /*
0246      * Period values should be same for multiple PWM channels as IP uses
0247      * same period register for multiple channels.
0248      */
0249     for (i = 0; i < NUM_PWM_CHANNEL; i++) {
0250         if (pc->period_cycles[i] &&
0251                 (pc->period_cycles[i] != period_cycles)) {
0252             /*
0253              * Allow channel to reconfigure period if no other
0254              * channels being configured.
0255              */
0256             if (i == pwm->hwpwm)
0257                 continue;
0258
0259             dev_err(chip->dev,
0260                 "period value conflicts with channel %u\n",
0261                 i);
0262             return -EINVAL;
0263         }
0264     }
0265
0266     pc->period_cycles[pwm->hwpwm] = period_cycles;
0267
0268     /* Configure clock prescaler to support Low frequency PWM wave */
0269     if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval,
0270                  &tb_divval)) {
0271         dev_err(chip->dev, "Unsupported values\n");
0272         return -EINVAL;
0273     }
0274
0275     pm_runtime_get_sync(chip->dev);
0276
0277     /* Update clock prescaler values */
0278     ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);
0279
0280     /* Update period & duty cycle with presacler division */
0281     period_cycles = period_cycles / ps_divval;
0282     duty_cycles = duty_cycles / ps_divval;
0283
0284     /* Configure shadow loading on Period register */
0285     ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);
0286
0287     ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);
0288
0289     /* Configure ehrpwm counter for up-count mode */
0290     ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
0291               TBCTL_CTRMODE_UP);
0292
0293     if (pwm->hwpwm == 1)
0294         /* Channel 1 configured with compare B register */
0295         cmp_reg = CMPB;
0296     else
0297         /* Channel 0 configured with compare A register */
0298         cmp_reg = CMPA;
0299
0300     ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
0301
0302     pm_runtime_put_sync(chip->dev);
0303
0304     return 0;
0305 }
0306
0307 static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip,
0308                    struct pwm_device *pwm,
0309                    enum pwm_polarity polarity)
0310 {
0311     struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
0312
0313     /* Configuration of polarity in hardware delayed, do at enable */
0314     pc->polarity[pwm->hwpwm] = polarity;
0315
0316     return 0;
0317 }
0318
0319 static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
0320 {
0321     struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
0322     u16 aqcsfrc_val, aqcsfrc_mask;
0323     int ret;
0324
0325     /* Leave clock enabled on enabling PWM */
0326     pm_runtime_get_sync(chip->dev);
0327
0328     /* Disabling Action Qualifier on PWM output */
0329     if (pwm->hwpwm) {
0330         aqcsfrc_val = AQCSFRC_CSFB_FRCDIS;
0331         aqcsfrc_mask = AQCSFRC_CSFB_MASK;
0332     } else {
0333         aqcsfrc_val = AQCSFRC_CSFA_FRCDIS;
0334         aqcsfrc_mask = AQCSFRC_CSFA_MASK;
0335     }
0336
0337     /* Changes to shadow mode */
0338     ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
0339               AQSFRC_RLDCSF_ZRO);
0340
0341     ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
0342
0343     /* Channels polarity can be configured from action qualifier module */
0344     configure_polarity(pc, pwm->hwpwm);
0345
0346     /* Enable TBCLK */
0347     ret = clk_enable(pc->tbclk);
0348     if (ret) {
0349         dev_err(chip->dev, "Failed to enable TBCLK for %s: %d\n",
0350             dev_name(pc->chip.dev), ret);
0351         return ret;
0352     }
0353
0354     return 0;
0355 }
0356
0357 static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
0358 {
0359     struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
0360     u16 aqcsfrc_val, aqcsfrc_mask;
0361
0362     /* Action Qualifier puts PWM output low forcefully */
0363     if (pwm->hwpwm) {
0364         aqcsfrc_val = AQCSFRC_CSFB_FRCLOW;
0365         aqcsfrc_mask = AQCSFRC_CSFB_MASK;
0366     } else {
0367         aqcsfrc_val = AQCSFRC_CSFA_FRCLOW;
0368         aqcsfrc_mask = AQCSFRC_CSFA_MASK;
0369     }
0370
0371     /* Update shadow register first before modifying active register */
0372     ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
0373               AQSFRC_RLDCSF_ZRO);
0374     ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
0375     /*
0376      * Changes to immediate action on Action Qualifier. This puts
0377      * Action Qualifier control on PWM output from next TBCLK
0378      */
0379     ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
0380               AQSFRC_RLDCSF_IMDT);
0381
0382     ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
0383
0384     /* Disabling TBCLK on PWM disable */
0385     clk_disable(pc->tbclk);
0386
0387     /* Disable clock on PWM disable */
0388     pm_runtime_put_sync(chip->dev);
0389 }
0390
0391 static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
0392 {
0393     struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
0394
0395     if (pwm_is_enabled(pwm)) {
0396         dev_warn(chip->dev, "Removing PWM device without disabling\n");
0397         pm_runtime_put_sync(chip->dev);
0398     }
0399
0400     /* set period value to zero on free */
0401     pc->period_cycles[pwm->hwpwm] = 0;
0402 }
0403
0404 static int ehrpwm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0405                 const struct pwm_state *state)
0406 {
0407     int err;
0408     bool enabled = pwm->state.enabled;
0409
0410     if (state->polarity != pwm->state.polarity) {
0411         if (enabled) {
0412             ehrpwm_pwm_disable(chip, pwm);
0413             enabled = false;
0414         }
0415
0416         err = ehrpwm_pwm_set_polarity(chip, pwm, state->polarity);
0417         if (err)
0418             return err;
0419     }
0420
0421     if (!state->enabled) {
0422         if (enabled)
0423             ehrpwm_pwm_disable(chip, pwm);
0424         return 0;
0425     }
0426
0427     err = ehrpwm_pwm_config(chip, pwm, state->duty_cycle, state->period);
0428     if (err)
0429         return err;
0430
0431     if (!enabled)
0432         err = ehrpwm_pwm_enable(chip, pwm);
0433
0434     return err;
0435 }
0436
0437 static const struct pwm_ops ehrpwm_pwm_ops = {
0438     .free = ehrpwm_pwm_free,
0439     .apply = ehrpwm_pwm_apply,
0440     .owner = THIS_MODULE,
0441 };
0442
0443 static const struct of_device_id ehrpwm_of_match[] = {
0444     { .compatible = "ti,am3352-ehrpwm" },
0445     { .compatible = "ti,am33xx-ehrpwm" },
0446     {},
0447 };
0448 MODULE_DEVICE_TABLE(of, ehrpwm_of_match);
0449
0450 static int ehrpwm_pwm_probe(struct platform_device *pdev)
0451 {
0452     struct device_node *np = pdev->dev.of_node;
0453     struct ehrpwm_pwm_chip *pc;
0454     struct clk *clk;
0455     int ret;
0456
0457     pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
0458     if (!pc)
0459         return -ENOMEM;
0460
0461     clk = devm_clk_get(&pdev->dev, "fck");
0462     if (IS_ERR(clk)) {
0463         if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
0464             dev_warn(&pdev->dev, "Binding is obsolete.\n");
0465             clk = devm_clk_get(pdev->dev.parent, "fck");
0466         }
0467     }
0468
0469     if (IS_ERR(clk))
0470         return dev_err_probe(&pdev->dev, PTR_ERR(clk), "Failed to get fck\n");
0471
0472     pc->clk_rate = clk_get_rate(clk);
0473     if (!pc->clk_rate) {
0474         dev_err(&pdev->dev, "failed to get clock rate\n");
0475         return -EINVAL;
0476     }
0477
0478     pc->chip.dev = &pdev->dev;
0479     pc->chip.ops = &ehrpwm_pwm_ops;
0480     pc->chip.npwm = NUM_PWM_CHANNEL;
0481
0482     pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);
0483     if (IS_ERR(pc->mmio_base))
0484         return PTR_ERR(pc->mmio_base);
0485
0486     /* Acquire tbclk for Time Base EHRPWM submodule */
0487     pc->tbclk = devm_clk_get(&pdev->dev, "tbclk");
0488     if (IS_ERR(pc->tbclk))
0489         return dev_err_probe(&pdev->dev, PTR_ERR(pc->tbclk), "Failed to get tbclk\n");
0490
0491     ret = clk_prepare(pc->tbclk);
0492     if (ret < 0) {
0493         dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret);
0494         return ret;
0495     }
0496
0497     ret = pwmchip_add(&pc->chip);
0498     if (ret < 0) {
0499         dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
0500         goto err_clk_unprepare;
0501     }
0502
0503     platform_set_drvdata(pdev, pc);
0504     pm_runtime_enable(&pdev->dev);
0505
0506     return 0;
0507
0508 err_clk_unprepare:
0509     clk_unprepare(pc->tbclk);
0510
0511     return ret;
0512 }
0513
0514 static int ehrpwm_pwm_remove(struct platform_device *pdev)
0515 {
0516     struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev);
0517
0518     pwmchip_remove(&pc->chip);
0519
0520     clk_unprepare(pc->tbclk);
0521
0522     pm_runtime_disable(&pdev->dev);
0523
0524     return 0;
0525 }
0526
0527 #ifdef CONFIG_PM_SLEEP
0528 static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc)
0529 {
0530     pm_runtime_get_sync(pc->chip.dev);
0531
0532     pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL);
0533     pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD);
0534     pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA);
0535     pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB);
0536     pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA);
0537     pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB);
0538     pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC);
0539     pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC);
0540
0541     pm_runtime_put_sync(pc->chip.dev);
0542 }
0543
0544 static void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc)
0545 {
0546     ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd);
0547     ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa);
0548     ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb);
0549     ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla);
0550     ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb);
0551     ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc);
0552     ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc);
0553     ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl);
0554 }
0555
0556 static int ehrpwm_pwm_suspend(struct device *dev)
0557 {
0558     struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
0559     unsigned int i;
0560
0561     ehrpwm_pwm_save_context(pc);
0562
0563     for (i = 0; i < pc->chip.npwm; i++) {
0564         struct pwm_device *pwm = &pc->chip.pwms[i];
0565
0566         if (!pwm_is_enabled(pwm))
0567             continue;
0568
0569         /* Disable explicitly if PWM is running */
0570         pm_runtime_put_sync(dev);
0571     }
0572
0573     return 0;
0574 }
0575
0576 static int ehrpwm_pwm_resume(struct device *dev)
0577 {
0578     struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
0579     unsigned int i;
0580
0581     for (i = 0; i < pc->chip.npwm; i++) {
0582         struct pwm_device *pwm = &pc->chip.pwms[i];
0583
0584         if (!pwm_is_enabled(pwm))
0585             continue;
0586
0587         /* Enable explicitly if PWM was running */
0588         pm_runtime_get_sync(dev);
0589     }
0590
0591     ehrpwm_pwm_restore_context(pc);
0592
0593     return 0;
0594 }
0595 #endif
0596
0597 static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend,
0598              ehrpwm_pwm_resume);
0599
0600 static struct platform_driver ehrpwm_pwm_driver = {
0601     .driver = {
0602         .name = "ehrpwm",
0603         .of_match_table = ehrpwm_of_match,
0604         .pm = &ehrpwm_pwm_pm_ops,
0605     },
0606     .probe = ehrpwm_pwm_probe,
0607     .remove = ehrpwm_pwm_remove,
0608 };
0609 module_platform_driver(ehrpwm_pwm_driver);
0610
0611 MODULE_DESCRIPTION("EHRPWM PWM driver");
0612 MODULE_AUTHOR("Texas Instruments");
0613 MODULE_LICENSE("GPL");