drivers/pwm/pwm-tegra.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * drivers/pwm/pwm-tegra.c
0004  *
0005  * Tegra pulse-width-modulation controller driver
0006  *
0007  * Copyright (c) 2010-2020, NVIDIA Corporation.
0008  * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
0009  *
0010  * Overview of Tegra Pulse Width Modulator Register:
0011  * 1. 13-bit: Frequency division (SCALE)
0012  * 2. 8-bit : Pulse division (DUTY)
0013  * 3. 1-bit : Enable bit
0014  *
0015  * The PWM clock frequency is divided by 256 before subdividing it based
0016  * on the programmable frequency division value to generate the required
0017  * frequency for PWM output. The maximum output frequency that can be
0018  * achieved is (max rate of source clock) / 256.
0019  * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
0020  * 408 MHz/256 = 1.6 MHz.
0021  * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
0022  *
0023  * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
0024  * To achieve 100% duty cycle, program Bit [24] of this register to
0025  * 1’b1. In which case the other bits [23:16] are set to don't care.
0026  *
0027  * Limitations:
0028  * -    When PWM is disabled, the output is driven to inactive.
0029  * -    It does not allow the current PWM period to complete and
0030  *  stops abruptly.
0031  *
0032  * -    If the register is reconfigured while PWM is running,
0033  *  it does not complete the currently running period.
0034  *
0035  * -    If the user input duty is beyond acceptible limits,
0036  *  -EINVAL is returned.
0037  */
0038
0039 #include <linux/clk.h>
0040 #include <linux/err.h>
0041 #include <linux/io.h>
0042 #include <linux/module.h>
0043 #include <linux/of.h>
0044 #include <linux/of_device.h>
0045 #include <linux/pm_opp.h>
0046 #include <linux/pwm.h>
0047 #include <linux/platform_device.h>
0048 #include <linux/pinctrl/consumer.h>
0049 #include <linux/pm_runtime.h>
0050 #include <linux/slab.h>
0051 #include <linux/reset.h>
0052
0053 #include <soc/tegra/common.h>
0054
0055 #define PWM_ENABLE  (1 << 31)
0056 #define PWM_DUTY_WIDTH  8
0057 #define PWM_DUTY_SHIFT  16
0058 #define PWM_SCALE_WIDTH 13
0059 #define PWM_SCALE_SHIFT 0
0060
0061 struct tegra_pwm_soc {
0062     unsigned int num_channels;
0063
0064     /* Maximum IP frequency for given SoCs */
0065     unsigned long max_frequency;
0066 };
0067
0068 struct tegra_pwm_chip {
0069     struct pwm_chip chip;
0070     struct device *dev;
0071
0072     struct clk *clk;
0073     struct reset_control*rst;
0074
0075     unsigned long clk_rate;
0076     unsigned long min_period_ns;
0077
0078     void __iomem *regs;
0079
0080     const struct tegra_pwm_soc *soc;
0081 };
0082
0083 static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
0084 {
0085     return container_of(chip, struct tegra_pwm_chip, chip);
0086 }
0087
0088 static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)
0089 {
0090     return readl(pc->regs + (offset << 4));
0091 }
0092
0093 static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)
0094 {
0095     writel(value, pc->regs + (offset << 4));
0096 }
0097
0098 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
0099                 int duty_ns, int period_ns)
0100 {
0101     struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
0102     unsigned long long c = duty_ns;
0103     unsigned long rate, required_clk_rate;
0104     u32 val = 0;
0105     int err;
0106
0107     /*
0108      * Convert from duty_ns / period_ns to a fixed number of duty ticks
0109      * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
0110      * nearest integer during division.
0111      */
0112     c *= (1 << PWM_DUTY_WIDTH);
0113     c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
0114
0115     val = (u32)c << PWM_DUTY_SHIFT;
0116
0117     /*
0118      *  min period = max clock limit >> PWM_DUTY_WIDTH
0119      */
0120     if (period_ns < pc->min_period_ns)
0121         return -EINVAL;
0122
0123     /*
0124      * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
0125      * cycles at the PWM clock rate will take period_ns nanoseconds.
0126      *
0127      * num_channels: If single instance of PWM controller has multiple
0128      * channels (e.g. Tegra210 or older) then it is not possible to
0129      * configure separate clock rates to each of the channels, in such
0130      * case the value stored during probe will be referred.
0131      *
0132      * If every PWM controller instance has one channel respectively, i.e.
0133      * nums_channels == 1 then only the clock rate can be modified
0134      * dynamically (e.g. Tegra186 or Tegra194).
0135      */
0136     if (pc->soc->num_channels == 1) {
0137         /*
0138          * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
0139          * with the maximum possible rate that the controller can
0140          * provide. Any further lower value can be derived by setting
0141          * PFM bits[0:12].
0142          *
0143          * required_clk_rate is a reference rate for source clock and
0144          * it is derived based on user requested period. By setting the
0145          * source clock rate as required_clk_rate, PWM controller will
0146          * be able to configure the requested period.
0147          */
0148         required_clk_rate =
0149             (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
0150
0151         err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
0152         if (err < 0)
0153             return -EINVAL;
0154
0155         /* Store the new rate for further references */
0156         pc->clk_rate = clk_get_rate(pc->clk);
0157     }
0158
0159     /* Consider precision in PWM_SCALE_WIDTH rate calculation */
0160     rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,
0161                    (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH);
0162
0163     /*
0164      * Since the actual PWM divider is the register's frequency divider
0165      * field plus 1, we need to decrement to get the correct value to
0166      * write to the register.
0167      */
0168     if (rate > 0)
0169         rate--;
0170     else
0171         return -EINVAL;
0172
0173     /*
0174      * Make sure that the rate will fit in the register's frequency
0175      * divider field.
0176      */
0177     if (rate >> PWM_SCALE_WIDTH)
0178         return -EINVAL;
0179
0180     val |= rate << PWM_SCALE_SHIFT;
0181
0182     /*
0183      * If the PWM channel is disabled, make sure to turn on the clock
0184      * before writing the register. Otherwise, keep it enabled.
0185      */
0186     if (!pwm_is_enabled(pwm)) {
0187         err = pm_runtime_resume_and_get(pc->dev);
0188         if (err)
0189             return err;
0190     } else
0191         val |= PWM_ENABLE;
0192
0193     pwm_writel(pc, pwm->hwpwm, val);
0194
0195     /*
0196      * If the PWM is not enabled, turn the clock off again to save power.
0197      */
0198     if (!pwm_is_enabled(pwm))
0199         pm_runtime_put(pc->dev);
0200
0201     return 0;
0202 }
0203
0204 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
0205 {
0206     struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
0207     int rc = 0;
0208     u32 val;
0209
0210     rc = pm_runtime_resume_and_get(pc->dev);
0211     if (rc)
0212         return rc;
0213
0214     val = pwm_readl(pc, pwm->hwpwm);
0215     val |= PWM_ENABLE;
0216     pwm_writel(pc, pwm->hwpwm, val);
0217
0218     return 0;
0219 }
0220
0221 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
0222 {
0223     struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
0224     u32 val;
0225
0226     val = pwm_readl(pc, pwm->hwpwm);
0227     val &= ~PWM_ENABLE;
0228     pwm_writel(pc, pwm->hwpwm, val);
0229
0230     pm_runtime_put_sync(pc->dev);
0231 }
0232
0233 static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0234                const struct pwm_state *state)
0235 {
0236     int err;
0237     bool enabled = pwm->state.enabled;
0238
0239     if (state->polarity != PWM_POLARITY_NORMAL)
0240         return -EINVAL;
0241
0242     if (!state->enabled) {
0243         if (enabled)
0244             tegra_pwm_disable(chip, pwm);
0245
0246         return 0;
0247     }
0248
0249     err = tegra_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
0250     if (err)
0251         return err;
0252
0253     if (!enabled)
0254         err = tegra_pwm_enable(chip, pwm);
0255
0256     return err;
0257 }
0258
0259 static const struct pwm_ops tegra_pwm_ops = {
0260     .apply = tegra_pwm_apply,
0261     .owner = THIS_MODULE,
0262 };
0263
0264 static int tegra_pwm_probe(struct platform_device *pdev)
0265 {
0266     struct tegra_pwm_chip *pc;
0267     int ret;
0268
0269     pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
0270     if (!pc)
0271         return -ENOMEM;
0272
0273     pc->soc = of_device_get_match_data(&pdev->dev);
0274     pc->dev = &pdev->dev;
0275
0276     pc->regs = devm_platform_ioremap_resource(pdev, 0);
0277     if (IS_ERR(pc->regs))
0278         return PTR_ERR(pc->regs);
0279
0280     platform_set_drvdata(pdev, pc);
0281
0282     pc->clk = devm_clk_get(&pdev->dev, NULL);
0283     if (IS_ERR(pc->clk))
0284         return PTR_ERR(pc->clk);
0285
0286     ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
0287     if (ret)
0288         return ret;
0289
0290     pm_runtime_enable(&pdev->dev);
0291     ret = pm_runtime_resume_and_get(&pdev->dev);
0292     if (ret)
0293         return ret;
0294
0295     /* Set maximum frequency of the IP */
0296     ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency);
0297     if (ret < 0) {
0298         dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
0299         goto put_pm;
0300     }
0301
0302     /*
0303      * The requested and configured frequency may differ due to
0304      * clock register resolutions. Get the configured frequency
0305      * so that PWM period can be calculated more accurately.
0306      */
0307     pc->clk_rate = clk_get_rate(pc->clk);
0308
0309     /* Set minimum limit of PWM period for the IP */
0310     pc->min_period_ns =
0311         (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
0312
0313     pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
0314     if (IS_ERR(pc->rst)) {
0315         ret = PTR_ERR(pc->rst);
0316         dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
0317         goto put_pm;
0318     }
0319
0320     reset_control_deassert(pc->rst);
0321
0322     pc->chip.dev = &pdev->dev;
0323     pc->chip.ops = &tegra_pwm_ops;
0324     pc->chip.npwm = pc->soc->num_channels;
0325
0326     ret = pwmchip_add(&pc->chip);
0327     if (ret < 0) {
0328         dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
0329         reset_control_assert(pc->rst);
0330         goto put_pm;
0331     }
0332
0333     pm_runtime_put(&pdev->dev);
0334
0335     return 0;
0336 put_pm:
0337     pm_runtime_put_sync_suspend(&pdev->dev);
0338     pm_runtime_force_suspend(&pdev->dev);
0339     return ret;
0340 }
0341
0342 static int tegra_pwm_remove(struct platform_device *pdev)
0343 {
0344     struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
0345
0346     pwmchip_remove(&pc->chip);
0347
0348     reset_control_assert(pc->rst);
0349
0350     pm_runtime_force_suspend(&pdev->dev);
0351
0352     return 0;
0353 }
0354
0355 static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev)
0356 {
0357     struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
0358     int err;
0359
0360     clk_disable_unprepare(pc->clk);
0361
0362     err = pinctrl_pm_select_sleep_state(dev);
0363     if (err) {
0364         clk_prepare_enable(pc->clk);
0365         return err;
0366     }
0367
0368     return 0;
0369 }
0370
0371 static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
0372 {
0373     struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
0374     int err;
0375
0376     err = pinctrl_pm_select_default_state(dev);
0377     if (err)
0378         return err;
0379
0380     err = clk_prepare_enable(pc->clk);
0381     if (err) {
0382         pinctrl_pm_select_sleep_state(dev);
0383         return err;
0384     }
0385
0386     return 0;
0387 }
0388
0389 static const struct tegra_pwm_soc tegra20_pwm_soc = {
0390     .num_channels = 4,
0391     .max_frequency = 48000000UL,
0392 };
0393
0394 static const struct tegra_pwm_soc tegra186_pwm_soc = {
0395     .num_channels = 1,
0396     .max_frequency = 102000000UL,
0397 };
0398
0399 static const struct tegra_pwm_soc tegra194_pwm_soc = {
0400     .num_channels = 1,
0401     .max_frequency = 408000000UL,
0402 };
0403
0404 static const struct of_device_id tegra_pwm_of_match[] = {
0405     { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
0406     { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
0407     { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
0408     { }
0409 };
0410 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
0411
0412 static const struct dev_pm_ops tegra_pwm_pm_ops = {
0413     SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume,
0414                NULL)
0415     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0416                 pm_runtime_force_resume)
0417 };
0418
0419 static struct platform_driver tegra_pwm_driver = {
0420     .driver = {
0421         .name = "tegra-pwm",
0422         .of_match_table = tegra_pwm_of_match,
0423         .pm = &tegra_pwm_pm_ops,
0424     },
0425     .probe = tegra_pwm_probe,
0426     .remove = tegra_pwm_remove,
0427 };
0428
0429 module_platform_driver(tegra_pwm_driver);
0430
0431 MODULE_LICENSE("GPL");
0432 MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
0433 MODULE_DESCRIPTION("Tegra PWM controller driver");
0434 MODULE_ALIAS("platform:tegra-pwm");