drivers/pwm/pwm-sun4i.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for Allwinner sun4i Pulse Width Modulation Controller
0004  *
0005  * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
0006  *
0007  * Limitations:
0008  * - When outputing the source clock directly, the PWM logic will be bypassed
0009  *   and the currently running period is not guaranteed to be completed
0010  */
0011
0012 #include <linux/bitops.h>
0013 #include <linux/clk.h>
0014 #include <linux/delay.h>
0015 #include <linux/err.h>
0016 #include <linux/io.h>
0017 #include <linux/jiffies.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/of_device.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pwm.h>
0023 #include <linux/reset.h>
0024 #include <linux/slab.h>
0025 #include <linux/spinlock.h>
0026 #include <linux/time.h>
0027
0028 #define PWM_CTRL_REG        0x0
0029
0030 #define PWM_CH_PRD_BASE     0x4
0031 #define PWM_CH_PRD_OFFSET   0x4
0032 #define PWM_CH_PRD(ch)      (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
0033
0034 #define PWMCH_OFFSET        15
0035 #define PWM_PRESCAL_MASK    GENMASK(3, 0)
0036 #define PWM_PRESCAL_OFF     0
0037 #define PWM_EN          BIT(4)
0038 #define PWM_ACT_STATE       BIT(5)
0039 #define PWM_CLK_GATING      BIT(6)
0040 #define PWM_MODE        BIT(7)
0041 #define PWM_PULSE       BIT(8)
0042 #define PWM_BYPASS      BIT(9)
0043
0044 #define PWM_RDY_BASE        28
0045 #define PWM_RDY_OFFSET      1
0046 #define PWM_RDY(ch)     BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
0047
0048 #define PWM_PRD(prd)        (((prd) - 1) << 16)
0049 #define PWM_PRD_MASK        GENMASK(15, 0)
0050
0051 #define PWM_DTY_MASK        GENMASK(15, 0)
0052
0053 #define PWM_REG_PRD(reg)    ((((reg) >> 16) & PWM_PRD_MASK) + 1)
0054 #define PWM_REG_DTY(reg)    ((reg) & PWM_DTY_MASK)
0055 #define PWM_REG_PRESCAL(reg, chan)  (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
0056
0057 #define BIT_CH(bit, chan)   ((bit) << ((chan) * PWMCH_OFFSET))
0058
0059 static const u32 prescaler_table[] = {
0060     120,
0061     180,
0062     240,
0063     360,
0064     480,
0065     0,
0066     0,
0067     0,
0068     12000,
0069     24000,
0070     36000,
0071     48000,
0072     72000,
0073     0,
0074     0,
0075     0, /* Actually 1 but tested separately */
0076 };
0077
0078 struct sun4i_pwm_data {
0079     bool has_prescaler_bypass;
0080     bool has_direct_mod_clk_output;
0081     unsigned int npwm;
0082 };
0083
0084 struct sun4i_pwm_chip {
0085     struct pwm_chip chip;
0086     struct clk *bus_clk;
0087     struct clk *clk;
0088     struct reset_control *rst;
0089     void __iomem *base;
0090     spinlock_t ctrl_lock;
0091     const struct sun4i_pwm_data *data;
0092 };
0093
0094 static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
0095 {
0096     return container_of(chip, struct sun4i_pwm_chip, chip);
0097 }
0098
0099 static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
0100                   unsigned long offset)
0101 {
0102     return readl(chip->base + offset);
0103 }
0104
0105 static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
0106                     u32 val, unsigned long offset)
0107 {
0108     writel(val, chip->base + offset);
0109 }
0110
0111 static void sun4i_pwm_get_state(struct pwm_chip *chip,
0112                 struct pwm_device *pwm,
0113                 struct pwm_state *state)
0114 {
0115     struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
0116     u64 clk_rate, tmp;
0117     u32 val;
0118     unsigned int prescaler;
0119
0120     clk_rate = clk_get_rate(sun4i_pwm->clk);
0121
0122     val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
0123
0124     /*
0125      * PWM chapter in H6 manual has a diagram which explains that if bypass
0126      * bit is set, no other setting has any meaning. Even more, experiment
0127      * proved that also enable bit is ignored in this case.
0128      */
0129     if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
0130         sun4i_pwm->data->has_direct_mod_clk_output) {
0131         state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
0132         state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
0133         state->polarity = PWM_POLARITY_NORMAL;
0134         state->enabled = true;
0135         return;
0136     }
0137
0138     if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
0139         sun4i_pwm->data->has_prescaler_bypass)
0140         prescaler = 1;
0141     else
0142         prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
0143
0144     if (prescaler == 0)
0145         return;
0146
0147     if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
0148         state->polarity = PWM_POLARITY_NORMAL;
0149     else
0150         state->polarity = PWM_POLARITY_INVERSED;
0151
0152     if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
0153         BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
0154         state->enabled = true;
0155     else
0156         state->enabled = false;
0157
0158     val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
0159
0160     tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
0161     state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
0162
0163     tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
0164     state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
0165 }
0166
0167 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
0168                    const struct pwm_state *state,
0169                    u32 *dty, u32 *prd, unsigned int *prsclr,
0170                    bool *bypass)
0171 {
0172     u64 clk_rate, div = 0;
0173     unsigned int prescaler = 0;
0174
0175     clk_rate = clk_get_rate(sun4i_pwm->clk);
0176
0177     *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
0178           state->enabled &&
0179           (state->period * clk_rate >= NSEC_PER_SEC) &&
0180           (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
0181           (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
0182
0183     /* Skip calculation of other parameters if we bypass them */
0184     if (*bypass)
0185         return 0;
0186
0187     if (sun4i_pwm->data->has_prescaler_bypass) {
0188         /* First, test without any prescaler when available */
0189         prescaler = PWM_PRESCAL_MASK;
0190         /*
0191          * When not using any prescaler, the clock period in nanoseconds
0192          * is not an integer so round it half up instead of
0193          * truncating to get less surprising values.
0194          */
0195         div = clk_rate * state->period + NSEC_PER_SEC / 2;
0196         do_div(div, NSEC_PER_SEC);
0197         if (div - 1 > PWM_PRD_MASK)
0198             prescaler = 0;
0199     }
0200
0201     if (prescaler == 0) {
0202         /* Go up from the first divider */
0203         for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
0204             unsigned int pval = prescaler_table[prescaler];
0205
0206             if (!pval)
0207                 continue;
0208
0209             div = clk_rate;
0210             do_div(div, pval);
0211             div = div * state->period;
0212             do_div(div, NSEC_PER_SEC);
0213             if (div - 1 <= PWM_PRD_MASK)
0214                 break;
0215         }
0216
0217         if (div - 1 > PWM_PRD_MASK)
0218             return -EINVAL;
0219     }
0220
0221     *prd = div;
0222     div *= state->duty_cycle;
0223     do_div(div, state->period);
0224     *dty = div;
0225     *prsclr = prescaler;
0226
0227     return 0;
0228 }
0229
0230 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0231                const struct pwm_state *state)
0232 {
0233     struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
0234     struct pwm_state cstate;
0235     u32 ctrl, duty = 0, period = 0, val;
0236     int ret;
0237     unsigned int delay_us, prescaler = 0;
0238     bool bypass;
0239
0240     pwm_get_state(pwm, &cstate);
0241
0242     if (!cstate.enabled) {
0243         ret = clk_prepare_enable(sun4i_pwm->clk);
0244         if (ret) {
0245             dev_err(chip->dev, "failed to enable PWM clock\n");
0246             return ret;
0247         }
0248     }
0249
0250     ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
0251                   &bypass);
0252     if (ret) {
0253         dev_err(chip->dev, "period exceeds the maximum value\n");
0254         if (!cstate.enabled)
0255             clk_disable_unprepare(sun4i_pwm->clk);
0256         return ret;
0257     }
0258
0259     spin_lock(&sun4i_pwm->ctrl_lock);
0260     ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
0261
0262     if (sun4i_pwm->data->has_direct_mod_clk_output) {
0263         if (bypass) {
0264             ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
0265             /* We can skip other parameter */
0266             sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
0267             spin_unlock(&sun4i_pwm->ctrl_lock);
0268             return 0;
0269         }
0270
0271         ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
0272     }
0273
0274     if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
0275         /* Prescaler changed, the clock has to be gated */
0276         ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
0277         sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
0278
0279         ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
0280         ctrl |= BIT_CH(prescaler, pwm->hwpwm);
0281     }
0282
0283     val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
0284     sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
0285
0286     if (state->polarity != PWM_POLARITY_NORMAL)
0287         ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
0288     else
0289         ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
0290
0291     ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
0292
0293     if (state->enabled)
0294         ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
0295
0296     sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
0297
0298     spin_unlock(&sun4i_pwm->ctrl_lock);
0299
0300     if (state->enabled)
0301         return 0;
0302
0303     /* We need a full period to elapse before disabling the channel. */
0304     delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);
0305     if ((delay_us / 500) > MAX_UDELAY_MS)
0306         msleep(delay_us / 1000 + 1);
0307     else
0308         usleep_range(delay_us, delay_us * 2);
0309
0310     spin_lock(&sun4i_pwm->ctrl_lock);
0311     ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
0312     ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
0313     ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
0314     sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
0315     spin_unlock(&sun4i_pwm->ctrl_lock);
0316
0317     clk_disable_unprepare(sun4i_pwm->clk);
0318
0319     return 0;
0320 }
0321
0322 static const struct pwm_ops sun4i_pwm_ops = {
0323     .apply = sun4i_pwm_apply,
0324     .get_state = sun4i_pwm_get_state,
0325     .owner = THIS_MODULE,
0326 };
0327
0328 static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
0329     .has_prescaler_bypass = false,
0330     .npwm = 2,
0331 };
0332
0333 static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
0334     .has_prescaler_bypass = true,
0335     .npwm = 2,
0336 };
0337
0338 static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
0339     .has_prescaler_bypass = true,
0340     .npwm = 1,
0341 };
0342
0343 static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
0344     .has_prescaler_bypass = true,
0345     .has_direct_mod_clk_output = true,
0346     .npwm = 1,
0347 };
0348
0349 static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
0350     .has_prescaler_bypass = true,
0351     .has_direct_mod_clk_output = true,
0352     .npwm = 2,
0353 };
0354
0355 static const struct of_device_id sun4i_pwm_dt_ids[] = {
0356     {
0357         .compatible = "allwinner,sun4i-a10-pwm",
0358         .data = &sun4i_pwm_dual_nobypass,
0359     }, {
0360         .compatible = "allwinner,sun5i-a10s-pwm",
0361         .data = &sun4i_pwm_dual_bypass,
0362     }, {
0363         .compatible = "allwinner,sun5i-a13-pwm",
0364         .data = &sun4i_pwm_single_bypass,
0365     }, {
0366         .compatible = "allwinner,sun7i-a20-pwm",
0367         .data = &sun4i_pwm_dual_bypass,
0368     }, {
0369         .compatible = "allwinner,sun8i-h3-pwm",
0370         .data = &sun4i_pwm_single_bypass,
0371     }, {
0372         .compatible = "allwinner,sun50i-a64-pwm",
0373         .data = &sun50i_a64_pwm_data,
0374     }, {
0375         .compatible = "allwinner,sun50i-h6-pwm",
0376         .data = &sun50i_h6_pwm_data,
0377     }, {
0378         /* sentinel */
0379     },
0380 };
0381 MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
0382
0383 static int sun4i_pwm_probe(struct platform_device *pdev)
0384 {
0385     struct sun4i_pwm_chip *sun4ichip;
0386     int ret;
0387
0388     sun4ichip = devm_kzalloc(&pdev->dev, sizeof(*sun4ichip), GFP_KERNEL);
0389     if (!sun4ichip)
0390         return -ENOMEM;
0391
0392     sun4ichip->data = of_device_get_match_data(&pdev->dev);
0393     if (!sun4ichip->data)
0394         return -ENODEV;
0395
0396     sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);
0397     if (IS_ERR(sun4ichip->base))
0398         return PTR_ERR(sun4ichip->base);
0399
0400     /*
0401      * All hardware variants need a source clock that is divided and
0402      * then feeds the counter that defines the output wave form. In the
0403      * device tree this clock is either unnamed or called "mod".
0404      * Some variants (e.g. H6) need another clock to access the
0405      * hardware registers; this is called "bus".
0406      * So we request "mod" first (and ignore the corner case that a
0407      * parent provides a "mod" clock while the right one would be the
0408      * unnamed one of the PWM device) and if this is not found we fall
0409      * back to the first clock of the PWM.
0410      */
0411     sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");
0412     if (IS_ERR(sun4ichip->clk))
0413         return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
0414                      "get mod clock failed\n");
0415
0416     if (!sun4ichip->clk) {
0417         sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);
0418         if (IS_ERR(sun4ichip->clk))
0419             return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
0420                          "get unnamed clock failed\n");
0421     }
0422
0423     sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
0424     if (IS_ERR(sun4ichip->bus_clk))
0425         return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),
0426                      "get bus clock failed\n");
0427
0428     sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
0429     if (IS_ERR(sun4ichip->rst))
0430         return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),
0431                      "get reset failed\n");
0432
0433     /* Deassert reset */
0434     ret = reset_control_deassert(sun4ichip->rst);
0435     if (ret) {
0436         dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
0437             ERR_PTR(ret));
0438         return ret;
0439     }
0440
0441     /*
0442      * We're keeping the bus clock on for the sake of simplicity.
0443      * Actually it only needs to be on for hardware register accesses.
0444      */
0445     ret = clk_prepare_enable(sun4ichip->bus_clk);
0446     if (ret) {
0447         dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
0448             ERR_PTR(ret));
0449         goto err_bus;
0450     }
0451
0452     sun4ichip->chip.dev = &pdev->dev;
0453     sun4ichip->chip.ops = &sun4i_pwm_ops;
0454     sun4ichip->chip.npwm = sun4ichip->data->npwm;
0455
0456     spin_lock_init(&sun4ichip->ctrl_lock);
0457
0458     ret = pwmchip_add(&sun4ichip->chip);
0459     if (ret < 0) {
0460         dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
0461         goto err_pwm_add;
0462     }
0463
0464     platform_set_drvdata(pdev, sun4ichip);
0465
0466     return 0;
0467
0468 err_pwm_add:
0469     clk_disable_unprepare(sun4ichip->bus_clk);
0470 err_bus:
0471     reset_control_assert(sun4ichip->rst);
0472
0473     return ret;
0474 }
0475
0476 static int sun4i_pwm_remove(struct platform_device *pdev)
0477 {
0478     struct sun4i_pwm_chip *sun4ichip = platform_get_drvdata(pdev);
0479
0480     pwmchip_remove(&sun4ichip->chip);
0481
0482     clk_disable_unprepare(sun4ichip->bus_clk);
0483     reset_control_assert(sun4ichip->rst);
0484
0485     return 0;
0486 }
0487
0488 static struct platform_driver sun4i_pwm_driver = {
0489     .driver = {
0490         .name = "sun4i-pwm",
0491         .of_match_table = sun4i_pwm_dt_ids,
0492     },
0493     .probe = sun4i_pwm_probe,
0494     .remove = sun4i_pwm_remove,
0495 };
0496 module_platform_driver(sun4i_pwm_driver);
0497
0498 MODULE_ALIAS("platform:sun4i-pwm");
0499 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
0500 MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
0501 MODULE_LICENSE("GPL v2");