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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics 2016
0004  *
0005  * Author: Gerald Baeza <gerald.baeza@st.com>
0006  *
0007  * Inspired by timer-stm32.c from Maxime Coquelin
0008  *             pwm-atmel.c from Bo Shen
0009  */
0010 
0011 #include <linux/bitfield.h>
0012 #include <linux/mfd/stm32-timers.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/pinctrl/consumer.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pwm.h>
0018 
0019 #define CCMR_CHANNEL_SHIFT 8
0020 #define CCMR_CHANNEL_MASK  0xFF
0021 #define MAX_BREAKINPUT 2
0022 
0023 struct stm32_breakinput {
0024     u32 index;
0025     u32 level;
0026     u32 filter;
0027 };
0028 
0029 struct stm32_pwm {
0030     struct pwm_chip chip;
0031     struct mutex lock; /* protect pwm config/enable */
0032     struct clk *clk;
0033     struct regmap *regmap;
0034     u32 max_arr;
0035     bool have_complementary_output;
0036     struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
0037     unsigned int num_breakinputs;
0038     u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
0039 };
0040 
0041 static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
0042 {
0043     return container_of(chip, struct stm32_pwm, chip);
0044 }
0045 
0046 static u32 active_channels(struct stm32_pwm *dev)
0047 {
0048     u32 ccer;
0049 
0050     regmap_read(dev->regmap, TIM_CCER, &ccer);
0051 
0052     return ccer & TIM_CCER_CCXE;
0053 }
0054 
0055 static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
0056 {
0057     switch (ch) {
0058     case 0:
0059         return regmap_write(dev->regmap, TIM_CCR1, value);
0060     case 1:
0061         return regmap_write(dev->regmap, TIM_CCR2, value);
0062     case 2:
0063         return regmap_write(dev->regmap, TIM_CCR3, value);
0064     case 3:
0065         return regmap_write(dev->regmap, TIM_CCR4, value);
0066     }
0067     return -EINVAL;
0068 }
0069 
0070 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
0071 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
0072 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
0073 #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
0074 
0075 /*
0076  * Capture using PWM input mode:
0077  *                              ___          ___
0078  * TI[1, 2, 3 or 4]: ........._|   |________|
0079  *                             ^0  ^1       ^2
0080  *                              .   .        .
0081  *                              .   .        XXXXX
0082  *                              .   .   XXXXX     |
0083  *                              .  XXXXX     .    |
0084  *                            XXXXX .        .    |
0085  * COUNTER:        ______XXXXX  .   .        .    |_XXX
0086  *                 start^       .   .        .        ^stop
0087  *                      .       .   .        .
0088  *                      v       v   .        v
0089  *                                  v
0090  * CCR1/CCR3:       tx..........t0...........t2
0091  * CCR2/CCR4:       tx..............t1.........
0092  *
0093  * DMA burst transfer:          |            |
0094  *                              v            v
0095  * DMA buffer:                  { t0, tx }   { t2, t1 }
0096  * DMA done:                                 ^
0097  *
0098  * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
0099  *    + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
0100  * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
0101  * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
0102  *    + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
0103  *
0104  * DMA done, compute:
0105  * - Period     = t2 - t0
0106  * - Duty cycle = t1 - t0
0107  */
0108 static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
0109                  unsigned long tmo_ms, u32 *raw_prd,
0110                  u32 *raw_dty)
0111 {
0112     struct device *parent = priv->chip.dev->parent;
0113     enum stm32_timers_dmas dma_id;
0114     u32 ccen, ccr;
0115     int ret;
0116 
0117     /* Ensure registers have been updated, enable counter and capture */
0118     regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
0119     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
0120 
0121     /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
0122     dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
0123     ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
0124     ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
0125     regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen);
0126 
0127     /*
0128      * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
0129      * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
0130      * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
0131      * or { CCR3, CCR4 }, { CCR3, CCR4 }
0132      */
0133     ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
0134                       2, tmo_ms);
0135     if (ret)
0136         goto stop;
0137 
0138     /* Period: t2 - t0 (take care of counter overflow) */
0139     if (priv->capture[0] <= priv->capture[2])
0140         *raw_prd = priv->capture[2] - priv->capture[0];
0141     else
0142         *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
0143 
0144     /* Duty cycle capture requires at least two capture units */
0145     if (pwm->chip->npwm < 2)
0146         *raw_dty = 0;
0147     else if (priv->capture[0] <= priv->capture[3])
0148         *raw_dty = priv->capture[3] - priv->capture[0];
0149     else
0150         *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
0151 
0152     if (*raw_dty > *raw_prd) {
0153         /*
0154          * Race beetween PWM input and DMA: it may happen
0155          * falling edge triggers new capture on TI2/4 before DMA
0156          * had a chance to read CCR2/4. It means capture[1]
0157          * contains period + duty_cycle. So, subtract period.
0158          */
0159         *raw_dty -= *raw_prd;
0160     }
0161 
0162 stop:
0163     regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0);
0164     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
0165 
0166     return ret;
0167 }
0168 
0169 static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
0170                  struct pwm_capture *result, unsigned long tmo_ms)
0171 {
0172     struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
0173     unsigned long long prd, div, dty;
0174     unsigned long rate;
0175     unsigned int psc = 0, icpsc, scale;
0176     u32 raw_prd = 0, raw_dty = 0;
0177     int ret = 0;
0178 
0179     mutex_lock(&priv->lock);
0180 
0181     if (active_channels(priv)) {
0182         ret = -EBUSY;
0183         goto unlock;
0184     }
0185 
0186     ret = clk_enable(priv->clk);
0187     if (ret) {
0188         dev_err(priv->chip.dev, "failed to enable counter clock\n");
0189         goto unlock;
0190     }
0191 
0192     rate = clk_get_rate(priv->clk);
0193     if (!rate) {
0194         ret = -EINVAL;
0195         goto clk_dis;
0196     }
0197 
0198     /* prescaler: fit timeout window provided by upper layer */
0199     div = (unsigned long long)rate * (unsigned long long)tmo_ms;
0200     do_div(div, MSEC_PER_SEC);
0201     prd = div;
0202     while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
0203         psc++;
0204         div = prd;
0205         do_div(div, psc + 1);
0206     }
0207     regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
0208     regmap_write(priv->regmap, TIM_PSC, psc);
0209 
0210     /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
0211     regmap_update_bits(priv->regmap,
0212                pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
0213                TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
0214                TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
0215                TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
0216 
0217     /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
0218     regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
0219                TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
0220                TIM_CCER_CC2P : TIM_CCER_CC4P);
0221 
0222     ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
0223     if (ret)
0224         goto stop;
0225 
0226     /*
0227      * Got a capture. Try to improve accuracy at high rates:
0228      * - decrease counter clock prescaler, scale up to max rate.
0229      * - use input prescaler, capture once every /2 /4 or /8 edges.
0230      */
0231     if (raw_prd) {
0232         u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
0233 
0234         scale = max_arr / min(max_arr, raw_prd);
0235     } else {
0236         scale = priv->max_arr; /* bellow resolution, use max scale */
0237     }
0238 
0239     if (psc && scale > 1) {
0240         /* 2nd measure with new scale */
0241         psc /= scale;
0242         regmap_write(priv->regmap, TIM_PSC, psc);
0243         ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
0244                         &raw_dty);
0245         if (ret)
0246             goto stop;
0247     }
0248 
0249     /* Compute intermediate period not to exceed timeout at low rates */
0250     prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
0251     do_div(prd, rate);
0252 
0253     for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
0254         /* input prescaler: also keep arbitrary margin */
0255         if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
0256             break;
0257         if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
0258             break;
0259     }
0260 
0261     if (!icpsc)
0262         goto done;
0263 
0264     /* Last chance to improve period accuracy, using input prescaler */
0265     regmap_update_bits(priv->regmap,
0266                pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
0267                TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
0268                FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
0269                FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
0270 
0271     ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
0272     if (ret)
0273         goto stop;
0274 
0275     if (raw_dty >= (raw_prd >> icpsc)) {
0276         /*
0277          * We may fall here using input prescaler, when input
0278          * capture starts on high side (before falling edge).
0279          * Example with icpsc to capture on each 4 events:
0280          *
0281          *       start   1st capture                     2nd capture
0282          *         v     v                               v
0283          *         ___   _____   _____   _____   _____   ____
0284          * TI1..4     |__|    |__|    |__|    |__|    |__|
0285          *            v  v    .  .    .  .    .       v  v
0286          * icpsc1/3:  .  0    .  1    .  2    .  3    .  0
0287          * icpsc2/4:  0       1       2       3       0
0288          *            v  v                            v  v
0289          * CCR1/3  ......t0..............................t2
0290          * CCR2/4  ..t1..............................t1'...
0291          *               .                            .  .
0292          * Capture0:     .<----------------------------->.
0293          * Capture1:     .<-------------------------->.  .
0294          *               .                            .  .
0295          * Period:       .<------>                    .  .
0296          * Low side:                                  .<>.
0297          *
0298          * Result:
0299          * - Period = Capture0 / icpsc
0300          * - Duty = Period - Low side = Period - (Capture0 - Capture1)
0301          */
0302         raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
0303     }
0304 
0305 done:
0306     prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
0307     result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
0308     dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
0309     result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
0310 stop:
0311     regmap_write(priv->regmap, TIM_CCER, 0);
0312     regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
0313     regmap_write(priv->regmap, TIM_PSC, 0);
0314 clk_dis:
0315     clk_disable(priv->clk);
0316 unlock:
0317     mutex_unlock(&priv->lock);
0318 
0319     return ret;
0320 }
0321 
0322 static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
0323                 int duty_ns, int period_ns)
0324 {
0325     unsigned long long prd, div, dty;
0326     unsigned int prescaler = 0;
0327     u32 ccmr, mask, shift;
0328 
0329     /* Period and prescaler values depends on clock rate */
0330     div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
0331 
0332     do_div(div, NSEC_PER_SEC);
0333     prd = div;
0334 
0335     while (div > priv->max_arr) {
0336         prescaler++;
0337         div = prd;
0338         do_div(div, prescaler + 1);
0339     }
0340 
0341     prd = div;
0342 
0343     if (prescaler > MAX_TIM_PSC)
0344         return -EINVAL;
0345 
0346     /*
0347      * All channels share the same prescaler and counter so when two
0348      * channels are active at the same time we can't change them
0349      */
0350     if (active_channels(priv) & ~(1 << ch * 4)) {
0351         u32 psc, arr;
0352 
0353         regmap_read(priv->regmap, TIM_PSC, &psc);
0354         regmap_read(priv->regmap, TIM_ARR, &arr);
0355 
0356         if ((psc != prescaler) || (arr != prd - 1))
0357             return -EBUSY;
0358     }
0359 
0360     regmap_write(priv->regmap, TIM_PSC, prescaler);
0361     regmap_write(priv->regmap, TIM_ARR, prd - 1);
0362     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
0363 
0364     /* Calculate the duty cycles */
0365     dty = prd * duty_ns;
0366     do_div(dty, period_ns);
0367 
0368     write_ccrx(priv, ch, dty);
0369 
0370     /* Configure output mode */
0371     shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
0372     ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
0373     mask = CCMR_CHANNEL_MASK << shift;
0374 
0375     if (ch < 2)
0376         regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
0377     else
0378         regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
0379 
0380     regmap_update_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE, TIM_BDTR_MOE);
0381 
0382     return 0;
0383 }
0384 
0385 static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
0386                   enum pwm_polarity polarity)
0387 {
0388     u32 mask;
0389 
0390     mask = TIM_CCER_CC1P << (ch * 4);
0391     if (priv->have_complementary_output)
0392         mask |= TIM_CCER_CC1NP << (ch * 4);
0393 
0394     regmap_update_bits(priv->regmap, TIM_CCER, mask,
0395                polarity == PWM_POLARITY_NORMAL ? 0 : mask);
0396 
0397     return 0;
0398 }
0399 
0400 static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
0401 {
0402     u32 mask;
0403     int ret;
0404 
0405     ret = clk_enable(priv->clk);
0406     if (ret)
0407         return ret;
0408 
0409     /* Enable channel */
0410     mask = TIM_CCER_CC1E << (ch * 4);
0411     if (priv->have_complementary_output)
0412         mask |= TIM_CCER_CC1NE << (ch * 4);
0413 
0414     regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
0415 
0416     /* Make sure that registers are updated */
0417     regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
0418 
0419     /* Enable controller */
0420     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
0421 
0422     return 0;
0423 }
0424 
0425 static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
0426 {
0427     u32 mask;
0428 
0429     /* Disable channel */
0430     mask = TIM_CCER_CC1E << (ch * 4);
0431     if (priv->have_complementary_output)
0432         mask |= TIM_CCER_CC1NE << (ch * 4);
0433 
0434     regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
0435 
0436     /* When all channels are disabled, we can disable the controller */
0437     if (!active_channels(priv))
0438         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
0439 
0440     clk_disable(priv->clk);
0441 }
0442 
0443 static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0444                const struct pwm_state *state)
0445 {
0446     bool enabled;
0447     struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
0448     int ret;
0449 
0450     enabled = pwm->state.enabled;
0451 
0452     if (enabled && !state->enabled) {
0453         stm32_pwm_disable(priv, pwm->hwpwm);
0454         return 0;
0455     }
0456 
0457     if (state->polarity != pwm->state.polarity)
0458         stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
0459 
0460     ret = stm32_pwm_config(priv, pwm->hwpwm,
0461                    state->duty_cycle, state->period);
0462     if (ret)
0463         return ret;
0464 
0465     if (!enabled && state->enabled)
0466         ret = stm32_pwm_enable(priv, pwm->hwpwm);
0467 
0468     return ret;
0469 }
0470 
0471 static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
0472                   const struct pwm_state *state)
0473 {
0474     struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
0475     int ret;
0476 
0477     /* protect common prescaler for all active channels */
0478     mutex_lock(&priv->lock);
0479     ret = stm32_pwm_apply(chip, pwm, state);
0480     mutex_unlock(&priv->lock);
0481 
0482     return ret;
0483 }
0484 
0485 static const struct pwm_ops stm32pwm_ops = {
0486     .owner = THIS_MODULE,
0487     .apply = stm32_pwm_apply_locked,
0488     .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
0489 };
0490 
0491 static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
0492                     const struct stm32_breakinput *bi)
0493 {
0494     u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
0495     u32 bke = TIM_BDTR_BKE(bi->index);
0496     u32 bkp = TIM_BDTR_BKP(bi->index);
0497     u32 bkf = TIM_BDTR_BKF(bi->index);
0498     u32 mask = bkf | bkp | bke;
0499     u32 bdtr;
0500 
0501     bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
0502 
0503     if (bi->level)
0504         bdtr |= bkp;
0505 
0506     regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
0507 
0508     regmap_read(priv->regmap, TIM_BDTR, &bdtr);
0509 
0510     return (bdtr & bke) ? 0 : -EINVAL;
0511 }
0512 
0513 static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
0514 {
0515     unsigned int i;
0516     int ret;
0517 
0518     for (i = 0; i < priv->num_breakinputs; i++) {
0519         ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
0520         if (ret < 0)
0521             return ret;
0522     }
0523 
0524     return 0;
0525 }
0526 
0527 static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
0528                        struct device_node *np)
0529 {
0530     int nb, ret, array_size;
0531     unsigned int i;
0532 
0533     nb = of_property_count_elems_of_size(np, "st,breakinput",
0534                          sizeof(struct stm32_breakinput));
0535 
0536     /*
0537      * Because "st,breakinput" parameter is optional do not make probe
0538      * failed if it doesn't exist.
0539      */
0540     if (nb <= 0)
0541         return 0;
0542 
0543     if (nb > MAX_BREAKINPUT)
0544         return -EINVAL;
0545 
0546     priv->num_breakinputs = nb;
0547     array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
0548     ret = of_property_read_u32_array(np, "st,breakinput",
0549                      (u32 *)priv->breakinputs, array_size);
0550     if (ret)
0551         return ret;
0552 
0553     for (i = 0; i < priv->num_breakinputs; i++) {
0554         if (priv->breakinputs[i].index > 1 ||
0555             priv->breakinputs[i].level > 1 ||
0556             priv->breakinputs[i].filter > 15)
0557             return -EINVAL;
0558     }
0559 
0560     return stm32_pwm_apply_breakinputs(priv);
0561 }
0562 
0563 static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
0564 {
0565     u32 ccer;
0566 
0567     /*
0568      * If complementary bit doesn't exist writing 1 will have no
0569      * effect so we can detect it.
0570      */
0571     regmap_update_bits(priv->regmap,
0572                TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
0573     regmap_read(priv->regmap, TIM_CCER, &ccer);
0574     regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);
0575 
0576     priv->have_complementary_output = (ccer != 0);
0577 }
0578 
0579 static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
0580 {
0581     u32 ccer;
0582     int npwm = 0;
0583 
0584     /*
0585      * If channels enable bits don't exist writing 1 will have no
0586      * effect so we can detect and count them.
0587      */
0588     regmap_update_bits(priv->regmap,
0589                TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
0590     regmap_read(priv->regmap, TIM_CCER, &ccer);
0591     regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
0592 
0593     if (ccer & TIM_CCER_CC1E)
0594         npwm++;
0595 
0596     if (ccer & TIM_CCER_CC2E)
0597         npwm++;
0598 
0599     if (ccer & TIM_CCER_CC3E)
0600         npwm++;
0601 
0602     if (ccer & TIM_CCER_CC4E)
0603         npwm++;
0604 
0605     return npwm;
0606 }
0607 
0608 static int stm32_pwm_probe(struct platform_device *pdev)
0609 {
0610     struct device *dev = &pdev->dev;
0611     struct device_node *np = dev->of_node;
0612     struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
0613     struct stm32_pwm *priv;
0614     int ret;
0615 
0616     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0617     if (!priv)
0618         return -ENOMEM;
0619 
0620     mutex_init(&priv->lock);
0621     priv->regmap = ddata->regmap;
0622     priv->clk = ddata->clk;
0623     priv->max_arr = ddata->max_arr;
0624 
0625     if (!priv->regmap || !priv->clk)
0626         return -EINVAL;
0627 
0628     ret = stm32_pwm_probe_breakinputs(priv, np);
0629     if (ret)
0630         return ret;
0631 
0632     stm32_pwm_detect_complementary(priv);
0633 
0634     priv->chip.dev = dev;
0635     priv->chip.ops = &stm32pwm_ops;
0636     priv->chip.npwm = stm32_pwm_detect_channels(priv);
0637 
0638     ret = pwmchip_add(&priv->chip);
0639     if (ret < 0)
0640         return ret;
0641 
0642     platform_set_drvdata(pdev, priv);
0643 
0644     return 0;
0645 }
0646 
0647 static int stm32_pwm_remove(struct platform_device *pdev)
0648 {
0649     struct stm32_pwm *priv = platform_get_drvdata(pdev);
0650     unsigned int i;
0651 
0652     for (i = 0; i < priv->chip.npwm; i++)
0653         pwm_disable(&priv->chip.pwms[i]);
0654 
0655     pwmchip_remove(&priv->chip);
0656 
0657     return 0;
0658 }
0659 
0660 static int __maybe_unused stm32_pwm_suspend(struct device *dev)
0661 {
0662     struct stm32_pwm *priv = dev_get_drvdata(dev);
0663     unsigned int i;
0664     u32 ccer, mask;
0665 
0666     /* Look for active channels */
0667     ccer = active_channels(priv);
0668 
0669     for (i = 0; i < priv->chip.npwm; i++) {
0670         mask = TIM_CCER_CC1E << (i * 4);
0671         if (ccer & mask) {
0672             dev_err(dev, "PWM %u still in use by consumer %s\n",
0673                 i, priv->chip.pwms[i].label);
0674             return -EBUSY;
0675         }
0676     }
0677 
0678     return pinctrl_pm_select_sleep_state(dev);
0679 }
0680 
0681 static int __maybe_unused stm32_pwm_resume(struct device *dev)
0682 {
0683     struct stm32_pwm *priv = dev_get_drvdata(dev);
0684     int ret;
0685 
0686     ret = pinctrl_pm_select_default_state(dev);
0687     if (ret)
0688         return ret;
0689 
0690     /* restore breakinput registers that may have been lost in low power */
0691     return stm32_pwm_apply_breakinputs(priv);
0692 }
0693 
0694 static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
0695 
0696 static const struct of_device_id stm32_pwm_of_match[] = {
0697     { .compatible = "st,stm32-pwm", },
0698     { /* end node */ },
0699 };
0700 MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
0701 
0702 static struct platform_driver stm32_pwm_driver = {
0703     .probe  = stm32_pwm_probe,
0704     .remove = stm32_pwm_remove,
0705     .driver = {
0706         .name = "stm32-pwm",
0707         .of_match_table = stm32_pwm_of_match,
0708         .pm = &stm32_pwm_pm_ops,
0709     },
0710 };
0711 module_platform_driver(stm32_pwm_driver);
0712 
0713 MODULE_ALIAS("platform:stm32-pwm");
0714 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
0715 MODULE_LICENSE("GPL v2");
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