drivers/pwm/pwm-stm32-lp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * STM32 Low-Power Timer PWM driver
0004  *
0005  * Copyright (C) STMicroelectronics 2017
0006  *
0007  * Author: Gerald Baeza <gerald.baeza@st.com>
0008  *
0009  * Inspired by Gerald Baeza's pwm-stm32 driver
0010  */
0011
0012 #include <linux/bitfield.h>
0013 #include <linux/mfd/stm32-lptimer.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/pinctrl/consumer.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pwm.h>
0019
0020 struct stm32_pwm_lp {
0021     struct pwm_chip chip;
0022     struct clk *clk;
0023     struct regmap *regmap;
0024 };
0025
0026 static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip)
0027 {
0028     return container_of(chip, struct stm32_pwm_lp, chip);
0029 }
0030
0031 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
0032 #define STM32_LPTIM_MAX_PRESCALER   128
0033
0034 static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0035                   const struct pwm_state *state)
0036 {
0037     struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
0038     unsigned long long prd, div, dty;
0039     struct pwm_state cstate;
0040     u32 val, mask, cfgr, presc = 0;
0041     bool reenable;
0042     int ret;
0043
0044     pwm_get_state(pwm, &cstate);
0045     reenable = !cstate.enabled;
0046
0047     if (!state->enabled) {
0048         if (cstate.enabled) {
0049             /* Disable LP timer */
0050             ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
0051             if (ret)
0052                 return ret;
0053             /* disable clock to PWM counter */
0054             clk_disable(priv->clk);
0055         }
0056         return 0;
0057     }
0058
0059     /* Calculate the period and prescaler value */
0060     div = (unsigned long long)clk_get_rate(priv->clk) * state->period;
0061     do_div(div, NSEC_PER_SEC);
0062     if (!div) {
0063         /* Clock is too slow to achieve requested period. */
0064         dev_dbg(priv->chip.dev, "Can't reach %llu ns\n", state->period);
0065         return -EINVAL;
0066     }
0067
0068     prd = div;
0069     while (div > STM32_LPTIM_MAX_ARR) {
0070         presc++;
0071         if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) {
0072             dev_err(priv->chip.dev, "max prescaler exceeded\n");
0073             return -EINVAL;
0074         }
0075         div = prd >> presc;
0076     }
0077     prd = div;
0078
0079     /* Calculate the duty cycle */
0080     dty = prd * state->duty_cycle;
0081     do_div(dty, state->period);
0082
0083     if (!cstate.enabled) {
0084         /* enable clock to drive PWM counter */
0085         ret = clk_enable(priv->clk);
0086         if (ret)
0087             return ret;
0088     }
0089
0090     ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr);
0091     if (ret)
0092         goto err;
0093
0094     if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) ||
0095         (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) {
0096         val = FIELD_PREP(STM32_LPTIM_PRESC, presc);
0097         val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity);
0098         mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL;
0099
0100         /* Must disable LP timer to modify CFGR */
0101         reenable = true;
0102         ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
0103         if (ret)
0104             goto err;
0105
0106         ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask,
0107                      val);
0108         if (ret)
0109             goto err;
0110     }
0111
0112     if (reenable) {
0113         /* Must (re)enable LP timer to modify CMP & ARR */
0114         ret = regmap_write(priv->regmap, STM32_LPTIM_CR,
0115                    STM32_LPTIM_ENABLE);
0116         if (ret)
0117             goto err;
0118     }
0119
0120     ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, prd - 1);
0121     if (ret)
0122         goto err;
0123
0124     ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty));
0125     if (ret)
0126         goto err;
0127
0128     /* ensure CMP & ARR registers are properly written */
0129     ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
0130                        (val & STM32_LPTIM_CMPOK_ARROK),
0131                        100, 1000);
0132     if (ret) {
0133         dev_err(priv->chip.dev, "ARR/CMP registers write issue\n");
0134         goto err;
0135     }
0136     ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
0137                STM32_LPTIM_CMPOKCF_ARROKCF);
0138     if (ret)
0139         goto err;
0140
0141     if (reenable) {
0142         /* Start LP timer in continuous mode */
0143         ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
0144                      STM32_LPTIM_CNTSTRT,
0145                      STM32_LPTIM_CNTSTRT);
0146         if (ret) {
0147             regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
0148             goto err;
0149         }
0150     }
0151
0152     return 0;
0153 err:
0154     if (!cstate.enabled)
0155         clk_disable(priv->clk);
0156
0157     return ret;
0158 }
0159
0160 static void stm32_pwm_lp_get_state(struct pwm_chip *chip,
0161                    struct pwm_device *pwm,
0162                    struct pwm_state *state)
0163 {
0164     struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
0165     unsigned long rate = clk_get_rate(priv->clk);
0166     u32 val, presc, prd;
0167     u64 tmp;
0168
0169     regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
0170     state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val);
0171     /* Keep PWM counter clock refcount in sync with PWM initial state */
0172     if (state->enabled)
0173         clk_enable(priv->clk);
0174
0175     regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val);
0176     presc = FIELD_GET(STM32_LPTIM_PRESC, val);
0177     state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val);
0178
0179     regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd);
0180     tmp = prd + 1;
0181     tmp = (tmp << presc) * NSEC_PER_SEC;
0182     state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
0183
0184     regmap_read(priv->regmap, STM32_LPTIM_CMP, &val);
0185     tmp = prd - val;
0186     tmp = (tmp << presc) * NSEC_PER_SEC;
0187     state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
0188 }
0189
0190 static const struct pwm_ops stm32_pwm_lp_ops = {
0191     .owner = THIS_MODULE,
0192     .apply = stm32_pwm_lp_apply,
0193     .get_state = stm32_pwm_lp_get_state,
0194 };
0195
0196 static int stm32_pwm_lp_probe(struct platform_device *pdev)
0197 {
0198     struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
0199     struct stm32_pwm_lp *priv;
0200     int ret;
0201
0202     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0203     if (!priv)
0204         return -ENOMEM;
0205
0206     priv->regmap = ddata->regmap;
0207     priv->clk = ddata->clk;
0208     priv->chip.dev = &pdev->dev;
0209     priv->chip.ops = &stm32_pwm_lp_ops;
0210     priv->chip.npwm = 1;
0211
0212     ret = devm_pwmchip_add(&pdev->dev, &priv->chip);
0213     if (ret < 0)
0214         return ret;
0215
0216     platform_set_drvdata(pdev, priv);
0217
0218     return 0;
0219 }
0220
0221 static int __maybe_unused stm32_pwm_lp_suspend(struct device *dev)
0222 {
0223     struct stm32_pwm_lp *priv = dev_get_drvdata(dev);
0224     struct pwm_state state;
0225
0226     pwm_get_state(&priv->chip.pwms[0], &state);
0227     if (state.enabled) {
0228         dev_err(dev, "The consumer didn't stop us (%s)\n",
0229             priv->chip.pwms[0].label);
0230         return -EBUSY;
0231     }
0232
0233     return pinctrl_pm_select_sleep_state(dev);
0234 }
0235
0236 static int __maybe_unused stm32_pwm_lp_resume(struct device *dev)
0237 {
0238     return pinctrl_pm_select_default_state(dev);
0239 }
0240
0241 static SIMPLE_DEV_PM_OPS(stm32_pwm_lp_pm_ops, stm32_pwm_lp_suspend,
0242              stm32_pwm_lp_resume);
0243
0244 static const struct of_device_id stm32_pwm_lp_of_match[] = {
0245     { .compatible = "st,stm32-pwm-lp", },
0246     {},
0247 };
0248 MODULE_DEVICE_TABLE(of, stm32_pwm_lp_of_match);
0249
0250 static struct platform_driver stm32_pwm_lp_driver = {
0251     .probe  = stm32_pwm_lp_probe,
0252     .driver = {
0253         .name = "stm32-pwm-lp",
0254         .of_match_table = of_match_ptr(stm32_pwm_lp_of_match),
0255         .pm = &stm32_pwm_lp_pm_ops,
0256     },
0257 };
0258 module_platform_driver(stm32_pwm_lp_driver);
0259
0260 MODULE_ALIAS("platform:stm32-pwm-lp");
0261 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM LP driver");
0262 MODULE_LICENSE("GPL v2");