drivers/pwm/pwm-sl28cpld.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * sl28cpld PWM driver
0004  *
0005  * Copyright (c) 2020 Michael Walle <michael@walle.cc>
0006  *
0007  * There is no public datasheet available for this PWM core. But it is easy
0008  * enough to be briefly explained. It consists of one 8-bit counter. The PWM
0009  * supports four distinct frequencies by selecting when to reset the counter.
0010  * With the prescaler setting you can select which bit of the counter is used
0011  * to reset it. This implies that the higher the frequency the less remaining
0012  * bits are available for the actual counter.
0013  *
0014  * Let cnt[7:0] be the counter, clocked at 32kHz:
0015  * +-----------+--------+--------------+-----------+---------------+
0016  * | prescaler |  reset | counter bits | frequency | period length |
0017  * +-----------+--------+--------------+-----------+---------------+
0018  * |         0 | cnt[7] |     cnt[6:0] |    250 Hz |    4000000 ns |
0019  * |         1 | cnt[6] |     cnt[5:0] |    500 Hz |    2000000 ns |
0020  * |         2 | cnt[5] |     cnt[4:0] |     1 kHz |    1000000 ns |
0021  * |         3 | cnt[4] |     cnt[3:0] |     2 kHz |     500000 ns |
0022  * +-----------+--------+--------------+-----------+---------------+
0023  *
0024  * Limitations:
0025  * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
0026  * - The hardware cannot atomically set the prescaler and the counter value,
0027  *   which might lead to glitches and inconsistent states if a write fails.
0028  * - The counter is not reset if you switch the prescaler which leads
0029  *   to glitches, too.
0030  * - The duty cycle will switch immediately and not after a complete cycle.
0031  * - Depending on the actual implementation, disabling the PWM might have
0032  *   side effects. For example, if the output pin is shared with a GPIO pin
0033  *   it will automatically switch back to GPIO mode.
0034  */
0035
0036 #include <linux/bitfield.h>
0037 #include <linux/kernel.h>
0038 #include <linux/mod_devicetable.h>
0039 #include <linux/module.h>
0040 #include <linux/platform_device.h>
0041 #include <linux/pwm.h>
0042 #include <linux/regmap.h>
0043
0044 /*
0045  * PWM timer block registers.
0046  */
0047 #define SL28CPLD_PWM_CTRL           0x00
0048 #define   SL28CPLD_PWM_CTRL_ENABLE      BIT(7)
0049 #define   SL28CPLD_PWM_CTRL_PRESCALER_MASK  GENMASK(1, 0)
0050 #define SL28CPLD_PWM_CYCLE          0x01
0051 #define   SL28CPLD_PWM_CYCLE_MAX        GENMASK(6, 0)
0052
0053 #define SL28CPLD_PWM_CLK            32000 /* 32 kHz */
0054 #define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)  (1 << (7 - (prescaler)))
0055 #define SL28CPLD_PWM_PERIOD(prescaler) \
0056     (NSEC_PER_SEC / SL28CPLD_PWM_CLK * SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler))
0057
0058 /*
0059  * We calculate the duty cycle like this:
0060  *   duty_cycle_ns = pwm_cycle_reg * max_period_ns / max_duty_cycle
0061  *
0062  * With
0063  *   max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
0064  *   max_duty_cycle = 1 << (7 - prescaler)
0065  * this then simplifies to:
0066  *   duty_cycle_ns = pwm_cycle_reg / SL28CPLD_PWM_CLK * NSEC_PER_SEC
0067  *                 = NSEC_PER_SEC / SL28CPLD_PWM_CLK * pwm_cycle_reg
0068  *
0069  * NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing
0070  * precision by doing the divison first.
0071  */
0072 #define SL28CPLD_PWM_TO_DUTY_CYCLE(reg) \
0073     (NSEC_PER_SEC / SL28CPLD_PWM_CLK * (reg))
0074 #define SL28CPLD_PWM_FROM_DUTY_CYCLE(duty_cycle) \
0075     (DIV_ROUND_DOWN_ULL((duty_cycle), NSEC_PER_SEC / SL28CPLD_PWM_CLK))
0076
0077 #define sl28cpld_pwm_read(priv, reg, val) \
0078     regmap_read((priv)->regmap, (priv)->offset + (reg), (val))
0079 #define sl28cpld_pwm_write(priv, reg, val) \
0080     regmap_write((priv)->regmap, (priv)->offset + (reg), (val))
0081
0082 struct sl28cpld_pwm {
0083     struct pwm_chip pwm_chip;
0084     struct regmap *regmap;
0085     u32 offset;
0086 };
0087 #define sl28cpld_pwm_from_chip(_chip) \
0088     container_of(_chip, struct sl28cpld_pwm, pwm_chip)
0089
0090 static void sl28cpld_pwm_get_state(struct pwm_chip *chip,
0091                    struct pwm_device *pwm,
0092                    struct pwm_state *state)
0093 {
0094     struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
0095     unsigned int reg;
0096     int prescaler;
0097
0098     sl28cpld_pwm_read(priv, SL28CPLD_PWM_CTRL, &reg);
0099
0100     state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE;
0101
0102     prescaler = FIELD_GET(SL28CPLD_PWM_CTRL_PRESCALER_MASK, reg);
0103     state->period = SL28CPLD_PWM_PERIOD(prescaler);
0104
0105     sl28cpld_pwm_read(priv, SL28CPLD_PWM_CYCLE, &reg);
0106     state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg);
0107     state->polarity = PWM_POLARITY_NORMAL;
0108
0109     /*
0110      * Sanitize values for the PWM core. Depending on the prescaler it
0111      * might happen that we calculate a duty_cycle greater than the actual
0112      * period. This might happen if someone (e.g. the bootloader) sets an
0113      * invalid combination of values. The behavior of the hardware is
0114      * undefined in this case. But we need to report sane values back to
0115      * the PWM core.
0116      */
0117     state->duty_cycle = min(state->duty_cycle, state->period);
0118 }
0119
0120 static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0121                   const struct pwm_state *state)
0122 {
0123     struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
0124     unsigned int cycle, prescaler;
0125     bool write_duty_cycle_first;
0126     int ret;
0127     u8 ctrl;
0128
0129     /* Polarity inversion is not supported */
0130     if (state->polarity != PWM_POLARITY_NORMAL)
0131         return -EINVAL;
0132
0133     /*
0134      * Calculate the prescaler. Pick the biggest period that isn't
0135      * bigger than the requested period.
0136      */
0137     prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);
0138     prescaler = order_base_2(prescaler);
0139
0140     if (prescaler > field_max(SL28CPLD_PWM_CTRL_PRESCALER_MASK))
0141         return -ERANGE;
0142
0143     ctrl = FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, prescaler);
0144     if (state->enabled)
0145         ctrl |= SL28CPLD_PWM_CTRL_ENABLE;
0146
0147     cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle);
0148     cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler));
0149
0150     /*
0151      * Work around the hardware limitation. See also above. Trap 100% duty
0152      * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't
0153      * care about the frequency because its "all-one" in either case.
0154      *
0155      * We don't need to check the actual prescaler setting, because only
0156      * if the prescaler is 0 we can have this particular value.
0157      */
0158     if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) {
0159         ctrl &= ~SL28CPLD_PWM_CTRL_PRESCALER_MASK;
0160         ctrl |= FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, 1);
0161         cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1);
0162     }
0163
0164     /*
0165      * To avoid glitches when we switch the prescaler, we have to make sure
0166      * we have a valid duty cycle for the new mode.
0167      *
0168      * Take the current prescaler (or the current period length) into
0169      * account to decide whether we have to write the duty cycle or the new
0170      * prescaler first. If the period length is decreasing we have to
0171      * write the duty cycle first.
0172      */
0173     write_duty_cycle_first = pwm->state.period > state->period;
0174
0175     if (write_duty_cycle_first) {
0176         ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
0177         if (ret)
0178             return ret;
0179     }
0180
0181     ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CTRL, ctrl);
0182     if (ret)
0183         return ret;
0184
0185     if (!write_duty_cycle_first) {
0186         ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
0187         if (ret)
0188             return ret;
0189     }
0190
0191     return 0;
0192 }
0193
0194 static const struct pwm_ops sl28cpld_pwm_ops = {
0195     .apply = sl28cpld_pwm_apply,
0196     .get_state = sl28cpld_pwm_get_state,
0197     .owner = THIS_MODULE,
0198 };
0199
0200 static int sl28cpld_pwm_probe(struct platform_device *pdev)
0201 {
0202     struct sl28cpld_pwm *priv;
0203     struct pwm_chip *chip;
0204     int ret;
0205
0206     if (!pdev->dev.parent) {
0207         dev_err(&pdev->dev, "no parent device\n");
0208         return -ENODEV;
0209     }
0210
0211     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0212     if (!priv)
0213         return -ENOMEM;
0214
0215     priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
0216     if (!priv->regmap) {
0217         dev_err(&pdev->dev, "could not get parent regmap\n");
0218         return -ENODEV;
0219     }
0220
0221     ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset);
0222     if (ret) {
0223         dev_err(&pdev->dev, "no 'reg' property found (%pe)\n",
0224             ERR_PTR(ret));
0225         return -EINVAL;
0226     }
0227
0228     /* Initialize the pwm_chip structure */
0229     chip = &priv->pwm_chip;
0230     chip->dev = &pdev->dev;
0231     chip->ops = &sl28cpld_pwm_ops;
0232     chip->npwm = 1;
0233
0234     ret = devm_pwmchip_add(&pdev->dev, &priv->pwm_chip);
0235     if (ret) {
0236         dev_err(&pdev->dev, "failed to add PWM chip (%pe)",
0237             ERR_PTR(ret));
0238         return ret;
0239     }
0240
0241     return 0;
0242 }
0243
0244 static const struct of_device_id sl28cpld_pwm_of_match[] = {
0245     { .compatible = "kontron,sl28cpld-pwm" },
0246     {}
0247 };
0248 MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match);
0249
0250 static struct platform_driver sl28cpld_pwm_driver = {
0251     .probe = sl28cpld_pwm_probe,
0252     .driver = {
0253         .name = "sl28cpld-pwm",
0254         .of_match_table = sl28cpld_pwm_of_match,
0255     },
0256 };
0257 module_platform_driver(sl28cpld_pwm_driver);
0258
0259 MODULE_DESCRIPTION("sl28cpld PWM Driver");
0260 MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
0261 MODULE_LICENSE("GPL");