drivers/pwm/pwm-sifive.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2017-2018 SiFive
0004  * For SiFive's PWM IP block documentation please refer Chapter 14 of
0005  * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
0006  *
0007  * Limitations:
0008  * - When changing both duty cycle and period, we cannot prevent in
0009  *   software that the output might produce a period with mixed
0010  *   settings (new period length and old duty cycle).
0011  * - The hardware cannot generate a 100% duty cycle.
0012  * - The hardware generates only inverted output.
0013  */
0014 #include <linux/clk.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pwm.h>
0019 #include <linux/slab.h>
0020 #include <linux/bitfield.h>
0021
0022 /* Register offsets */
0023 #define PWM_SIFIVE_PWMCFG       0x0
0024 #define PWM_SIFIVE_PWMCOUNT     0x8
0025 #define PWM_SIFIVE_PWMS         0x10
0026 #define PWM_SIFIVE_PWMCMP(i)        (0x20 + 4 * (i))
0027
0028 /* PWMCFG fields */
0029 #define PWM_SIFIVE_PWMCFG_SCALE     GENMASK(3, 0)
0030 #define PWM_SIFIVE_PWMCFG_STICKY    BIT(8)
0031 #define PWM_SIFIVE_PWMCFG_ZERO_CMP  BIT(9)
0032 #define PWM_SIFIVE_PWMCFG_DEGLITCH  BIT(10)
0033 #define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
0034 #define PWM_SIFIVE_PWMCFG_EN_ONCE   BIT(13)
0035 #define PWM_SIFIVE_PWMCFG_CENTER    BIT(16)
0036 #define PWM_SIFIVE_PWMCFG_GANG      BIT(24)
0037 #define PWM_SIFIVE_PWMCFG_IP        BIT(28)
0038
0039 #define PWM_SIFIVE_CMPWIDTH     16
0040 #define PWM_SIFIVE_DEFAULT_PERIOD   10000000
0041
0042 struct pwm_sifive_ddata {
0043     struct pwm_chip chip;
0044     struct mutex lock; /* lock to protect user_count and approx_period */
0045     struct notifier_block notifier;
0046     struct clk *clk;
0047     void __iomem *regs;
0048     unsigned int real_period;
0049     unsigned int approx_period;
0050     int user_count;
0051 };
0052
0053 static inline
0054 struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
0055 {
0056     return container_of(c, struct pwm_sifive_ddata, chip);
0057 }
0058
0059 static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
0060 {
0061     struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
0062
0063     mutex_lock(&ddata->lock);
0064     ddata->user_count++;
0065     mutex_unlock(&ddata->lock);
0066
0067     return 0;
0068 }
0069
0070 static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
0071 {
0072     struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
0073
0074     mutex_lock(&ddata->lock);
0075     ddata->user_count--;
0076     mutex_unlock(&ddata->lock);
0077 }
0078
0079 /* Called holding ddata->lock */
0080 static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
0081                     unsigned long rate)
0082 {
0083     unsigned long long num;
0084     unsigned long scale_pow;
0085     int scale;
0086     u32 val;
0087     /*
0088      * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
0089      * period length is using pwmscale which provides the number of bits the
0090      * counter is shifted before being feed to the comparators. A period
0091      * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
0092      * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
0093      */
0094     scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
0095     scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
0096
0097     val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
0098           FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
0099     writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
0100
0101     /* As scale <= 15 the shift operation cannot overflow. */
0102     num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
0103     ddata->real_period = div64_ul(num, rate);
0104     dev_dbg(ddata->chip.dev,
0105         "New real_period = %u ns\n", ddata->real_period);
0106 }
0107
0108 static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
0109                  struct pwm_state *state)
0110 {
0111     struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
0112     u32 duty, val;
0113
0114     duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
0115
0116     state->enabled = duty > 0;
0117
0118     val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
0119     if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
0120         state->enabled = false;
0121
0122     state->period = ddata->real_period;
0123     state->duty_cycle =
0124         (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
0125     state->polarity = PWM_POLARITY_INVERSED;
0126 }
0127
0128 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0129                 const struct pwm_state *state)
0130 {
0131     struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
0132     struct pwm_state cur_state;
0133     unsigned int duty_cycle;
0134     unsigned long long num;
0135     bool enabled;
0136     int ret = 0;
0137     u32 frac;
0138
0139     if (state->polarity != PWM_POLARITY_INVERSED)
0140         return -EINVAL;
0141
0142     cur_state = pwm->state;
0143     enabled = cur_state.enabled;
0144
0145     duty_cycle = state->duty_cycle;
0146     if (!state->enabled)
0147         duty_cycle = 0;
0148
0149     /*
0150      * The problem of output producing mixed setting as mentioned at top,
0151      * occurs here. To minimize the window for this problem, we are
0152      * calculating the register values first and then writing them
0153      * consecutively
0154      */
0155     num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
0156     frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
0157     /* The hardware cannot generate a 100% duty cycle */
0158     frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
0159
0160     mutex_lock(&ddata->lock);
0161     if (state->period != ddata->approx_period) {
0162         if (ddata->user_count != 1) {
0163             mutex_unlock(&ddata->lock);
0164             return -EBUSY;
0165         }
0166         ddata->approx_period = state->period;
0167         pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
0168     }
0169     mutex_unlock(&ddata->lock);
0170
0171     /*
0172      * If the PWM is enabled the clk is already on. So only enable it
0173      * conditionally to have it on exactly once afterwards independent of
0174      * the PWM state.
0175      */
0176     if (!enabled) {
0177         ret = clk_enable(ddata->clk);
0178         if (ret) {
0179             dev_err(ddata->chip.dev, "Enable clk failed\n");
0180             return ret;
0181         }
0182     }
0183
0184     writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
0185
0186     if (!state->enabled)
0187         clk_disable(ddata->clk);
0188
0189     return 0;
0190 }
0191
0192 static const struct pwm_ops pwm_sifive_ops = {
0193     .request = pwm_sifive_request,
0194     .free = pwm_sifive_free,
0195     .get_state = pwm_sifive_get_state,
0196     .apply = pwm_sifive_apply,
0197     .owner = THIS_MODULE,
0198 };
0199
0200 static int pwm_sifive_clock_notifier(struct notifier_block *nb,
0201                      unsigned long event, void *data)
0202 {
0203     struct clk_notifier_data *ndata = data;
0204     struct pwm_sifive_ddata *ddata =
0205         container_of(nb, struct pwm_sifive_ddata, notifier);
0206
0207     if (event == POST_RATE_CHANGE)
0208         pwm_sifive_update_clock(ddata, ndata->new_rate);
0209
0210     return NOTIFY_OK;
0211 }
0212
0213 static int pwm_sifive_probe(struct platform_device *pdev)
0214 {
0215     struct device *dev = &pdev->dev;
0216     struct pwm_sifive_ddata *ddata;
0217     struct pwm_chip *chip;
0218     int ret;
0219     u32 val;
0220     unsigned int enabled_pwms = 0, enabled_clks = 1;
0221
0222     ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
0223     if (!ddata)
0224         return -ENOMEM;
0225
0226     mutex_init(&ddata->lock);
0227     chip = &ddata->chip;
0228     chip->dev = dev;
0229     chip->ops = &pwm_sifive_ops;
0230     chip->npwm = 4;
0231
0232     ddata->regs = devm_platform_ioremap_resource(pdev, 0);
0233     if (IS_ERR(ddata->regs))
0234         return PTR_ERR(ddata->regs);
0235
0236     ddata->clk = devm_clk_get(dev, NULL);
0237     if (IS_ERR(ddata->clk))
0238         return dev_err_probe(dev, PTR_ERR(ddata->clk),
0239                      "Unable to find controller clock\n");
0240
0241     ret = clk_prepare_enable(ddata->clk);
0242     if (ret) {
0243         dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
0244         return ret;
0245     }
0246
0247     val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
0248     if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
0249         unsigned int i;
0250
0251         for (i = 0; i < chip->npwm; ++i) {
0252             val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
0253             if (val > 0)
0254                 ++enabled_pwms;
0255         }
0256     }
0257
0258     /* The clk should be on once for each running PWM. */
0259     if (enabled_pwms) {
0260         while (enabled_clks < enabled_pwms) {
0261             /* This is not expected to fail as the clk is already on */
0262             ret = clk_enable(ddata->clk);
0263             if (unlikely(ret)) {
0264                 dev_err_probe(dev, ret, "Failed to enable clk\n");
0265                 goto disable_clk;
0266             }
0267             ++enabled_clks;
0268         }
0269     } else {
0270         clk_disable(ddata->clk);
0271         enabled_clks = 0;
0272     }
0273
0274     /* Watch for changes to underlying clock frequency */
0275     ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
0276     ret = clk_notifier_register(ddata->clk, &ddata->notifier);
0277     if (ret) {
0278         dev_err(dev, "failed to register clock notifier: %d\n", ret);
0279         goto disable_clk;
0280     }
0281
0282     ret = pwmchip_add(chip);
0283     if (ret < 0) {
0284         dev_err(dev, "cannot register PWM: %d\n", ret);
0285         goto unregister_clk;
0286     }
0287
0288     platform_set_drvdata(pdev, ddata);
0289     dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
0290
0291     return 0;
0292
0293 unregister_clk:
0294     clk_notifier_unregister(ddata->clk, &ddata->notifier);
0295 disable_clk:
0296     while (enabled_clks) {
0297         clk_disable(ddata->clk);
0298         --enabled_clks;
0299     }
0300     clk_unprepare(ddata->clk);
0301
0302     return ret;
0303 }
0304
0305 static int pwm_sifive_remove(struct platform_device *dev)
0306 {
0307     struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
0308     struct pwm_device *pwm;
0309     int ch;
0310
0311     pwmchip_remove(&ddata->chip);
0312     clk_notifier_unregister(ddata->clk, &ddata->notifier);
0313
0314     for (ch = 0; ch < ddata->chip.npwm; ch++) {
0315         pwm = &ddata->chip.pwms[ch];
0316         if (pwm->state.enabled)
0317             clk_disable(ddata->clk);
0318     }
0319
0320     clk_unprepare(ddata->clk);
0321
0322     return 0;
0323 }
0324
0325 static const struct of_device_id pwm_sifive_of_match[] = {
0326     { .compatible = "sifive,pwm0" },
0327     {},
0328 };
0329 MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
0330
0331 static struct platform_driver pwm_sifive_driver = {
0332     .probe = pwm_sifive_probe,
0333     .remove = pwm_sifive_remove,
0334     .driver = {
0335         .name = "pwm-sifive",
0336         .of_match_table = pwm_sifive_of_match,
0337     },
0338 };
0339 module_platform_driver(pwm_sifive_driver);
0340
0341 MODULE_DESCRIPTION("SiFive PWM driver");
0342 MODULE_LICENSE("GPL v2");