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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2007 Ben Dooks
0004  * Copyright (c) 2008 Simtec Electronics
0005  *     Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
0006  * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
0007  * Copyright (c) 2017 Samsung Electronics Co., Ltd.
0008  *
0009  * PWM driver for Samsung SoCs
0010  */
0011 
0012 #include <linux/bitops.h>
0013 #include <linux/clk.h>
0014 #include <linux/export.h>
0015 #include <linux/err.h>
0016 #include <linux/io.h>
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/pwm.h>
0022 #include <linux/slab.h>
0023 #include <linux/spinlock.h>
0024 #include <linux/time.h>
0025 
0026 /* For struct samsung_timer_variant and samsung_pwm_lock. */
0027 #include <clocksource/samsung_pwm.h>
0028 
0029 #define REG_TCFG0           0x00
0030 #define REG_TCFG1           0x04
0031 #define REG_TCON            0x08
0032 
0033 #define REG_TCNTB(chan)         (0x0c + ((chan) * 0xc))
0034 #define REG_TCMPB(chan)         (0x10 + ((chan) * 0xc))
0035 
0036 #define TCFG0_PRESCALER_MASK        0xff
0037 #define TCFG0_PRESCALER1_SHIFT      8
0038 
0039 #define TCFG1_MUX_MASK          0xf
0040 #define TCFG1_SHIFT(chan)       (4 * (chan))
0041 
0042 /*
0043  * Each channel occupies 4 bits in TCON register, but there is a gap of 4
0044  * bits (one channel) after channel 0, so channels have different numbering
0045  * when accessing TCON register. See to_tcon_channel() function.
0046  *
0047  * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
0048  * in its set of bits is 2 as opposed to 3 for other channels.
0049  */
0050 #define TCON_START(chan)        BIT(4 * (chan) + 0)
0051 #define TCON_MANUALUPDATE(chan)     BIT(4 * (chan) + 1)
0052 #define TCON_INVERT(chan)       BIT(4 * (chan) + 2)
0053 #define _TCON_AUTORELOAD(chan)      BIT(4 * (chan) + 3)
0054 #define _TCON_AUTORELOAD4(chan)     BIT(4 * (chan) + 2)
0055 #define TCON_AUTORELOAD(chan)       \
0056     ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
0057 
0058 /**
0059  * struct samsung_pwm_channel - private data of PWM channel
0060  * @period_ns:  current period in nanoseconds programmed to the hardware
0061  * @duty_ns:    current duty time in nanoseconds programmed to the hardware
0062  * @tin_ns: time of one timer tick in nanoseconds with current timer rate
0063  */
0064 struct samsung_pwm_channel {
0065     u32 period_ns;
0066     u32 duty_ns;
0067     u32 tin_ns;
0068 };
0069 
0070 /**
0071  * struct samsung_pwm_chip - private data of PWM chip
0072  * @chip:       generic PWM chip
0073  * @variant:        local copy of hardware variant data
0074  * @inverter_mask:  inverter status for all channels - one bit per channel
0075  * @disabled_mask:  disabled status for all channels - one bit per channel
0076  * @base:       base address of mapped PWM registers
0077  * @base_clk:       base clock used to drive the timers
0078  * @tclk0:      external clock 0 (can be ERR_PTR if not present)
0079  * @tclk1:      external clock 1 (can be ERR_PTR if not present)
0080  */
0081 struct samsung_pwm_chip {
0082     struct pwm_chip chip;
0083     struct samsung_pwm_variant variant;
0084     u8 inverter_mask;
0085     u8 disabled_mask;
0086 
0087     void __iomem *base;
0088     struct clk *base_clk;
0089     struct clk *tclk0;
0090     struct clk *tclk1;
0091 };
0092 
0093 #ifndef CONFIG_CLKSRC_SAMSUNG_PWM
0094 /*
0095  * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
0096  * and some registers need access synchronization. If both drivers are
0097  * compiled in, the spinlock is defined in the clocksource driver,
0098  * otherwise following definition is used.
0099  *
0100  * Currently we do not need any more complex synchronization method
0101  * because all the supported SoCs contain only one instance of the PWM
0102  * IP. Should this change, both drivers will need to be modified to
0103  * properly synchronize accesses to particular instances.
0104  */
0105 static DEFINE_SPINLOCK(samsung_pwm_lock);
0106 #endif
0107 
0108 static inline
0109 struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
0110 {
0111     return container_of(chip, struct samsung_pwm_chip, chip);
0112 }
0113 
0114 static inline unsigned int to_tcon_channel(unsigned int channel)
0115 {
0116     /* TCON register has a gap of 4 bits (1 channel) after channel 0 */
0117     return (channel == 0) ? 0 : (channel + 1);
0118 }
0119 
0120 static void __pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
0121                       struct pwm_device *pwm)
0122 {
0123     unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
0124     u32 tcon;
0125 
0126     tcon = readl(chip->base + REG_TCON);
0127     tcon |= TCON_MANUALUPDATE(tcon_chan);
0128     writel(tcon, chip->base + REG_TCON);
0129 
0130     tcon &= ~TCON_MANUALUPDATE(tcon_chan);
0131     writel(tcon, chip->base + REG_TCON);
0132 }
0133 
0134 static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm,
0135                     unsigned int channel, u8 divisor)
0136 {
0137     u8 shift = TCFG1_SHIFT(channel);
0138     unsigned long flags;
0139     u32 reg;
0140     u8 bits;
0141 
0142     bits = (fls(divisor) - 1) - pwm->variant.div_base;
0143 
0144     spin_lock_irqsave(&samsung_pwm_lock, flags);
0145 
0146     reg = readl(pwm->base + REG_TCFG1);
0147     reg &= ~(TCFG1_MUX_MASK << shift);
0148     reg |= bits << shift;
0149     writel(reg, pwm->base + REG_TCFG1);
0150 
0151     spin_unlock_irqrestore(&samsung_pwm_lock, flags);
0152 }
0153 
0154 static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan)
0155 {
0156     struct samsung_pwm_variant *variant = &chip->variant;
0157     u32 reg;
0158 
0159     reg = readl(chip->base + REG_TCFG1);
0160     reg >>= TCFG1_SHIFT(chan);
0161     reg &= TCFG1_MUX_MASK;
0162 
0163     return (BIT(reg) & variant->tclk_mask) == 0;
0164 }
0165 
0166 static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip,
0167                           unsigned int chan)
0168 {
0169     unsigned long rate;
0170     u32 reg;
0171 
0172     rate = clk_get_rate(chip->base_clk);
0173 
0174     reg = readl(chip->base + REG_TCFG0);
0175     if (chan >= 2)
0176         reg >>= TCFG0_PRESCALER1_SHIFT;
0177     reg &= TCFG0_PRESCALER_MASK;
0178 
0179     return rate / (reg + 1);
0180 }
0181 
0182 static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip,
0183                       unsigned int chan, unsigned long freq)
0184 {
0185     struct samsung_pwm_variant *variant = &chip->variant;
0186     unsigned long rate;
0187     struct clk *clk;
0188     u8 div;
0189 
0190     if (!pwm_samsung_is_tdiv(chip, chan)) {
0191         clk = (chan < 2) ? chip->tclk0 : chip->tclk1;
0192         if (!IS_ERR(clk)) {
0193             rate = clk_get_rate(clk);
0194             if (rate)
0195                 return rate;
0196         }
0197 
0198         dev_warn(chip->chip.dev,
0199             "tclk of PWM %d is inoperational, using tdiv\n", chan);
0200     }
0201 
0202     rate = pwm_samsung_get_tin_rate(chip, chan);
0203     dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate);
0204 
0205     /*
0206      * Compare minimum PWM frequency that can be achieved with possible
0207      * divider settings and choose the lowest divisor that can generate
0208      * frequencies lower than requested.
0209      */
0210     if (variant->bits < 32) {
0211         /* Only for s3c24xx */
0212         for (div = variant->div_base; div < 4; ++div)
0213             if ((rate >> (variant->bits + div)) < freq)
0214                 break;
0215     } else {
0216         /*
0217          * Other variants have enough counter bits to generate any
0218          * requested rate, so no need to check higher divisors.
0219          */
0220         div = variant->div_base;
0221     }
0222 
0223     pwm_samsung_set_divisor(chip, chan, BIT(div));
0224 
0225     return rate >> div;
0226 }
0227 
0228 static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
0229 {
0230     struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
0231     struct samsung_pwm_channel *our_chan;
0232 
0233     if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
0234         dev_warn(chip->dev,
0235             "tried to request PWM channel %d without output\n",
0236             pwm->hwpwm);
0237         return -EINVAL;
0238     }
0239 
0240     our_chan = kzalloc(sizeof(*our_chan), GFP_KERNEL);
0241     if (!our_chan)
0242         return -ENOMEM;
0243 
0244     pwm_set_chip_data(pwm, our_chan);
0245 
0246     return 0;
0247 }
0248 
0249 static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm)
0250 {
0251     kfree(pwm_get_chip_data(pwm));
0252 }
0253 
0254 static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
0255 {
0256     struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
0257     unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
0258     unsigned long flags;
0259     u32 tcon;
0260 
0261     spin_lock_irqsave(&samsung_pwm_lock, flags);
0262 
0263     tcon = readl(our_chip->base + REG_TCON);
0264 
0265     tcon &= ~TCON_START(tcon_chan);
0266     tcon |= TCON_MANUALUPDATE(tcon_chan);
0267     writel(tcon, our_chip->base + REG_TCON);
0268 
0269     tcon &= ~TCON_MANUALUPDATE(tcon_chan);
0270     tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
0271     writel(tcon, our_chip->base + REG_TCON);
0272 
0273     our_chip->disabled_mask &= ~BIT(pwm->hwpwm);
0274 
0275     spin_unlock_irqrestore(&samsung_pwm_lock, flags);
0276 
0277     return 0;
0278 }
0279 
0280 static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
0281 {
0282     struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
0283     unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
0284     unsigned long flags;
0285     u32 tcon;
0286 
0287     spin_lock_irqsave(&samsung_pwm_lock, flags);
0288 
0289     tcon = readl(our_chip->base + REG_TCON);
0290     tcon &= ~TCON_AUTORELOAD(tcon_chan);
0291     writel(tcon, our_chip->base + REG_TCON);
0292 
0293     /*
0294      * In case the PWM is at 100% duty cycle, force a manual
0295      * update to prevent the signal from staying high.
0296      */
0297     if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U)
0298         __pwm_samsung_manual_update(our_chip, pwm);
0299 
0300     our_chip->disabled_mask |= BIT(pwm->hwpwm);
0301 
0302     spin_unlock_irqrestore(&samsung_pwm_lock, flags);
0303 }
0304 
0305 static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
0306                       struct pwm_device *pwm)
0307 {
0308     unsigned long flags;
0309 
0310     spin_lock_irqsave(&samsung_pwm_lock, flags);
0311 
0312     __pwm_samsung_manual_update(chip, pwm);
0313 
0314     spin_unlock_irqrestore(&samsung_pwm_lock, flags);
0315 }
0316 
0317 static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
0318                 int duty_ns, int period_ns, bool force_period)
0319 {
0320     struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
0321     struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
0322     u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
0323 
0324     tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
0325     oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
0326 
0327     /* We need tick count for calculation, not last tick. */
0328     ++tcnt;
0329 
0330     /* Check to see if we are changing the clock rate of the PWM. */
0331     if (chan->period_ns != period_ns || force_period) {
0332         unsigned long tin_rate;
0333         u32 period;
0334 
0335         period = NSEC_PER_SEC / period_ns;
0336 
0337         dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n",
0338                         duty_ns, period_ns, period);
0339 
0340         tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period);
0341 
0342         dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate);
0343 
0344         tin_ns = NSEC_PER_SEC / tin_rate;
0345         tcnt = period_ns / tin_ns;
0346     }
0347 
0348     /* Period is too short. */
0349     if (tcnt <= 1)
0350         return -ERANGE;
0351 
0352     /* Note that counters count down. */
0353     tcmp = duty_ns / tin_ns;
0354 
0355     /* 0% duty is not available */
0356     if (!tcmp)
0357         ++tcmp;
0358 
0359     tcmp = tcnt - tcmp;
0360 
0361     /* Decrement to get tick numbers, instead of tick counts. */
0362     --tcnt;
0363     /* -1UL will give 100% duty. */
0364     --tcmp;
0365 
0366     dev_dbg(our_chip->chip.dev,
0367                 "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
0368 
0369     /* Update PWM registers. */
0370     writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
0371     writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
0372 
0373     /*
0374      * In case the PWM is currently at 100% duty cycle, force a manual
0375      * update to prevent the signal staying high if the PWM is disabled
0376      * shortly afer this update (before it autoreloaded the new values).
0377      */
0378     if (oldtcmp == (u32) -1) {
0379         dev_dbg(our_chip->chip.dev, "Forcing manual update");
0380         pwm_samsung_manual_update(our_chip, pwm);
0381     }
0382 
0383     chan->period_ns = period_ns;
0384     chan->tin_ns = tin_ns;
0385     chan->duty_ns = duty_ns;
0386 
0387     return 0;
0388 }
0389 
0390 static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
0391                   int duty_ns, int period_ns)
0392 {
0393     return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false);
0394 }
0395 
0396 static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip,
0397                    unsigned int channel, bool invert)
0398 {
0399     unsigned int tcon_chan = to_tcon_channel(channel);
0400     unsigned long flags;
0401     u32 tcon;
0402 
0403     spin_lock_irqsave(&samsung_pwm_lock, flags);
0404 
0405     tcon = readl(chip->base + REG_TCON);
0406 
0407     if (invert) {
0408         chip->inverter_mask |= BIT(channel);
0409         tcon |= TCON_INVERT(tcon_chan);
0410     } else {
0411         chip->inverter_mask &= ~BIT(channel);
0412         tcon &= ~TCON_INVERT(tcon_chan);
0413     }
0414 
0415     writel(tcon, chip->base + REG_TCON);
0416 
0417     spin_unlock_irqrestore(&samsung_pwm_lock, flags);
0418 }
0419 
0420 static int pwm_samsung_set_polarity(struct pwm_chip *chip,
0421                     struct pwm_device *pwm,
0422                     enum pwm_polarity polarity)
0423 {
0424     struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
0425     bool invert = (polarity == PWM_POLARITY_NORMAL);
0426 
0427     /* Inverted means normal in the hardware. */
0428     pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert);
0429 
0430     return 0;
0431 }
0432 
0433 static int pwm_samsung_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0434                  const struct pwm_state *state)
0435 {
0436     int err, enabled = pwm->state.enabled;
0437 
0438     if (state->polarity != pwm->state.polarity) {
0439         if (enabled) {
0440             pwm_samsung_disable(chip, pwm);
0441             enabled = false;
0442         }
0443 
0444         err = pwm_samsung_set_polarity(chip, pwm, state->polarity);
0445         if (err)
0446             return err;
0447     }
0448 
0449     if (!state->enabled) {
0450         if (enabled)
0451             pwm_samsung_disable(chip, pwm);
0452 
0453         return 0;
0454     }
0455 
0456     /*
0457      * We currently avoid using 64bit arithmetic by using the
0458      * fact that anything faster than 1Hz is easily representable
0459      * by 32bits.
0460      */
0461     if (state->period > NSEC_PER_SEC)
0462         return -ERANGE;
0463 
0464     err = pwm_samsung_config(chip, pwm, state->duty_cycle, state->period);
0465     if (err)
0466         return err;
0467 
0468     if (!pwm->state.enabled)
0469         err = pwm_samsung_enable(chip, pwm);
0470 
0471     return err;
0472 }
0473 
0474 static const struct pwm_ops pwm_samsung_ops = {
0475     .request    = pwm_samsung_request,
0476     .free       = pwm_samsung_free,
0477     .apply      = pwm_samsung_apply,
0478     .owner      = THIS_MODULE,
0479 };
0480 
0481 #ifdef CONFIG_OF
0482 static const struct samsung_pwm_variant s3c24xx_variant = {
0483     .bits       = 16,
0484     .div_base   = 1,
0485     .has_tint_cstat = false,
0486     .tclk_mask  = BIT(4),
0487 };
0488 
0489 static const struct samsung_pwm_variant s3c64xx_variant = {
0490     .bits       = 32,
0491     .div_base   = 0,
0492     .has_tint_cstat = true,
0493     .tclk_mask  = BIT(7) | BIT(6) | BIT(5),
0494 };
0495 
0496 static const struct samsung_pwm_variant s5p64x0_variant = {
0497     .bits       = 32,
0498     .div_base   = 0,
0499     .has_tint_cstat = true,
0500     .tclk_mask  = 0,
0501 };
0502 
0503 static const struct samsung_pwm_variant s5pc100_variant = {
0504     .bits       = 32,
0505     .div_base   = 0,
0506     .has_tint_cstat = true,
0507     .tclk_mask  = BIT(5),
0508 };
0509 
0510 static const struct of_device_id samsung_pwm_matches[] = {
0511     { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant },
0512     { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant },
0513     { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant },
0514     { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant },
0515     { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant },
0516     {},
0517 };
0518 MODULE_DEVICE_TABLE(of, samsung_pwm_matches);
0519 
0520 static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
0521 {
0522     struct device_node *np = chip->chip.dev->of_node;
0523     const struct of_device_id *match;
0524     struct property *prop;
0525     const __be32 *cur;
0526     u32 val;
0527 
0528     match = of_match_node(samsung_pwm_matches, np);
0529     if (!match)
0530         return -ENODEV;
0531 
0532     memcpy(&chip->variant, match->data, sizeof(chip->variant));
0533 
0534     of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
0535         if (val >= SAMSUNG_PWM_NUM) {
0536             dev_err(chip->chip.dev,
0537                 "%s: invalid channel index in samsung,pwm-outputs property\n",
0538                                 __func__);
0539             continue;
0540         }
0541         chip->variant.output_mask |= BIT(val);
0542     }
0543 
0544     return 0;
0545 }
0546 #else
0547 static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
0548 {
0549     return -ENODEV;
0550 }
0551 #endif
0552 
0553 static int pwm_samsung_probe(struct platform_device *pdev)
0554 {
0555     struct device *dev = &pdev->dev;
0556     struct samsung_pwm_chip *chip;
0557     unsigned int chan;
0558     int ret;
0559 
0560     chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
0561     if (chip == NULL)
0562         return -ENOMEM;
0563 
0564     chip->chip.dev = &pdev->dev;
0565     chip->chip.ops = &pwm_samsung_ops;
0566     chip->chip.npwm = SAMSUNG_PWM_NUM;
0567     chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1;
0568 
0569     if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
0570         ret = pwm_samsung_parse_dt(chip);
0571         if (ret)
0572             return ret;
0573     } else {
0574         if (!pdev->dev.platform_data) {
0575             dev_err(&pdev->dev, "no platform data specified\n");
0576             return -EINVAL;
0577         }
0578 
0579         memcpy(&chip->variant, pdev->dev.platform_data,
0580                             sizeof(chip->variant));
0581     }
0582 
0583     chip->base = devm_platform_ioremap_resource(pdev, 0);
0584     if (IS_ERR(chip->base))
0585         return PTR_ERR(chip->base);
0586 
0587     chip->base_clk = devm_clk_get(&pdev->dev, "timers");
0588     if (IS_ERR(chip->base_clk)) {
0589         dev_err(dev, "failed to get timer base clk\n");
0590         return PTR_ERR(chip->base_clk);
0591     }
0592 
0593     ret = clk_prepare_enable(chip->base_clk);
0594     if (ret < 0) {
0595         dev_err(dev, "failed to enable base clock\n");
0596         return ret;
0597     }
0598 
0599     for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan)
0600         if (chip->variant.output_mask & BIT(chan))
0601             pwm_samsung_set_invert(chip, chan, true);
0602 
0603     /* Following clocks are optional. */
0604     chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0");
0605     chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1");
0606 
0607     platform_set_drvdata(pdev, chip);
0608 
0609     ret = pwmchip_add(&chip->chip);
0610     if (ret < 0) {
0611         dev_err(dev, "failed to register PWM chip\n");
0612         clk_disable_unprepare(chip->base_clk);
0613         return ret;
0614     }
0615 
0616     dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
0617         clk_get_rate(chip->base_clk),
0618         !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0,
0619         !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0);
0620 
0621     return 0;
0622 }
0623 
0624 static int pwm_samsung_remove(struct platform_device *pdev)
0625 {
0626     struct samsung_pwm_chip *chip = platform_get_drvdata(pdev);
0627 
0628     pwmchip_remove(&chip->chip);
0629 
0630     clk_disable_unprepare(chip->base_clk);
0631 
0632     return 0;
0633 }
0634 
0635 #ifdef CONFIG_PM_SLEEP
0636 static int pwm_samsung_resume(struct device *dev)
0637 {
0638     struct samsung_pwm_chip *our_chip = dev_get_drvdata(dev);
0639     struct pwm_chip *chip = &our_chip->chip;
0640     unsigned int i;
0641 
0642     for (i = 0; i < SAMSUNG_PWM_NUM; i++) {
0643         struct pwm_device *pwm = &chip->pwms[i];
0644         struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
0645 
0646         if (!chan)
0647             continue;
0648 
0649         if (our_chip->variant.output_mask & BIT(i))
0650             pwm_samsung_set_invert(our_chip, i,
0651                     our_chip->inverter_mask & BIT(i));
0652 
0653         if (chan->period_ns) {
0654             __pwm_samsung_config(chip, pwm, chan->duty_ns,
0655                          chan->period_ns, true);
0656             /* needed to make PWM disable work on Odroid-XU3 */
0657             pwm_samsung_manual_update(our_chip, pwm);
0658         }
0659 
0660         if (our_chip->disabled_mask & BIT(i))
0661             pwm_samsung_disable(chip, pwm);
0662         else
0663             pwm_samsung_enable(chip, pwm);
0664     }
0665 
0666     return 0;
0667 }
0668 #endif
0669 
0670 static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume);
0671 
0672 static struct platform_driver pwm_samsung_driver = {
0673     .driver     = {
0674         .name   = "samsung-pwm",
0675         .pm = &pwm_samsung_pm_ops,
0676         .of_match_table = of_match_ptr(samsung_pwm_matches),
0677     },
0678     .probe      = pwm_samsung_probe,
0679     .remove     = pwm_samsung_remove,
0680 };
0681 module_platform_driver(pwm_samsung_driver);
0682 
0683 MODULE_LICENSE("GPL");
0684 MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
0685 MODULE_ALIAS("platform:samsung-pwm");
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