drivers/pwm/pwm-rockchip.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * PWM driver for Rockchip SoCs
0004  *
0005  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
0006  * Copyright (C) 2014 ROCKCHIP, Inc.
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pwm.h>
0016 #include <linux/time.h>
0017
0018 #define PWM_CTRL_TIMER_EN   (1 << 0)
0019 #define PWM_CTRL_OUTPUT_EN  (1 << 3)
0020
0021 #define PWM_ENABLE      (1 << 0)
0022 #define PWM_CONTINUOUS      (1 << 1)
0023 #define PWM_DUTY_POSITIVE   (1 << 3)
0024 #define PWM_DUTY_NEGATIVE   (0 << 3)
0025 #define PWM_INACTIVE_NEGATIVE   (0 << 4)
0026 #define PWM_INACTIVE_POSITIVE   (1 << 4)
0027 #define PWM_POLARITY_MASK   (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
0028 #define PWM_OUTPUT_LEFT     (0 << 5)
0029 #define PWM_LOCK_EN     (1 << 6)
0030 #define PWM_LP_DISABLE      (0 << 8)
0031
0032 struct rockchip_pwm_chip {
0033     struct pwm_chip chip;
0034     struct clk *clk;
0035     struct clk *pclk;
0036     const struct rockchip_pwm_data *data;
0037     void __iomem *base;
0038 };
0039
0040 struct rockchip_pwm_regs {
0041     unsigned long duty;
0042     unsigned long period;
0043     unsigned long cntr;
0044     unsigned long ctrl;
0045 };
0046
0047 struct rockchip_pwm_data {
0048     struct rockchip_pwm_regs regs;
0049     unsigned int prescaler;
0050     bool supports_polarity;
0051     bool supports_lock;
0052     u32 enable_conf;
0053 };
0054
0055 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
0056 {
0057     return container_of(c, struct rockchip_pwm_chip, chip);
0058 }
0059
0060 static void rockchip_pwm_get_state(struct pwm_chip *chip,
0061                    struct pwm_device *pwm,
0062                    struct pwm_state *state)
0063 {
0064     struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
0065     u32 enable_conf = pc->data->enable_conf;
0066     unsigned long clk_rate;
0067     u64 tmp;
0068     u32 val;
0069     int ret;
0070
0071     ret = clk_enable(pc->pclk);
0072     if (ret)
0073         return;
0074
0075     ret = clk_enable(pc->clk);
0076     if (ret)
0077         return;
0078
0079     clk_rate = clk_get_rate(pc->clk);
0080
0081     tmp = readl_relaxed(pc->base + pc->data->regs.period);
0082     tmp *= pc->data->prescaler * NSEC_PER_SEC;
0083     state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
0084
0085     tmp = readl_relaxed(pc->base + pc->data->regs.duty);
0086     tmp *= pc->data->prescaler * NSEC_PER_SEC;
0087     state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
0088
0089     val = readl_relaxed(pc->base + pc->data->regs.ctrl);
0090     state->enabled = (val & enable_conf) == enable_conf;
0091
0092     if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
0093         state->polarity = PWM_POLARITY_INVERSED;
0094     else
0095         state->polarity = PWM_POLARITY_NORMAL;
0096
0097     clk_disable(pc->clk);
0098     clk_disable(pc->pclk);
0099 }
0100
0101 static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
0102                    const struct pwm_state *state)
0103 {
0104     struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
0105     unsigned long period, duty;
0106     u64 clk_rate, div;
0107     u32 ctrl;
0108
0109     clk_rate = clk_get_rate(pc->clk);
0110
0111     /*
0112      * Since period and duty cycle registers have a width of 32
0113      * bits, every possible input period can be obtained using the
0114      * default prescaler value for all practical clock rate values.
0115      */
0116     div = clk_rate * state->period;
0117     period = DIV_ROUND_CLOSEST_ULL(div,
0118                        pc->data->prescaler * NSEC_PER_SEC);
0119
0120     div = clk_rate * state->duty_cycle;
0121     duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
0122
0123     /*
0124      * Lock the period and duty of previous configuration, then
0125      * change the duty and period, that would not be effective.
0126      */
0127     ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
0128     if (pc->data->supports_lock) {
0129         ctrl |= PWM_LOCK_EN;
0130         writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
0131     }
0132
0133     writel(period, pc->base + pc->data->regs.period);
0134     writel(duty, pc->base + pc->data->regs.duty);
0135
0136     if (pc->data->supports_polarity) {
0137         ctrl &= ~PWM_POLARITY_MASK;
0138         if (state->polarity == PWM_POLARITY_INVERSED)
0139             ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
0140         else
0141             ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
0142     }
0143
0144     /*
0145      * Unlock and set polarity at the same time,
0146      * the configuration of duty, period and polarity
0147      * would be effective together at next period.
0148      */
0149     if (pc->data->supports_lock)
0150         ctrl &= ~PWM_LOCK_EN;
0151
0152     writel(ctrl, pc->base + pc->data->regs.ctrl);
0153 }
0154
0155 static int rockchip_pwm_enable(struct pwm_chip *chip,
0156                    struct pwm_device *pwm,
0157                    bool enable)
0158 {
0159     struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
0160     u32 enable_conf = pc->data->enable_conf;
0161     int ret;
0162     u32 val;
0163
0164     if (enable) {
0165         ret = clk_enable(pc->clk);
0166         if (ret)
0167             return ret;
0168     }
0169
0170     val = readl_relaxed(pc->base + pc->data->regs.ctrl);
0171
0172     if (enable)
0173         val |= enable_conf;
0174     else
0175         val &= ~enable_conf;
0176
0177     writel_relaxed(val, pc->base + pc->data->regs.ctrl);
0178
0179     if (!enable)
0180         clk_disable(pc->clk);
0181
0182     return 0;
0183 }
0184
0185 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0186                   const struct pwm_state *state)
0187 {
0188     struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
0189     struct pwm_state curstate;
0190     bool enabled;
0191     int ret = 0;
0192
0193     ret = clk_enable(pc->pclk);
0194     if (ret)
0195         return ret;
0196
0197     ret = clk_enable(pc->clk);
0198     if (ret)
0199         return ret;
0200
0201     pwm_get_state(pwm, &curstate);
0202     enabled = curstate.enabled;
0203
0204     if (state->polarity != curstate.polarity && enabled &&
0205         !pc->data->supports_lock) {
0206         ret = rockchip_pwm_enable(chip, pwm, false);
0207         if (ret)
0208             goto out;
0209         enabled = false;
0210     }
0211
0212     rockchip_pwm_config(chip, pwm, state);
0213     if (state->enabled != enabled) {
0214         ret = rockchip_pwm_enable(chip, pwm, state->enabled);
0215         if (ret)
0216             goto out;
0217     }
0218
0219 out:
0220     clk_disable(pc->clk);
0221     clk_disable(pc->pclk);
0222
0223     return ret;
0224 }
0225
0226 static const struct pwm_ops rockchip_pwm_ops = {
0227     .get_state = rockchip_pwm_get_state,
0228     .apply = rockchip_pwm_apply,
0229     .owner = THIS_MODULE,
0230 };
0231
0232 static const struct rockchip_pwm_data pwm_data_v1 = {
0233     .regs = {
0234         .duty = 0x04,
0235         .period = 0x08,
0236         .cntr = 0x00,
0237         .ctrl = 0x0c,
0238     },
0239     .prescaler = 2,
0240     .supports_polarity = false,
0241     .supports_lock = false,
0242     .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
0243 };
0244
0245 static const struct rockchip_pwm_data pwm_data_v2 = {
0246     .regs = {
0247         .duty = 0x08,
0248         .period = 0x04,
0249         .cntr = 0x00,
0250         .ctrl = 0x0c,
0251     },
0252     .prescaler = 1,
0253     .supports_polarity = true,
0254     .supports_lock = false,
0255     .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
0256                PWM_CONTINUOUS,
0257 };
0258
0259 static const struct rockchip_pwm_data pwm_data_vop = {
0260     .regs = {
0261         .duty = 0x08,
0262         .period = 0x04,
0263         .cntr = 0x0c,
0264         .ctrl = 0x00,
0265     },
0266     .prescaler = 1,
0267     .supports_polarity = true,
0268     .supports_lock = false,
0269     .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
0270                PWM_CONTINUOUS,
0271 };
0272
0273 static const struct rockchip_pwm_data pwm_data_v3 = {
0274     .regs = {
0275         .duty = 0x08,
0276         .period = 0x04,
0277         .cntr = 0x00,
0278         .ctrl = 0x0c,
0279     },
0280     .prescaler = 1,
0281     .supports_polarity = true,
0282     .supports_lock = true,
0283     .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
0284                PWM_CONTINUOUS,
0285 };
0286
0287 static const struct of_device_id rockchip_pwm_dt_ids[] = {
0288     { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
0289     { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
0290     { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
0291     { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
0292     { /* sentinel */ }
0293 };
0294 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
0295
0296 static int rockchip_pwm_probe(struct platform_device *pdev)
0297 {
0298     const struct of_device_id *id;
0299     struct rockchip_pwm_chip *pc;
0300     u32 enable_conf, ctrl;
0301     bool enabled;
0302     int ret, count;
0303
0304     id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
0305     if (!id)
0306         return -EINVAL;
0307
0308     pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
0309     if (!pc)
0310         return -ENOMEM;
0311
0312     pc->base = devm_platform_ioremap_resource(pdev, 0);
0313     if (IS_ERR(pc->base))
0314         return PTR_ERR(pc->base);
0315
0316     pc->clk = devm_clk_get(&pdev->dev, "pwm");
0317     if (IS_ERR(pc->clk)) {
0318         pc->clk = devm_clk_get(&pdev->dev, NULL);
0319         if (IS_ERR(pc->clk))
0320             return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
0321                          "Can't get PWM clk\n");
0322     }
0323
0324     count = of_count_phandle_with_args(pdev->dev.of_node,
0325                        "clocks", "#clock-cells");
0326     if (count == 2)
0327         pc->pclk = devm_clk_get(&pdev->dev, "pclk");
0328     else
0329         pc->pclk = pc->clk;
0330
0331     if (IS_ERR(pc->pclk)) {
0332         ret = PTR_ERR(pc->pclk);
0333         if (ret != -EPROBE_DEFER)
0334             dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
0335         return ret;
0336     }
0337
0338     ret = clk_prepare_enable(pc->clk);
0339     if (ret) {
0340         dev_err(&pdev->dev, "Can't prepare enable PWM clk: %d\n", ret);
0341         return ret;
0342     }
0343
0344     ret = clk_prepare_enable(pc->pclk);
0345     if (ret) {
0346         dev_err(&pdev->dev, "Can't prepare enable APB clk: %d\n", ret);
0347         goto err_clk;
0348     }
0349
0350     platform_set_drvdata(pdev, pc);
0351
0352     pc->data = id->data;
0353     pc->chip.dev = &pdev->dev;
0354     pc->chip.ops = &rockchip_pwm_ops;
0355     pc->chip.npwm = 1;
0356
0357     enable_conf = pc->data->enable_conf;
0358     ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
0359     enabled = (ctrl & enable_conf) == enable_conf;
0360
0361     ret = pwmchip_add(&pc->chip);
0362     if (ret < 0) {
0363         dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
0364         goto err_pclk;
0365     }
0366
0367     /* Keep the PWM clk enabled if the PWM appears to be up and running. */
0368     if (!enabled)
0369         clk_disable(pc->clk);
0370
0371     clk_disable(pc->pclk);
0372
0373     return 0;
0374
0375 err_pclk:
0376     clk_disable_unprepare(pc->pclk);
0377 err_clk:
0378     clk_disable_unprepare(pc->clk);
0379
0380     return ret;
0381 }
0382
0383 static int rockchip_pwm_remove(struct platform_device *pdev)
0384 {
0385     struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
0386
0387     pwmchip_remove(&pc->chip);
0388
0389     clk_unprepare(pc->pclk);
0390     clk_unprepare(pc->clk);
0391
0392     return 0;
0393 }
0394
0395 static struct platform_driver rockchip_pwm_driver = {
0396     .driver = {
0397         .name = "rockchip-pwm",
0398         .of_match_table = rockchip_pwm_dt_ids,
0399     },
0400     .probe = rockchip_pwm_probe,
0401     .remove = rockchip_pwm_remove,
0402 };
0403 module_platform_driver(rockchip_pwm_driver);
0404
0405 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
0406 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
0407 MODULE_LICENSE("GPL v2");