drivers/pwm/pwm-renesas-tpu.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R-Mobile TPU PWM driver
0004  *
0005  * Copyright (C) 2012 Renesas Solutions Corp.
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/init.h>
0012 #include <linux/ioport.h>
0013 #include <linux/module.h>
0014 #include <linux/mutex.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/pwm.h>
0019 #include <linux/slab.h>
0020 #include <linux/spinlock.h>
0021
0022 #define TPU_CHANNEL_MAX     4
0023
0024 #define TPU_TSTR        0x00    /* Timer start register (shared) */
0025
0026 #define TPU_TCRn        0x00    /* Timer control register */
0027 #define TPU_TCR_CCLR_NONE   (0 << 5)
0028 #define TPU_TCR_CCLR_TGRA   (1 << 5)
0029 #define TPU_TCR_CCLR_TGRB   (2 << 5)
0030 #define TPU_TCR_CCLR_TGRC   (5 << 5)
0031 #define TPU_TCR_CCLR_TGRD   (6 << 5)
0032 #define TPU_TCR_CKEG_RISING (0 << 3)
0033 #define TPU_TCR_CKEG_FALLING    (1 << 3)
0034 #define TPU_TCR_CKEG_BOTH   (2 << 3)
0035 #define TPU_TMDRn       0x04    /* Timer mode register */
0036 #define TPU_TMDR_BFWT       (1 << 6)
0037 #define TPU_TMDR_BFB        (1 << 5)
0038 #define TPU_TMDR_BFA        (1 << 4)
0039 #define TPU_TMDR_MD_NORMAL  (0 << 0)
0040 #define TPU_TMDR_MD_PWM     (2 << 0)
0041 #define TPU_TIORn       0x08    /* Timer I/O control register */
0042 #define TPU_TIOR_IOA_0      (0 << 0)
0043 #define TPU_TIOR_IOA_0_CLR  (1 << 0)
0044 #define TPU_TIOR_IOA_0_SET  (2 << 0)
0045 #define TPU_TIOR_IOA_0_TOGGLE   (3 << 0)
0046 #define TPU_TIOR_IOA_1      (4 << 0)
0047 #define TPU_TIOR_IOA_1_CLR  (5 << 0)
0048 #define TPU_TIOR_IOA_1_SET  (6 << 0)
0049 #define TPU_TIOR_IOA_1_TOGGLE   (7 << 0)
0050 #define TPU_TIERn       0x0c    /* Timer interrupt enable register */
0051 #define TPU_TSRn        0x10    /* Timer status register */
0052 #define TPU_TCNTn       0x14    /* Timer counter */
0053 #define TPU_TGRAn       0x18    /* Timer general register A */
0054 #define TPU_TGRBn       0x1c    /* Timer general register B */
0055 #define TPU_TGRCn       0x20    /* Timer general register C */
0056 #define TPU_TGRDn       0x24    /* Timer general register D */
0057
0058 #define TPU_CHANNEL_OFFSET  0x10
0059 #define TPU_CHANNEL_SIZE    0x40
0060
0061 enum tpu_pin_state {
0062     TPU_PIN_INACTIVE,       /* Pin is driven inactive */
0063     TPU_PIN_PWM,            /* Pin is driven by PWM */
0064     TPU_PIN_ACTIVE,         /* Pin is driven active */
0065 };
0066
0067 struct tpu_device;
0068
0069 struct tpu_pwm_device {
0070     bool timer_on;          /* Whether the timer is running */
0071
0072     struct tpu_device *tpu;
0073     unsigned int channel;       /* Channel number in the TPU */
0074
0075     enum pwm_polarity polarity;
0076     unsigned int prescaler;
0077     u16 period;
0078     u16 duty;
0079 };
0080
0081 struct tpu_device {
0082     struct platform_device *pdev;
0083     struct pwm_chip chip;
0084     spinlock_t lock;
0085
0086     void __iomem *base;
0087     struct clk *clk;
0088 };
0089
0090 #define to_tpu_device(c)    container_of(c, struct tpu_device, chip)
0091
0092 static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value)
0093 {
0094     void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET
0095                + tpd->channel * TPU_CHANNEL_SIZE;
0096
0097     iowrite16(value, base + reg_nr);
0098 }
0099
0100 static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd,
0101                 enum tpu_pin_state state)
0102 {
0103     static const char * const states[] = { "inactive", "PWM", "active" };
0104
0105     dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",
0106         tpd->channel, states[state]);
0107
0108     switch (state) {
0109     case TPU_PIN_INACTIVE:
0110         tpu_pwm_write(tpd, TPU_TIORn,
0111                   tpd->polarity == PWM_POLARITY_INVERSED ?
0112                   TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
0113         break;
0114     case TPU_PIN_PWM:
0115         tpu_pwm_write(tpd, TPU_TIORn,
0116                   tpd->polarity == PWM_POLARITY_INVERSED ?
0117                   TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
0118         break;
0119     case TPU_PIN_ACTIVE:
0120         tpu_pwm_write(tpd, TPU_TIORn,
0121                   tpd->polarity == PWM_POLARITY_INVERSED ?
0122                   TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
0123         break;
0124     }
0125 }
0126
0127 static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start)
0128 {
0129     unsigned long flags;
0130     u16 value;
0131
0132     spin_lock_irqsave(&tpd->tpu->lock, flags);
0133     value = ioread16(tpd->tpu->base + TPU_TSTR);
0134
0135     if (start)
0136         value |= 1 << tpd->channel;
0137     else
0138         value &= ~(1 << tpd->channel);
0139
0140     iowrite16(value, tpd->tpu->base + TPU_TSTR);
0141     spin_unlock_irqrestore(&tpd->tpu->lock, flags);
0142 }
0143
0144 static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd)
0145 {
0146     int ret;
0147
0148     if (!tpd->timer_on) {
0149         /* Wake up device and enable clock. */
0150         pm_runtime_get_sync(&tpd->tpu->pdev->dev);
0151         ret = clk_prepare_enable(tpd->tpu->clk);
0152         if (ret) {
0153             dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");
0154             return ret;
0155         }
0156         tpd->timer_on = true;
0157     }
0158
0159     /*
0160      * Make sure the channel is stopped, as we need to reconfigure it
0161      * completely. First drive the pin to the inactive state to avoid
0162      * glitches.
0163      */
0164     tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
0165     tpu_pwm_start_stop(tpd, false);
0166
0167     /*
0168      * - Clear TCNT on TGRB match
0169      * - Count on rising edge
0170      * - Set prescaler
0171      * - Output 0 until TGRA, output 1 until TGRB (active low polarity)
0172      * - Output 1 until TGRA, output 0 until TGRB (active high polarity
0173      * - PWM mode
0174      */
0175     tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
0176               tpd->prescaler);
0177     tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM);
0178     tpu_pwm_set_pin(tpd, TPU_PIN_PWM);
0179     tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
0180     tpu_pwm_write(tpd, TPU_TGRBn, tpd->period);
0181
0182     dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
0183         tpd->channel, tpd->duty, tpd->period);
0184
0185     /* Start the channel. */
0186     tpu_pwm_start_stop(tpd, true);
0187
0188     return 0;
0189 }
0190
0191 static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd)
0192 {
0193     if (!tpd->timer_on)
0194         return;
0195
0196     /* Disable channel. */
0197     tpu_pwm_start_stop(tpd, false);
0198
0199     /* Stop clock and mark device as idle. */
0200     clk_disable_unprepare(tpd->tpu->clk);
0201     pm_runtime_put(&tpd->tpu->pdev->dev);
0202
0203     tpd->timer_on = false;
0204 }
0205
0206 /* -----------------------------------------------------------------------------
0207  * PWM API
0208  */
0209
0210 static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
0211 {
0212     struct tpu_device *tpu = to_tpu_device(chip);
0213     struct tpu_pwm_device *tpd;
0214
0215     if (pwm->hwpwm >= TPU_CHANNEL_MAX)
0216         return -EINVAL;
0217
0218     tpd = kzalloc(sizeof(*tpd), GFP_KERNEL);
0219     if (tpd == NULL)
0220         return -ENOMEM;
0221
0222     tpd->tpu = tpu;
0223     tpd->channel = pwm->hwpwm;
0224     tpd->polarity = PWM_POLARITY_NORMAL;
0225     tpd->prescaler = 0;
0226     tpd->period = 0;
0227     tpd->duty = 0;
0228
0229     tpd->timer_on = false;
0230
0231     pwm_set_chip_data(pwm, tpd);
0232
0233     return 0;
0234 }
0235
0236 static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
0237 {
0238     struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
0239
0240     tpu_pwm_timer_stop(tpd);
0241     kfree(tpd);
0242 }
0243
0244 static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
0245               u64 duty_ns, u64 period_ns, bool enabled)
0246 {
0247     struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
0248     struct tpu_device *tpu = to_tpu_device(chip);
0249     unsigned int prescaler;
0250     bool duty_only = false;
0251     u32 clk_rate;
0252     u64 period;
0253     u32 duty;
0254     int ret;
0255
0256     clk_rate = clk_get_rate(tpu->clk);
0257     if (unlikely(clk_rate > NSEC_PER_SEC)) {
0258         /*
0259          * This won't happen in the nearer future, so this is only a
0260          * safeguard to prevent the following calculation from
0261          * overflowing. With this clk_rate * period_ns / NSEC_PER_SEC is
0262          * not greater than period_ns and so fits into an u64.
0263          */
0264         return -EINVAL;
0265     }
0266
0267     period = mul_u64_u64_div_u64(clk_rate, period_ns, NSEC_PER_SEC);
0268
0269     /*
0270      * Find the minimal prescaler in [0..3] such that
0271      *
0272      *     period >> (2 * prescaler) < 0x10000
0273      *
0274      * This could be calculated using something like:
0275      *
0276      *     prescaler = max(ilog2(period) / 2, 7) - 7;
0277      *
0278      * but given there are only four allowed results and that ilog2 isn't
0279      * cheap on all platforms using a switch statement is more effective.
0280      */
0281     switch (period) {
0282     case 1 ... 0xffff:
0283         prescaler = 0;
0284         break;
0285
0286     case 0x10000 ... 0x3ffff:
0287         prescaler = 1;
0288         break;
0289
0290     case 0x40000 ... 0xfffff:
0291         prescaler = 2;
0292         break;
0293
0294     case 0x100000 ... 0x3fffff:
0295         prescaler = 3;
0296         break;
0297
0298     default:
0299         return -EINVAL;
0300     }
0301
0302     period >>= 2 * prescaler;
0303
0304     if (duty_ns)
0305         duty = mul_u64_u64_div_u64(clk_rate, duty_ns,
0306                        (u64)NSEC_PER_SEC << (2 * prescaler));
0307     else
0308         duty = 0;
0309
0310     dev_dbg(&tpu->pdev->dev,
0311         "rate %u, prescaler %u, period %u, duty %u\n",
0312         clk_rate, 1 << (2 * prescaler), (u32)period, duty);
0313
0314     if (tpd->prescaler == prescaler && tpd->period == period)
0315         duty_only = true;
0316
0317     tpd->prescaler = prescaler;
0318     tpd->period = period;
0319     tpd->duty = duty;
0320
0321     /* If the channel is disabled we're done. */
0322     if (!enabled)
0323         return 0;
0324
0325     if (duty_only && tpd->timer_on) {
0326         /*
0327          * If only the duty cycle changed and the timer is already
0328          * running, there's no need to reconfigure it completely, Just
0329          * modify the duty cycle.
0330          */
0331         tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
0332         dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,
0333             tpd->duty);
0334     } else {
0335         /* Otherwise perform a full reconfiguration. */
0336         ret = tpu_pwm_timer_start(tpd);
0337         if (ret < 0)
0338             return ret;
0339     }
0340
0341     if (duty == 0 || duty == period) {
0342         /*
0343          * To avoid running the timer when not strictly required, handle
0344          * 0% and 100% duty cycles as fixed levels and stop the timer.
0345          */
0346         tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
0347         tpu_pwm_timer_stop(tpd);
0348     }
0349
0350     return 0;
0351 }
0352
0353 static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
0354                 enum pwm_polarity polarity)
0355 {
0356     struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
0357
0358     tpd->polarity = polarity;
0359
0360     return 0;
0361 }
0362
0363 static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
0364 {
0365     struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
0366     int ret;
0367
0368     ret = tpu_pwm_timer_start(tpd);
0369     if (ret < 0)
0370         return ret;
0371
0372     /*
0373      * To avoid running the timer when not strictly required, handle 0% and
0374      * 100% duty cycles as fixed levels and stop the timer.
0375      */
0376     if (tpd->duty == 0 || tpd->duty == tpd->period) {
0377         tpu_pwm_set_pin(tpd, tpd->duty ?
0378                 TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
0379         tpu_pwm_timer_stop(tpd);
0380     }
0381
0382     return 0;
0383 }
0384
0385 static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
0386 {
0387     struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
0388
0389     /* The timer must be running to modify the pin output configuration. */
0390     tpu_pwm_timer_start(tpd);
0391     tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
0392     tpu_pwm_timer_stop(tpd);
0393 }
0394
0395 static int tpu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0396              const struct pwm_state *state)
0397 {
0398     int err;
0399     bool enabled = pwm->state.enabled;
0400
0401     if (state->polarity != pwm->state.polarity) {
0402         if (enabled) {
0403             tpu_pwm_disable(chip, pwm);
0404             enabled = false;
0405         }
0406
0407         err = tpu_pwm_set_polarity(chip, pwm, state->polarity);
0408         if (err)
0409             return err;
0410     }
0411
0412     if (!state->enabled) {
0413         if (enabled)
0414             tpu_pwm_disable(chip, pwm);
0415
0416         return 0;
0417     }
0418
0419     err = tpu_pwm_config(pwm->chip, pwm,
0420                  state->duty_cycle, state->period, enabled);
0421     if (err)
0422         return err;
0423
0424     if (!enabled)
0425         err = tpu_pwm_enable(chip, pwm);
0426
0427     return err;
0428 }
0429
0430 static const struct pwm_ops tpu_pwm_ops = {
0431     .request = tpu_pwm_request,
0432     .free = tpu_pwm_free,
0433     .apply = tpu_pwm_apply,
0434     .owner = THIS_MODULE,
0435 };
0436
0437 /* -----------------------------------------------------------------------------
0438  * Probe and remove
0439  */
0440
0441 static int tpu_probe(struct platform_device *pdev)
0442 {
0443     struct tpu_device *tpu;
0444     int ret;
0445
0446     tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
0447     if (tpu == NULL)
0448         return -ENOMEM;
0449
0450     spin_lock_init(&tpu->lock);
0451     tpu->pdev = pdev;
0452
0453     /* Map memory, get clock and pin control. */
0454     tpu->base = devm_platform_ioremap_resource(pdev, 0);
0455     if (IS_ERR(tpu->base))
0456         return PTR_ERR(tpu->base);
0457
0458     tpu->clk = devm_clk_get(&pdev->dev, NULL);
0459     if (IS_ERR(tpu->clk))
0460         return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n");
0461
0462     /* Initialize and register the device. */
0463     platform_set_drvdata(pdev, tpu);
0464
0465     tpu->chip.dev = &pdev->dev;
0466     tpu->chip.ops = &tpu_pwm_ops;
0467     tpu->chip.npwm = TPU_CHANNEL_MAX;
0468
0469     ret = devm_pm_runtime_enable(&pdev->dev);
0470     if (ret < 0)
0471         return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n");
0472
0473     ret = devm_pwmchip_add(&pdev->dev, &tpu->chip);
0474     if (ret < 0)
0475         return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n");
0476
0477     return 0;
0478 }
0479
0480 #ifdef CONFIG_OF
0481 static const struct of_device_id tpu_of_table[] = {
0482     { .compatible = "renesas,tpu-r8a73a4", },
0483     { .compatible = "renesas,tpu-r8a7740", },
0484     { .compatible = "renesas,tpu-r8a7790", },
0485     { .compatible = "renesas,tpu", },
0486     { },
0487 };
0488
0489 MODULE_DEVICE_TABLE(of, tpu_of_table);
0490 #endif
0491
0492 static struct platform_driver tpu_driver = {
0493     .probe      = tpu_probe,
0494     .driver     = {
0495         .name   = "renesas-tpu-pwm",
0496         .of_match_table = of_match_ptr(tpu_of_table),
0497     }
0498 };
0499
0500 module_platform_driver(tpu_driver);
0501
0502 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
0503 MODULE_DESCRIPTION("Renesas TPU PWM Driver");
0504 MODULE_LICENSE("GPL v2");
0505 MODULE_ALIAS("platform:renesas-tpu-pwm");