drivers/pwm/pwm-rcar.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R-Car PWM Timer driver
0004  *
0005  * Copyright (C) 2015 Renesas Electronics Corporation
0006  *
0007  * Limitations:
0008  * - The hardware cannot generate a 0% duty cycle.
0009  */
0010
0011 #include <linux/clk.h>
0012 #include <linux/err.h>
0013 #include <linux/io.h>
0014 #include <linux/log2.h>
0015 #include <linux/math64.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/pm_runtime.h>
0020 #include <linux/pwm.h>
0021 #include <linux/slab.h>
0022
0023 #define RCAR_PWM_MAX_DIVISION   24
0024 #define RCAR_PWM_MAX_CYCLE  1023
0025
0026 #define RCAR_PWMCR      0x00
0027 #define  RCAR_PWMCR_CC0_MASK    0x000f0000
0028 #define  RCAR_PWMCR_CC0_SHIFT   16
0029 #define  RCAR_PWMCR_CCMD    BIT(15)
0030 #define  RCAR_PWMCR_SYNC    BIT(11)
0031 #define  RCAR_PWMCR_SS0     BIT(4)
0032 #define  RCAR_PWMCR_EN0     BIT(0)
0033
0034 #define RCAR_PWMCNT     0x04
0035 #define  RCAR_PWMCNT_CYC0_MASK  0x03ff0000
0036 #define  RCAR_PWMCNT_CYC0_SHIFT 16
0037 #define  RCAR_PWMCNT_PH0_MASK   0x000003ff
0038 #define  RCAR_PWMCNT_PH0_SHIFT  0
0039
0040 struct rcar_pwm_chip {
0041     struct pwm_chip chip;
0042     void __iomem *base;
0043     struct clk *clk;
0044 };
0045
0046 static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
0047 {
0048     return container_of(chip, struct rcar_pwm_chip, chip);
0049 }
0050
0051 static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
0052                unsigned int offset)
0053 {
0054     writel(data, rp->base + offset);
0055 }
0056
0057 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
0058 {
0059     return readl(rp->base + offset);
0060 }
0061
0062 static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
0063                 unsigned int offset)
0064 {
0065     u32 value;
0066
0067     value = rcar_pwm_read(rp, offset);
0068     value &= ~mask;
0069     value |= data & mask;
0070     rcar_pwm_write(rp, value, offset);
0071 }
0072
0073 static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
0074 {
0075     unsigned long clk_rate = clk_get_rate(rp->clk);
0076     u64 div, tmp;
0077
0078     if (clk_rate == 0)
0079         return -EINVAL;
0080
0081     div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
0082     tmp = (u64)period_ns * clk_rate + div - 1;
0083     tmp = div64_u64(tmp, div);
0084     div = ilog2(tmp - 1) + 1;
0085
0086     return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
0087 }
0088
0089 static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
0090                        unsigned int div)
0091 {
0092     u32 value;
0093
0094     value = rcar_pwm_read(rp, RCAR_PWMCR);
0095     value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
0096
0097     if (div & 1)
0098         value |= RCAR_PWMCR_CCMD;
0099
0100     div >>= 1;
0101
0102     value |= div << RCAR_PWMCR_CC0_SHIFT;
0103     rcar_pwm_write(rp, value, RCAR_PWMCR);
0104 }
0105
0106 static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
0107                 int period_ns)
0108 {
0109     unsigned long long one_cycle, tmp;  /* 0.01 nanoseconds */
0110     unsigned long clk_rate = clk_get_rate(rp->clk);
0111     u32 cyc, ph;
0112
0113     one_cycle = NSEC_PER_SEC * 100ULL << div;
0114     do_div(one_cycle, clk_rate);
0115
0116     tmp = period_ns * 100ULL;
0117     do_div(tmp, one_cycle);
0118     cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
0119
0120     tmp = duty_ns * 100ULL;
0121     do_div(tmp, one_cycle);
0122     ph = tmp & RCAR_PWMCNT_PH0_MASK;
0123
0124     /* Avoid prohibited setting */
0125     if (cyc == 0 || ph == 0)
0126         return -EINVAL;
0127
0128     rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
0129
0130     return 0;
0131 }
0132
0133 static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
0134 {
0135     return pm_runtime_get_sync(chip->dev);
0136 }
0137
0138 static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
0139 {
0140     pm_runtime_put(chip->dev);
0141 }
0142
0143 static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
0144 {
0145     u32 value;
0146
0147     /* Don't enable the PWM device if CYC0 or PH0 is 0 */
0148     value = rcar_pwm_read(rp, RCAR_PWMCNT);
0149     if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
0150         (value & RCAR_PWMCNT_PH0_MASK) == 0)
0151         return -EINVAL;
0152
0153     rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
0154
0155     return 0;
0156 }
0157
0158 static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
0159 {
0160     rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
0161 }
0162
0163 static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0164               const struct pwm_state *state)
0165 {
0166     struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
0167     int div, ret;
0168
0169     /* This HW/driver only supports normal polarity */
0170     if (state->polarity != PWM_POLARITY_NORMAL)
0171         return -EINVAL;
0172
0173     if (!state->enabled) {
0174         rcar_pwm_disable(rp);
0175         return 0;
0176     }
0177
0178     div = rcar_pwm_get_clock_division(rp, state->period);
0179     if (div < 0)
0180         return div;
0181
0182     rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
0183
0184     ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
0185     if (!ret)
0186         rcar_pwm_set_clock_control(rp, div);
0187
0188     /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
0189     rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
0190
0191     if (!ret)
0192         ret = rcar_pwm_enable(rp);
0193
0194     return ret;
0195 }
0196
0197 static const struct pwm_ops rcar_pwm_ops = {
0198     .request = rcar_pwm_request,
0199     .free = rcar_pwm_free,
0200     .apply = rcar_pwm_apply,
0201     .owner = THIS_MODULE,
0202 };
0203
0204 static int rcar_pwm_probe(struct platform_device *pdev)
0205 {
0206     struct rcar_pwm_chip *rcar_pwm;
0207     int ret;
0208
0209     rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
0210     if (rcar_pwm == NULL)
0211         return -ENOMEM;
0212
0213     rcar_pwm->base = devm_platform_ioremap_resource(pdev, 0);
0214     if (IS_ERR(rcar_pwm->base))
0215         return PTR_ERR(rcar_pwm->base);
0216
0217     rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
0218     if (IS_ERR(rcar_pwm->clk)) {
0219         dev_err(&pdev->dev, "cannot get clock\n");
0220         return PTR_ERR(rcar_pwm->clk);
0221     }
0222
0223     platform_set_drvdata(pdev, rcar_pwm);
0224
0225     rcar_pwm->chip.dev = &pdev->dev;
0226     rcar_pwm->chip.ops = &rcar_pwm_ops;
0227     rcar_pwm->chip.npwm = 1;
0228
0229     pm_runtime_enable(&pdev->dev);
0230
0231     ret = pwmchip_add(&rcar_pwm->chip);
0232     if (ret < 0) {
0233         dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
0234         pm_runtime_disable(&pdev->dev);
0235         return ret;
0236     }
0237
0238     return 0;
0239 }
0240
0241 static int rcar_pwm_remove(struct platform_device *pdev)
0242 {
0243     struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
0244
0245     pwmchip_remove(&rcar_pwm->chip);
0246
0247     pm_runtime_disable(&pdev->dev);
0248
0249     return 0;
0250 }
0251
0252 static const struct of_device_id rcar_pwm_of_table[] = {
0253     { .compatible = "renesas,pwm-rcar", },
0254     { },
0255 };
0256 MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
0257
0258 static struct platform_driver rcar_pwm_driver = {
0259     .probe = rcar_pwm_probe,
0260     .remove = rcar_pwm_remove,
0261     .driver = {
0262         .name = "pwm-rcar",
0263         .of_match_table = of_match_ptr(rcar_pwm_of_table),
0264     }
0265 };
0266 module_platform_driver(rcar_pwm_driver);
0267
0268 MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
0269 MODULE_DESCRIPTION("Renesas PWM Timer Driver");
0270 MODULE_LICENSE("GPL v2");
0271 MODULE_ALIAS("platform:pwm-rcar");