drivers/pwm/pwm-mxs.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright 2012 Freescale Semiconductor, Inc.
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/err.h>
0008 #include <linux/io.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/pwm.h>
0014 #include <linux/slab.h>
0015 #include <linux/stmp_device.h>
0016
0017 #define SET 0x4
0018 #define CLR 0x8
0019 #define TOG 0xc
0020
0021 #define PWM_CTRL        0x0
0022 #define PWM_ACTIVE0     0x10
0023 #define PWM_PERIOD0     0x20
0024 #define  PERIOD_PERIOD(p)   ((p) & 0xffff)
0025 #define  PERIOD_PERIOD_MAX  0x10000
0026 #define  PERIOD_ACTIVE_HIGH (3 << 16)
0027 #define  PERIOD_ACTIVE_LOW  (2 << 16)
0028 #define  PERIOD_INACTIVE_HIGH   (3 << 18)
0029 #define  PERIOD_INACTIVE_LOW    (2 << 18)
0030 #define  PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW)
0031 #define  PERIOD_POLARITY_INVERSE    (PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH)
0032 #define  PERIOD_CDIV(div)   (((div) & 0x7) << 20)
0033 #define  PERIOD_CDIV_MAX    8
0034
0035 static const u8 cdiv_shift[PERIOD_CDIV_MAX] = {
0036     0, 1, 2, 3, 4, 6, 8, 10
0037 };
0038
0039 struct mxs_pwm_chip {
0040     struct pwm_chip chip;
0041     struct clk *clk;
0042     void __iomem *base;
0043 };
0044
0045 #define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
0046
0047 static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0048              const struct pwm_state *state)
0049 {
0050     struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
0051     int ret, div = 0;
0052     unsigned int period_cycles, duty_cycles;
0053     unsigned long rate;
0054     unsigned long long c;
0055     unsigned int pol_bits;
0056
0057     /*
0058      * If the PWM channel is disabled, make sure to turn on the
0059      * clock before calling clk_get_rate() and writing to the
0060      * registers. Otherwise, just keep it enabled.
0061      */
0062     if (!pwm_is_enabled(pwm)) {
0063         ret = clk_prepare_enable(mxs->clk);
0064         if (ret)
0065             return ret;
0066     }
0067
0068     if (!state->enabled && pwm_is_enabled(pwm))
0069         writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
0070
0071     rate = clk_get_rate(mxs->clk);
0072     while (1) {
0073         c = rate >> cdiv_shift[div];
0074         c = c * state->period;
0075         do_div(c, 1000000000);
0076         if (c < PERIOD_PERIOD_MAX)
0077             break;
0078         div++;
0079         if (div >= PERIOD_CDIV_MAX)
0080             return -EINVAL;
0081     }
0082
0083     period_cycles = c;
0084     c *= state->duty_cycle;
0085     do_div(c, state->period);
0086     duty_cycles = c;
0087
0088     /*
0089      * The data sheet the says registers must be written to in
0090      * this order (ACTIVEn, then PERIODn). Also, the new settings
0091      * only take effect at the beginning of a new period, avoiding
0092      * glitches.
0093      */
0094
0095     pol_bits = state->polarity == PWM_POLARITY_NORMAL ?
0096         PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE;
0097     writel(duty_cycles << 16,
0098            mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
0099     writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div),
0100            mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
0101
0102     if (state->enabled) {
0103         if (!pwm_is_enabled(pwm)) {
0104             /*
0105              * The clock was enabled above. Just enable
0106              * the channel in the control register.
0107              */
0108             writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
0109         }
0110     } else {
0111         clk_disable_unprepare(mxs->clk);
0112     }
0113     return 0;
0114 }
0115
0116 static const struct pwm_ops mxs_pwm_ops = {
0117     .apply = mxs_pwm_apply,
0118     .owner = THIS_MODULE,
0119 };
0120
0121 static int mxs_pwm_probe(struct platform_device *pdev)
0122 {
0123     struct device_node *np = pdev->dev.of_node;
0124     struct mxs_pwm_chip *mxs;
0125     int ret;
0126
0127     mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
0128     if (!mxs)
0129         return -ENOMEM;
0130
0131     mxs->base = devm_platform_ioremap_resource(pdev, 0);
0132     if (IS_ERR(mxs->base))
0133         return PTR_ERR(mxs->base);
0134
0135     mxs->clk = devm_clk_get(&pdev->dev, NULL);
0136     if (IS_ERR(mxs->clk))
0137         return PTR_ERR(mxs->clk);
0138
0139     mxs->chip.dev = &pdev->dev;
0140     mxs->chip.ops = &mxs_pwm_ops;
0141
0142     ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
0143     if (ret < 0) {
0144         dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
0145         return ret;
0146     }
0147
0148     /* FIXME: Only do this if the PWM isn't already running */
0149     ret = stmp_reset_block(mxs->base);
0150     if (ret)
0151         return dev_err_probe(&pdev->dev, ret, "failed to reset PWM\n");
0152
0153     ret = devm_pwmchip_add(&pdev->dev, &mxs->chip);
0154     if (ret < 0) {
0155         dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
0156         return ret;
0157     }
0158
0159     return 0;
0160 }
0161
0162 static const struct of_device_id mxs_pwm_dt_ids[] = {
0163     { .compatible = "fsl,imx23-pwm", },
0164     { /* sentinel */ }
0165 };
0166 MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
0167
0168 static struct platform_driver mxs_pwm_driver = {
0169     .driver = {
0170         .name = "mxs-pwm",
0171         .of_match_table = mxs_pwm_dt_ids,
0172     },
0173     .probe = mxs_pwm_probe,
0174 };
0175 module_platform_driver(mxs_pwm_driver);
0176
0177 MODULE_ALIAS("platform:mxs-pwm");
0178 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
0179 MODULE_DESCRIPTION("Freescale MXS PWM Driver");
0180 MODULE_LICENSE("GPL v2");