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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * MediaTek display pulse-width-modulation controller driver.
0004  * Copyright (c) 2015 MediaTek Inc.
0005  * Author: YH Huang <yh.huang@mediatek.com>
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/clk.h>
0010 #include <linux/err.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pwm.h>
0017 #include <linux/slab.h>
0018 
0019 #define DISP_PWM_EN     0x00
0020 
0021 #define PWM_CLKDIV_SHIFT    16
0022 #define PWM_CLKDIV_MAX      0x3ff
0023 #define PWM_CLKDIV_MASK     (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
0024 
0025 #define PWM_PERIOD_BIT_WIDTH    12
0026 #define PWM_PERIOD_MASK     ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
0027 
0028 #define PWM_HIGH_WIDTH_SHIFT    16
0029 #define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
0030 
0031 struct mtk_pwm_data {
0032     u32 enable_mask;
0033     unsigned int con0;
0034     u32 con0_sel;
0035     unsigned int con1;
0036 
0037     bool has_commit;
0038     unsigned int commit;
0039     unsigned int commit_mask;
0040 
0041     unsigned int bls_debug;
0042     u32 bls_debug_mask;
0043 };
0044 
0045 struct mtk_disp_pwm {
0046     struct pwm_chip chip;
0047     const struct mtk_pwm_data *data;
0048     struct clk *clk_main;
0049     struct clk *clk_mm;
0050     void __iomem *base;
0051     bool enabled;
0052 };
0053 
0054 static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
0055 {
0056     return container_of(chip, struct mtk_disp_pwm, chip);
0057 }
0058 
0059 static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
0060                      u32 mask, u32 data)
0061 {
0062     void __iomem *address = mdp->base + offset;
0063     u32 value;
0064 
0065     value = readl(address);
0066     value &= ~mask;
0067     value |= data;
0068     writel(value, address);
0069 }
0070 
0071 static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0072                   const struct pwm_state *state)
0073 {
0074     struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
0075     u32 clk_div, period, high_width, value;
0076     u64 div, rate;
0077     int err;
0078 
0079     if (state->polarity != PWM_POLARITY_NORMAL)
0080         return -EINVAL;
0081 
0082     if (!state->enabled) {
0083         mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
0084                      0x0);
0085 
0086         if (mdp->enabled) {
0087             clk_disable_unprepare(mdp->clk_mm);
0088             clk_disable_unprepare(mdp->clk_main);
0089         }
0090 
0091         mdp->enabled = false;
0092         return 0;
0093     }
0094 
0095     if (!mdp->enabled) {
0096         err = clk_prepare_enable(mdp->clk_main);
0097         if (err < 0) {
0098             dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n",
0099                 ERR_PTR(err));
0100             return err;
0101         }
0102 
0103         err = clk_prepare_enable(mdp->clk_mm);
0104         if (err < 0) {
0105             dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n",
0106                 ERR_PTR(err));
0107             clk_disable_unprepare(mdp->clk_main);
0108             return err;
0109         }
0110     }
0111 
0112     /*
0113      * Find period, high_width and clk_div to suit duty_ns and period_ns.
0114      * Calculate proper div value to keep period value in the bound.
0115      *
0116      * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
0117      * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
0118      *
0119      * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
0120      * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
0121      */
0122     rate = clk_get_rate(mdp->clk_main);
0123     clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
0124               PWM_PERIOD_BIT_WIDTH;
0125     if (clk_div > PWM_CLKDIV_MAX) {
0126         if (!mdp->enabled) {
0127             clk_disable_unprepare(mdp->clk_mm);
0128             clk_disable_unprepare(mdp->clk_main);
0129         }
0130         return -EINVAL;
0131     }
0132 
0133     div = NSEC_PER_SEC * (clk_div + 1);
0134     period = mul_u64_u64_div_u64(state->period, rate, div);
0135     if (period > 0)
0136         period--;
0137 
0138     high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
0139     value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
0140 
0141     mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
0142                  PWM_CLKDIV_MASK,
0143                  clk_div << PWM_CLKDIV_SHIFT);
0144     mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
0145                  PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
0146                  value);
0147 
0148     if (mdp->data->has_commit) {
0149         mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
0150                      mdp->data->commit_mask,
0151                      mdp->data->commit_mask);
0152         mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
0153                      mdp->data->commit_mask,
0154                      0x0);
0155     } else {
0156         /*
0157          * For MT2701, disable double buffer before writing register
0158          * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
0159          */
0160         mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
0161                      mdp->data->bls_debug_mask,
0162                      mdp->data->bls_debug_mask);
0163         mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
0164                      mdp->data->con0_sel,
0165                      mdp->data->con0_sel);
0166     }
0167 
0168     mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
0169                  mdp->data->enable_mask);
0170     mdp->enabled = true;
0171 
0172     return 0;
0173 }
0174 
0175 static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
0176                    struct pwm_device *pwm,
0177                    struct pwm_state *state)
0178 {
0179     struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
0180     u64 rate, period, high_width;
0181     u32 clk_div, con0, con1;
0182     int err;
0183 
0184     err = clk_prepare_enable(mdp->clk_main);
0185     if (err < 0) {
0186         dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
0187         return;
0188     }
0189 
0190     err = clk_prepare_enable(mdp->clk_mm);
0191     if (err < 0) {
0192         dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
0193         clk_disable_unprepare(mdp->clk_main);
0194         return;
0195     }
0196 
0197     rate = clk_get_rate(mdp->clk_main);
0198     con0 = readl(mdp->base + mdp->data->con0);
0199     con1 = readl(mdp->base + mdp->data->con1);
0200     state->enabled = !!(con0 & BIT(0));
0201     clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
0202     period = FIELD_GET(PWM_PERIOD_MASK, con1);
0203     /*
0204      * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
0205      * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
0206      */
0207     state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
0208     high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
0209     state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
0210                            rate);
0211     state->polarity = PWM_POLARITY_NORMAL;
0212     clk_disable_unprepare(mdp->clk_mm);
0213     clk_disable_unprepare(mdp->clk_main);
0214 }
0215 
0216 static const struct pwm_ops mtk_disp_pwm_ops = {
0217     .apply = mtk_disp_pwm_apply,
0218     .get_state = mtk_disp_pwm_get_state,
0219     .owner = THIS_MODULE,
0220 };
0221 
0222 static int mtk_disp_pwm_probe(struct platform_device *pdev)
0223 {
0224     struct mtk_disp_pwm *mdp;
0225     int ret;
0226 
0227     mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
0228     if (!mdp)
0229         return -ENOMEM;
0230 
0231     mdp->data = of_device_get_match_data(&pdev->dev);
0232 
0233     mdp->base = devm_platform_ioremap_resource(pdev, 0);
0234     if (IS_ERR(mdp->base))
0235         return PTR_ERR(mdp->base);
0236 
0237     mdp->clk_main = devm_clk_get(&pdev->dev, "main");
0238     if (IS_ERR(mdp->clk_main))
0239         return PTR_ERR(mdp->clk_main);
0240 
0241     mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
0242     if (IS_ERR(mdp->clk_mm))
0243         return PTR_ERR(mdp->clk_mm);
0244 
0245     mdp->chip.dev = &pdev->dev;
0246     mdp->chip.ops = &mtk_disp_pwm_ops;
0247     mdp->chip.npwm = 1;
0248 
0249     ret = pwmchip_add(&mdp->chip);
0250     if (ret < 0) {
0251         dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
0252         return ret;
0253     }
0254 
0255     platform_set_drvdata(pdev, mdp);
0256 
0257     return 0;
0258 }
0259 
0260 static int mtk_disp_pwm_remove(struct platform_device *pdev)
0261 {
0262     struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
0263 
0264     pwmchip_remove(&mdp->chip);
0265 
0266     return 0;
0267 }
0268 
0269 static const struct mtk_pwm_data mt2701_pwm_data = {
0270     .enable_mask = BIT(16),
0271     .con0 = 0xa8,
0272     .con0_sel = 0x2,
0273     .con1 = 0xac,
0274     .has_commit = false,
0275     .bls_debug = 0xb0,
0276     .bls_debug_mask = 0x3,
0277 };
0278 
0279 static const struct mtk_pwm_data mt8173_pwm_data = {
0280     .enable_mask = BIT(0),
0281     .con0 = 0x10,
0282     .con0_sel = 0x0,
0283     .con1 = 0x14,
0284     .has_commit = true,
0285     .commit = 0x8,
0286     .commit_mask = 0x1,
0287 };
0288 
0289 static const struct mtk_pwm_data mt8183_pwm_data = {
0290     .enable_mask = BIT(0),
0291     .con0 = 0x18,
0292     .con0_sel = 0x0,
0293     .con1 = 0x1c,
0294     .has_commit = false,
0295     .bls_debug = 0x80,
0296     .bls_debug_mask = 0x3,
0297 };
0298 
0299 static const struct of_device_id mtk_disp_pwm_of_match[] = {
0300     { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
0301     { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
0302     { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
0303     { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
0304     { }
0305 };
0306 MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
0307 
0308 static struct platform_driver mtk_disp_pwm_driver = {
0309     .driver = {
0310         .name = "mediatek-disp-pwm",
0311         .of_match_table = mtk_disp_pwm_of_match,
0312     },
0313     .probe = mtk_disp_pwm_probe,
0314     .remove = mtk_disp_pwm_remove,
0315 };
0316 module_platform_driver(mtk_disp_pwm_driver);
0317 
0318 MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
0319 MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
0320 MODULE_LICENSE("GPL v2");
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