drivers/pwm/pwm-lpss.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Intel Low Power Subsystem PWM controller driver
0004  *
0005  * Copyright (C) 2014, Intel Corporation
0006  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
0007  * Author: Chew Kean Ho <kean.ho.chew@intel.com>
0008  * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
0009  * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
0010  * Author: Alan Cox <alan@linux.intel.com>
0011  */
0012
0013 #include <linux/delay.h>
0014 #include <linux/io.h>
0015 #include <linux/iopoll.h>
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/time.h>
0020
0021 #include "pwm-lpss.h"
0022
0023 #define PWM             0x00000000
0024 #define PWM_ENABLE          BIT(31)
0025 #define PWM_SW_UPDATE           BIT(30)
0026 #define PWM_BASE_UNIT_SHIFT     8
0027 #define PWM_ON_TIME_DIV_MASK        0x000000ff
0028
0029 /* Size of each PWM register space if multiple */
0030 #define PWM_SIZE            0x400
0031
0032 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
0033 {
0034     return container_of(chip, struct pwm_lpss_chip, chip);
0035 }
0036
0037 static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
0038 {
0039     struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
0040
0041     return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
0042 }
0043
0044 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
0045 {
0046     struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
0047
0048     writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
0049 }
0050
0051 static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
0052 {
0053     struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
0054     const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
0055     const unsigned int ms = 500 * USEC_PER_MSEC;
0056     u32 val;
0057     int err;
0058
0059     /*
0060      * PWM Configuration register has SW_UPDATE bit that is set when a new
0061      * configuration is written to the register. The bit is automatically
0062      * cleared at the start of the next output cycle by the IP block.
0063      *
0064      * If one writes a new configuration to the register while it still has
0065      * the bit enabled, PWM may freeze. That is, while one can still write
0066      * to the register, it won't have an effect. Thus, we try to sleep long
0067      * enough that the bit gets cleared and make sure the bit is not
0068      * enabled while we update the configuration.
0069      */
0070     err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
0071     if (err)
0072         dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
0073
0074     return err;
0075 }
0076
0077 static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
0078 {
0079     if (pwm_lpss_read(pwm) & PWM_SW_UPDATE) {
0080         dev_err(pwm->chip->dev, "PWM_SW_UPDATE is still set, skipping update\n");
0081         return -EBUSY;
0082     }
0083
0084     return 0;
0085 }
0086
0087 static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
0088                  int duty_ns, int period_ns)
0089 {
0090     unsigned long long on_time_div;
0091     unsigned long c = lpwm->info->clk_rate, base_unit_range;
0092     unsigned long long base_unit, freq = NSEC_PER_SEC;
0093     u32 ctrl;
0094
0095     do_div(freq, period_ns);
0096
0097     /*
0098      * The equation is:
0099      * base_unit = round(base_unit_range * freq / c)
0100      */
0101     base_unit_range = BIT(lpwm->info->base_unit_bits);
0102     freq *= base_unit_range;
0103
0104     base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
0105     /* base_unit must not be 0 and we also want to avoid overflowing it */
0106     base_unit = clamp_val(base_unit, 1, base_unit_range - 1);
0107
0108     on_time_div = 255ULL * duty_ns;
0109     do_div(on_time_div, period_ns);
0110     on_time_div = 255ULL - on_time_div;
0111
0112     ctrl = pwm_lpss_read(pwm);
0113     ctrl &= ~PWM_ON_TIME_DIV_MASK;
0114     ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
0115     ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
0116     ctrl |= on_time_div;
0117
0118     pwm_lpss_write(pwm, ctrl);
0119     pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
0120 }
0121
0122 static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
0123 {
0124     if (cond)
0125         pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
0126 }
0127
0128 static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm,
0129                    struct pwm_device *pwm,
0130                    const struct pwm_state *state)
0131 {
0132     int ret;
0133
0134     ret = pwm_lpss_is_updating(pwm);
0135     if (ret)
0136         return ret;
0137
0138     pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
0139     pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
0140     ret = pwm_lpss_wait_for_update(pwm);
0141     if (ret)
0142         return ret;
0143
0144     pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
0145     return 0;
0146 }
0147
0148 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0149               const struct pwm_state *state)
0150 {
0151     struct pwm_lpss_chip *lpwm = to_lpwm(chip);
0152     int ret = 0;
0153
0154     if (state->enabled) {
0155         if (!pwm_is_enabled(pwm)) {
0156             pm_runtime_get_sync(chip->dev);
0157             ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
0158             if (ret)
0159                 pm_runtime_put(chip->dev);
0160         } else {
0161             ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
0162         }
0163     } else if (pwm_is_enabled(pwm)) {
0164         pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
0165         pm_runtime_put(chip->dev);
0166     }
0167
0168     return ret;
0169 }
0170
0171 static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
0172                    struct pwm_state *state)
0173 {
0174     struct pwm_lpss_chip *lpwm = to_lpwm(chip);
0175     unsigned long base_unit_range;
0176     unsigned long long base_unit, freq, on_time_div;
0177     u32 ctrl;
0178
0179     pm_runtime_get_sync(chip->dev);
0180
0181     base_unit_range = BIT(lpwm->info->base_unit_bits);
0182
0183     ctrl = pwm_lpss_read(pwm);
0184     on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
0185     base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
0186
0187     freq = base_unit * lpwm->info->clk_rate;
0188     do_div(freq, base_unit_range);
0189     if (freq == 0)
0190         state->period = NSEC_PER_SEC;
0191     else
0192         state->period = NSEC_PER_SEC / (unsigned long)freq;
0193
0194     on_time_div *= state->period;
0195     do_div(on_time_div, 255);
0196     state->duty_cycle = on_time_div;
0197
0198     state->polarity = PWM_POLARITY_NORMAL;
0199     state->enabled = !!(ctrl & PWM_ENABLE);
0200
0201     pm_runtime_put(chip->dev);
0202 }
0203
0204 static const struct pwm_ops pwm_lpss_ops = {
0205     .apply = pwm_lpss_apply,
0206     .get_state = pwm_lpss_get_state,
0207     .owner = THIS_MODULE,
0208 };
0209
0210 struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
0211                      const struct pwm_lpss_boardinfo *info)
0212 {
0213     struct pwm_lpss_chip *lpwm;
0214     unsigned long c;
0215     int i, ret;
0216     u32 ctrl;
0217
0218     if (WARN_ON(info->npwm > MAX_PWMS))
0219         return ERR_PTR(-ENODEV);
0220
0221     lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
0222     if (!lpwm)
0223         return ERR_PTR(-ENOMEM);
0224
0225     lpwm->regs = devm_ioremap_resource(dev, r);
0226     if (IS_ERR(lpwm->regs))
0227         return ERR_CAST(lpwm->regs);
0228
0229     lpwm->info = info;
0230
0231     c = lpwm->info->clk_rate;
0232     if (!c)
0233         return ERR_PTR(-EINVAL);
0234
0235     lpwm->chip.dev = dev;
0236     lpwm->chip.ops = &pwm_lpss_ops;
0237     lpwm->chip.npwm = info->npwm;
0238
0239     ret = devm_pwmchip_add(dev, &lpwm->chip);
0240     if (ret) {
0241         dev_err(dev, "failed to add PWM chip: %d\n", ret);
0242         return ERR_PTR(ret);
0243     }
0244
0245     for (i = 0; i < lpwm->info->npwm; i++) {
0246         ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
0247         if (ctrl & PWM_ENABLE)
0248             pm_runtime_get(dev);
0249     }
0250
0251     return lpwm;
0252 }
0253 EXPORT_SYMBOL_GPL(pwm_lpss_probe);
0254
0255 MODULE_DESCRIPTION("PWM driver for Intel LPSS");
0256 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
0257 MODULE_LICENSE("GPL v2");