drivers/pwm/pwm-lpc18xx-sct.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver
0004  *
0005  * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
0006  *
0007  * Notes
0008  * =====
0009  * NXP LPC18xx provides a State Configurable Timer (SCT) which can be configured
0010  * as a Pulse Width Modulator.
0011  *
0012  * SCT supports 16 outputs, 16 events and 16 registers. Each event will be
0013  * triggered when its related register matches the SCT counter value, and it
0014  * will set or clear a selected output.
0015  *
0016  * One of the events is preselected to generate the period, thus the maximum
0017  * number of simultaneous channels is limited to 15. Notice that period is
0018  * global to all the channels, thus PWM driver will refuse setting different
0019  * values to it, unless there's only one channel requested.
0020  */
0021
0022 #include <linux/clk.h>
0023 #include <linux/err.h>
0024 #include <linux/io.h>
0025 #include <linux/module.h>
0026 #include <linux/platform_device.h>
0027 #include <linux/pwm.h>
0028
0029 /* LPC18xx SCT registers */
0030 #define LPC18XX_PWM_CONFIG      0x000
0031 #define LPC18XX_PWM_CONFIG_UNIFY    BIT(0)
0032 #define LPC18XX_PWM_CONFIG_NORELOAD BIT(7)
0033
0034 #define LPC18XX_PWM_CTRL        0x004
0035 #define LPC18XX_PWM_CTRL_HALT       BIT(2)
0036 #define LPC18XX_PWM_BIDIR       BIT(4)
0037 #define LPC18XX_PWM_PRE_SHIFT       5
0038 #define LPC18XX_PWM_PRE_MASK        (0xff << LPC18XX_PWM_PRE_SHIFT)
0039 #define LPC18XX_PWM_PRE(x)      (x << LPC18XX_PWM_PRE_SHIFT)
0040
0041 #define LPC18XX_PWM_LIMIT       0x008
0042
0043 #define LPC18XX_PWM_RES_BASE        0x058
0044 #define LPC18XX_PWM_RES_SHIFT(_ch)  (_ch * 2)
0045 #define LPC18XX_PWM_RES(_ch, _action)   (_action << LPC18XX_PWM_RES_SHIFT(_ch))
0046 #define LPC18XX_PWM_RES_MASK(_ch)   (0x3 << LPC18XX_PWM_RES_SHIFT(_ch))
0047
0048 #define LPC18XX_PWM_MATCH_BASE      0x100
0049 #define LPC18XX_PWM_MATCH(_ch)      (LPC18XX_PWM_MATCH_BASE + _ch * 4)
0050
0051 #define LPC18XX_PWM_MATCHREL_BASE   0x200
0052 #define LPC18XX_PWM_MATCHREL(_ch)   (LPC18XX_PWM_MATCHREL_BASE + _ch * 4)
0053
0054 #define LPC18XX_PWM_EVSTATEMSK_BASE 0x300
0055 #define LPC18XX_PWM_EVSTATEMSK(_ch) (LPC18XX_PWM_EVSTATEMSK_BASE + _ch * 8)
0056 #define LPC18XX_PWM_EVSTATEMSK_ALL  0xffffffff
0057
0058 #define LPC18XX_PWM_EVCTRL_BASE     0x304
0059 #define LPC18XX_PWM_EVCTRL(_ev)     (LPC18XX_PWM_EVCTRL_BASE + _ev * 8)
0060
0061 #define LPC18XX_PWM_EVCTRL_MATCH(_ch)   _ch
0062
0063 #define LPC18XX_PWM_EVCTRL_COMB_SHIFT   12
0064 #define LPC18XX_PWM_EVCTRL_COMB_MATCH   (0x1 << LPC18XX_PWM_EVCTRL_COMB_SHIFT)
0065
0066 #define LPC18XX_PWM_OUTPUTSET_BASE  0x500
0067 #define LPC18XX_PWM_OUTPUTSET(_ch)  (LPC18XX_PWM_OUTPUTSET_BASE + _ch * 8)
0068
0069 #define LPC18XX_PWM_OUTPUTCL_BASE   0x504
0070 #define LPC18XX_PWM_OUTPUTCL(_ch)   (LPC18XX_PWM_OUTPUTCL_BASE + _ch * 8)
0071
0072 /* LPC18xx SCT unified counter */
0073 #define LPC18XX_PWM_TIMER_MAX       0xffffffff
0074
0075 /* LPC18xx SCT events */
0076 #define LPC18XX_PWM_EVENT_PERIOD    0
0077 #define LPC18XX_PWM_EVENT_MAX       16
0078
0079 #define LPC18XX_NUM_PWMS        16
0080
0081 /* SCT conflict resolution */
0082 enum lpc18xx_pwm_res_action {
0083     LPC18XX_PWM_RES_NONE,
0084     LPC18XX_PWM_RES_SET,
0085     LPC18XX_PWM_RES_CLEAR,
0086     LPC18XX_PWM_RES_TOGGLE,
0087 };
0088
0089 struct lpc18xx_pwm_data {
0090     unsigned int duty_event;
0091 };
0092
0093 struct lpc18xx_pwm_chip {
0094     struct device *dev;
0095     struct pwm_chip chip;
0096     void __iomem *base;
0097     struct clk *pwm_clk;
0098     unsigned long clk_rate;
0099     unsigned int period_ns;
0100     unsigned int min_period_ns;
0101     u64 max_period_ns;
0102     unsigned int period_event;
0103     unsigned long event_map;
0104     struct mutex res_lock;
0105     struct mutex period_lock;
0106     struct lpc18xx_pwm_data channeldata[LPC18XX_NUM_PWMS];
0107 };
0108
0109 static inline struct lpc18xx_pwm_chip *
0110 to_lpc18xx_pwm_chip(struct pwm_chip *chip)
0111 {
0112     return container_of(chip, struct lpc18xx_pwm_chip, chip);
0113 }
0114
0115 static inline void lpc18xx_pwm_writel(struct lpc18xx_pwm_chip *lpc18xx_pwm,
0116                       u32 reg, u32 val)
0117 {
0118     writel(val, lpc18xx_pwm->base + reg);
0119 }
0120
0121 static inline u32 lpc18xx_pwm_readl(struct lpc18xx_pwm_chip *lpc18xx_pwm,
0122                     u32 reg)
0123 {
0124     return readl(lpc18xx_pwm->base + reg);
0125 }
0126
0127 static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm,
0128                      struct pwm_device *pwm,
0129                      enum lpc18xx_pwm_res_action action)
0130 {
0131     u32 val;
0132
0133     mutex_lock(&lpc18xx_pwm->res_lock);
0134
0135     /*
0136      * Simultaneous set and clear may happen on an output, that is the case
0137      * when duty_ns == period_ns. LPC18xx SCT allows to set a conflict
0138      * resolution action to be taken in such a case.
0139      */
0140     val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE);
0141     val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm);
0142     val |= LPC18XX_PWM_RES(pwm->hwpwm, action);
0143     lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val);
0144
0145     mutex_unlock(&lpc18xx_pwm->res_lock);
0146 }
0147
0148 static void lpc18xx_pwm_config_period(struct pwm_chip *chip, u64 period_ns)
0149 {
0150     struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
0151     u32 val;
0152
0153     /*
0154      * With clk_rate < NSEC_PER_SEC this cannot overflow.
0155      * With period_ns < max_period_ns this also fits into an u32.
0156      * As period_ns >= min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, lpc18xx_pwm->clk_rate);
0157      * we have val >= 1.
0158      */
0159     val = mul_u64_u64_div_u64(period_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
0160
0161     lpc18xx_pwm_writel(lpc18xx_pwm,
0162                LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event),
0163                val - 1);
0164
0165     lpc18xx_pwm_writel(lpc18xx_pwm,
0166                LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event),
0167                val - 1);
0168 }
0169
0170 static void lpc18xx_pwm_config_duty(struct pwm_chip *chip,
0171                     struct pwm_device *pwm, u64 duty_ns)
0172 {
0173     struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
0174     struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
0175     u32 val;
0176
0177     /*
0178      * With clk_rate < NSEC_PER_SEC this cannot overflow.
0179      * With duty_ns <= period_ns < max_period_ns this also fits into an u32.
0180      */
0181     val = mul_u64_u64_div_u64(duty_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
0182
0183     lpc18xx_pwm_writel(lpc18xx_pwm,
0184                LPC18XX_PWM_MATCH(lpc18xx_data->duty_event),
0185                val);
0186
0187     lpc18xx_pwm_writel(lpc18xx_pwm,
0188                LPC18XX_PWM_MATCHREL(lpc18xx_data->duty_event),
0189                val);
0190 }
0191
0192 static int lpc18xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
0193                   int duty_ns, int period_ns)
0194 {
0195     struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
0196     int requested_events, i;
0197
0198     if (period_ns < lpc18xx_pwm->min_period_ns ||
0199         period_ns > lpc18xx_pwm->max_period_ns) {
0200         dev_err(chip->dev, "period %d not in range\n", period_ns);
0201         return -ERANGE;
0202     }
0203
0204     mutex_lock(&lpc18xx_pwm->period_lock);
0205
0206     requested_events = bitmap_weight(&lpc18xx_pwm->event_map,
0207                      LPC18XX_PWM_EVENT_MAX);
0208
0209     /*
0210      * The PWM supports only a single period for all PWM channels.
0211      * Once the period is set, it can only be changed if no more than one
0212      * channel is requested at that moment.
0213      */
0214     if (requested_events > 2 && lpc18xx_pwm->period_ns != period_ns &&
0215         lpc18xx_pwm->period_ns) {
0216         dev_err(chip->dev, "conflicting period requested for PWM %u\n",
0217             pwm->hwpwm);
0218         mutex_unlock(&lpc18xx_pwm->period_lock);
0219         return -EBUSY;
0220     }
0221
0222     if ((requested_events <= 2 && lpc18xx_pwm->period_ns != period_ns) ||
0223         !lpc18xx_pwm->period_ns) {
0224         lpc18xx_pwm->period_ns = period_ns;
0225         for (i = 0; i < chip->npwm; i++)
0226             pwm_set_period(&chip->pwms[i], period_ns);
0227         lpc18xx_pwm_config_period(chip, period_ns);
0228     }
0229
0230     mutex_unlock(&lpc18xx_pwm->period_lock);
0231
0232     lpc18xx_pwm_config_duty(chip, pwm, duty_ns);
0233
0234     return 0;
0235 }
0236
0237 static int lpc18xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity)
0238 {
0239     struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
0240     struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
0241     enum lpc18xx_pwm_res_action res_action;
0242     unsigned int set_event, clear_event;
0243
0244     lpc18xx_pwm_writel(lpc18xx_pwm,
0245                LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event),
0246                LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_data->duty_event) |
0247                LPC18XX_PWM_EVCTRL_COMB_MATCH);
0248
0249     lpc18xx_pwm_writel(lpc18xx_pwm,
0250                LPC18XX_PWM_EVSTATEMSK(lpc18xx_data->duty_event),
0251                LPC18XX_PWM_EVSTATEMSK_ALL);
0252
0253     if (polarity == PWM_POLARITY_NORMAL) {
0254         set_event = lpc18xx_pwm->period_event;
0255         clear_event = lpc18xx_data->duty_event;
0256         res_action = LPC18XX_PWM_RES_SET;
0257     } else {
0258         set_event = lpc18xx_data->duty_event;
0259         clear_event = lpc18xx_pwm->period_event;
0260         res_action = LPC18XX_PWM_RES_CLEAR;
0261     }
0262
0263     lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm),
0264                BIT(set_event));
0265     lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm),
0266                BIT(clear_event));
0267     lpc18xx_pwm_set_conflict_res(lpc18xx_pwm, pwm, res_action);
0268
0269     return 0;
0270 }
0271
0272 static void lpc18xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
0273 {
0274     struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
0275     struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
0276
0277     lpc18xx_pwm_writel(lpc18xx_pwm,
0278                LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event), 0);
0279     lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0);
0280     lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0);
0281 }
0282
0283 static int lpc18xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
0284 {
0285     struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
0286     struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
0287     unsigned long event;
0288
0289     event = find_first_zero_bit(&lpc18xx_pwm->event_map,
0290                     LPC18XX_PWM_EVENT_MAX);
0291
0292     if (event >= LPC18XX_PWM_EVENT_MAX) {
0293         dev_err(lpc18xx_pwm->dev,
0294             "maximum number of simultaneous channels reached\n");
0295         return -EBUSY;
0296     }
0297
0298     set_bit(event, &lpc18xx_pwm->event_map);
0299     lpc18xx_data->duty_event = event;
0300
0301     return 0;
0302 }
0303
0304 static void lpc18xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
0305 {
0306     struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
0307     struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
0308
0309     clear_bit(lpc18xx_data->duty_event, &lpc18xx_pwm->event_map);
0310 }
0311
0312 static int lpc18xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0313                  const struct pwm_state *state)
0314 {
0315     int err;
0316     bool enabled = pwm->state.enabled;
0317
0318     if (state->polarity != pwm->state.polarity && pwm->state.enabled) {
0319         lpc18xx_pwm_disable(chip, pwm);
0320         enabled = false;
0321     }
0322
0323     if (!state->enabled) {
0324         if (enabled)
0325             lpc18xx_pwm_disable(chip, pwm);
0326
0327         return 0;
0328     }
0329
0330     err = lpc18xx_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
0331     if (err)
0332         return err;
0333
0334     if (!enabled)
0335         err = lpc18xx_pwm_enable(chip, pwm, state->polarity);
0336
0337     return err;
0338 }
0339 static const struct pwm_ops lpc18xx_pwm_ops = {
0340     .apply = lpc18xx_pwm_apply,
0341     .request = lpc18xx_pwm_request,
0342     .free = lpc18xx_pwm_free,
0343     .owner = THIS_MODULE,
0344 };
0345
0346 static const struct of_device_id lpc18xx_pwm_of_match[] = {
0347     { .compatible = "nxp,lpc1850-sct-pwm" },
0348     {}
0349 };
0350 MODULE_DEVICE_TABLE(of, lpc18xx_pwm_of_match);
0351
0352 static int lpc18xx_pwm_probe(struct platform_device *pdev)
0353 {
0354     struct lpc18xx_pwm_chip *lpc18xx_pwm;
0355     int ret;
0356     u64 val;
0357
0358     lpc18xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*lpc18xx_pwm),
0359                    GFP_KERNEL);
0360     if (!lpc18xx_pwm)
0361         return -ENOMEM;
0362
0363     lpc18xx_pwm->dev = &pdev->dev;
0364
0365     lpc18xx_pwm->base = devm_platform_ioremap_resource(pdev, 0);
0366     if (IS_ERR(lpc18xx_pwm->base))
0367         return PTR_ERR(lpc18xx_pwm->base);
0368
0369     lpc18xx_pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
0370     if (IS_ERR(lpc18xx_pwm->pwm_clk))
0371         return dev_err_probe(&pdev->dev, PTR_ERR(lpc18xx_pwm->pwm_clk),
0372                      "failed to get pwm clock\n");
0373
0374     ret = clk_prepare_enable(lpc18xx_pwm->pwm_clk);
0375     if (ret < 0)
0376         return dev_err_probe(&pdev->dev, ret,
0377                      "could not prepare or enable pwm clock\n");
0378
0379     lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk);
0380     if (!lpc18xx_pwm->clk_rate) {
0381         ret = dev_err_probe(&pdev->dev,
0382                     -EINVAL, "pwm clock has no frequency\n");
0383         goto disable_pwmclk;
0384     }
0385
0386     /*
0387      * If clkrate is too fast, the calculations in .apply() might overflow.
0388      */
0389     if (lpc18xx_pwm->clk_rate > NSEC_PER_SEC) {
0390         ret = dev_err_probe(&pdev->dev, -EINVAL, "pwm clock to fast\n");
0391         goto disable_pwmclk;
0392     }
0393
0394     mutex_init(&lpc18xx_pwm->res_lock);
0395     mutex_init(&lpc18xx_pwm->period_lock);
0396
0397     lpc18xx_pwm->max_period_ns =
0398         mul_u64_u64_div_u64(NSEC_PER_SEC, LPC18XX_PWM_TIMER_MAX, lpc18xx_pwm->clk_rate);
0399
0400     lpc18xx_pwm->min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC,
0401                           lpc18xx_pwm->clk_rate);
0402
0403     lpc18xx_pwm->chip.dev = &pdev->dev;
0404     lpc18xx_pwm->chip.ops = &lpc18xx_pwm_ops;
0405     lpc18xx_pwm->chip.npwm = LPC18XX_NUM_PWMS;
0406
0407     /* SCT counter must be in unify (32 bit) mode */
0408     lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CONFIG,
0409                LPC18XX_PWM_CONFIG_UNIFY);
0410
0411     /*
0412      * Everytime the timer counter reaches the period value, the related
0413      * event will be triggered and the counter reset to 0.
0414      */
0415     set_bit(LPC18XX_PWM_EVENT_PERIOD, &lpc18xx_pwm->event_map);
0416     lpc18xx_pwm->period_event = LPC18XX_PWM_EVENT_PERIOD;
0417
0418     lpc18xx_pwm_writel(lpc18xx_pwm,
0419                LPC18XX_PWM_EVSTATEMSK(lpc18xx_pwm->period_event),
0420                LPC18XX_PWM_EVSTATEMSK_ALL);
0421
0422     val = LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_pwm->period_event) |
0423           LPC18XX_PWM_EVCTRL_COMB_MATCH;
0424     lpc18xx_pwm_writel(lpc18xx_pwm,
0425                LPC18XX_PWM_EVCTRL(lpc18xx_pwm->period_event), val);
0426
0427     lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_LIMIT,
0428                BIT(lpc18xx_pwm->period_event));
0429
0430     val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
0431     val &= ~LPC18XX_PWM_BIDIR;
0432     val &= ~LPC18XX_PWM_CTRL_HALT;
0433     val &= ~LPC18XX_PWM_PRE_MASK;
0434     val |= LPC18XX_PWM_PRE(0);
0435     lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, val);
0436
0437     ret = pwmchip_add(&lpc18xx_pwm->chip);
0438     if (ret < 0) {
0439         dev_err_probe(&pdev->dev, ret, "pwmchip_add failed\n");
0440         goto disable_pwmclk;
0441     }
0442
0443     platform_set_drvdata(pdev, lpc18xx_pwm);
0444
0445     return 0;
0446
0447 disable_pwmclk:
0448     clk_disable_unprepare(lpc18xx_pwm->pwm_clk);
0449     return ret;
0450 }
0451
0452 static int lpc18xx_pwm_remove(struct platform_device *pdev)
0453 {
0454     struct lpc18xx_pwm_chip *lpc18xx_pwm = platform_get_drvdata(pdev);
0455     u32 val;
0456
0457     pwmchip_remove(&lpc18xx_pwm->chip);
0458
0459     val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
0460     lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL,
0461                val | LPC18XX_PWM_CTRL_HALT);
0462
0463     clk_disable_unprepare(lpc18xx_pwm->pwm_clk);
0464
0465     return 0;
0466 }
0467
0468 static struct platform_driver lpc18xx_pwm_driver = {
0469     .driver = {
0470         .name = "lpc18xx-sct-pwm",
0471         .of_match_table = lpc18xx_pwm_of_match,
0472     },
0473     .probe = lpc18xx_pwm_probe,
0474     .remove = lpc18xx_pwm_remove,
0475 };
0476 module_platform_driver(lpc18xx_pwm_driver);
0477
0478 MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
0479 MODULE_DESCRIPTION("NXP LPC18xx PWM driver");
0480 MODULE_LICENSE("GPL v2");