drivers/pwm/pwm-intel-lgm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2020 Intel Corporation.
0004  *
0005  * Limitations:
0006  * - The hardware supports fixed period & configures only 2-wire mode.
0007  * - Supports normal polarity. Does not support changing polarity.
0008  * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
0009  *   keep track of running period.
0010  * - When duty cycle is changed, PWM output may be a mix of previous setting
0011  *   and new setting for the first period. From second period, the output is
0012  *   based on new setting.
0013  * - It is a dedicated PWM fan controller. There are no other consumers for
0014  *   this PWM controller.
0015  */
0016 #include <linux/bitfield.h>
0017 #include <linux/clk.h>
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/mod_devicetable.h>
0021 #include <linux/pwm.h>
0022 #include <linux/regmap.h>
0023 #include <linux/reset.h>
0024
0025 #define LGM_PWM_FAN_CON0        0x0
0026 #define LGM_PWM_FAN_EN_EN       BIT(0)
0027 #define LGM_PWM_FAN_EN_DIS      0x0
0028 #define LGM_PWM_FAN_EN_MSK      BIT(0)
0029 #define LGM_PWM_FAN_MODE_2WIRE      0x0
0030 #define LGM_PWM_FAN_MODE_MSK        BIT(1)
0031 #define LGM_PWM_FAN_DC_MSK      GENMASK(23, 16)
0032
0033 #define LGM_PWM_FAN_CON1        0x4
0034 #define LGM_PWM_FAN_MAX_RPM_MSK     GENMASK(15, 0)
0035
0036 #define LGM_PWM_MAX_RPM         (BIT(16) - 1)
0037 #define LGM_PWM_DEFAULT_RPM     4000
0038 #define LGM_PWM_MAX_DUTY_CYCLE      (BIT(8) - 1)
0039
0040 #define LGM_PWM_DC_BITS         8
0041
0042 #define LGM_PWM_PERIOD_2WIRE_NS     (40 * NSEC_PER_MSEC)
0043
0044 struct lgm_pwm_chip {
0045     struct pwm_chip chip;
0046     struct regmap *regmap;
0047     u32 period;
0048 };
0049
0050 static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
0051 {
0052     return container_of(chip, struct lgm_pwm_chip, chip);
0053 }
0054
0055 static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
0056 {
0057     struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
0058     struct regmap *regmap = pc->regmap;
0059
0060     return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
0061                   enable ? LGM_PWM_FAN_EN_EN : LGM_PWM_FAN_EN_DIS);
0062 }
0063
0064 static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0065              const struct pwm_state *state)
0066 {
0067     struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
0068     u32 duty_cycle, val;
0069     int ret;
0070
0071     /* The hardware only supports normal polarity and fixed period. */
0072     if (state->polarity != PWM_POLARITY_NORMAL || state->period < pc->period)
0073         return -EINVAL;
0074
0075     if (!state->enabled)
0076         return lgm_pwm_enable(chip, 0);
0077
0078     duty_cycle = min_t(u64, state->duty_cycle, pc->period);
0079     val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
0080
0081     ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_DC_MSK,
0082                  FIELD_PREP(LGM_PWM_FAN_DC_MSK, val));
0083     if (ret)
0084         return ret;
0085
0086     return lgm_pwm_enable(chip, 1);
0087 }
0088
0089 static void lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
0090                   struct pwm_state *state)
0091 {
0092     struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
0093     u32 duty, val;
0094
0095     state->enabled = regmap_test_bits(pc->regmap, LGM_PWM_FAN_CON0,
0096                       LGM_PWM_FAN_EN_EN);
0097     state->polarity = PWM_POLARITY_NORMAL;
0098     state->period = pc->period; /* fixed period */
0099
0100     regmap_read(pc->regmap, LGM_PWM_FAN_CON0, &val);
0101     duty = FIELD_GET(LGM_PWM_FAN_DC_MSK, val);
0102     state->duty_cycle = DIV_ROUND_UP(duty * pc->period, LGM_PWM_MAX_DUTY_CYCLE);
0103 }
0104
0105 static const struct pwm_ops lgm_pwm_ops = {
0106     .get_state = lgm_pwm_get_state,
0107     .apply = lgm_pwm_apply,
0108     .owner = THIS_MODULE,
0109 };
0110
0111 static void lgm_pwm_init(struct lgm_pwm_chip *pc)
0112 {
0113     struct regmap *regmap = pc->regmap;
0114     u32 con0_val;
0115
0116     con0_val = FIELD_PREP(LGM_PWM_FAN_MODE_MSK, LGM_PWM_FAN_MODE_2WIRE);
0117     pc->period = LGM_PWM_PERIOD_2WIRE_NS;
0118     regmap_update_bits(regmap, LGM_PWM_FAN_CON1, LGM_PWM_FAN_MAX_RPM_MSK,
0119                LGM_PWM_DEFAULT_RPM);
0120     regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_MODE_MSK,
0121                con0_val);
0122 }
0123
0124 static const struct regmap_config lgm_pwm_regmap_config = {
0125     .reg_bits = 32,
0126     .reg_stride = 4,
0127     .val_bits = 32,
0128 };
0129
0130 static void lgm_clk_release(void *data)
0131 {
0132     struct clk *clk = data;
0133
0134     clk_disable_unprepare(clk);
0135 }
0136
0137 static int lgm_clk_enable(struct device *dev, struct clk *clk)
0138 {
0139     int ret;
0140
0141     ret = clk_prepare_enable(clk);
0142     if (ret)
0143         return ret;
0144
0145     return devm_add_action_or_reset(dev, lgm_clk_release, clk);
0146 }
0147
0148 static void lgm_reset_control_release(void *data)
0149 {
0150     struct reset_control *rst = data;
0151
0152     reset_control_assert(rst);
0153 }
0154
0155 static int lgm_reset_control_deassert(struct device *dev, struct reset_control *rst)
0156 {
0157     int ret;
0158
0159     ret = reset_control_deassert(rst);
0160     if (ret)
0161         return ret;
0162
0163     return devm_add_action_or_reset(dev, lgm_reset_control_release, rst);
0164 }
0165
0166 static int lgm_pwm_probe(struct platform_device *pdev)
0167 {
0168     struct device *dev = &pdev->dev;
0169     struct reset_control *rst;
0170     struct lgm_pwm_chip *pc;
0171     void __iomem *io_base;
0172     struct clk *clk;
0173     int ret;
0174
0175     pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
0176     if (!pc)
0177         return -ENOMEM;
0178
0179     io_base = devm_platform_ioremap_resource(pdev, 0);
0180     if (IS_ERR(io_base))
0181         return PTR_ERR(io_base);
0182
0183     pc->regmap = devm_regmap_init_mmio(dev, io_base, &lgm_pwm_regmap_config);
0184     if (IS_ERR(pc->regmap))
0185         return dev_err_probe(dev, PTR_ERR(pc->regmap),
0186                      "failed to init register map\n");
0187
0188     clk = devm_clk_get(dev, NULL);
0189     if (IS_ERR(clk))
0190         return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
0191
0192     ret = lgm_clk_enable(dev, clk);
0193     if (ret)
0194         return dev_err_probe(dev, ret, "failed to enable clock\n");
0195
0196     rst = devm_reset_control_get_exclusive(dev, NULL);
0197     if (IS_ERR(rst))
0198         return dev_err_probe(dev, PTR_ERR(rst),
0199                      "failed to get reset control\n");
0200
0201     ret = lgm_reset_control_deassert(dev, rst);
0202     if (ret)
0203         return dev_err_probe(dev, ret, "cannot deassert reset control\n");
0204
0205     pc->chip.dev = dev;
0206     pc->chip.ops = &lgm_pwm_ops;
0207     pc->chip.npwm = 1;
0208
0209     lgm_pwm_init(pc);
0210
0211     ret = devm_pwmchip_add(dev, &pc->chip);
0212     if (ret < 0)
0213         return dev_err_probe(dev, ret, "failed to add PWM chip\n");
0214
0215     return 0;
0216 }
0217
0218 static const struct of_device_id lgm_pwm_of_match[] = {
0219     { .compatible = "intel,lgm-pwm" },
0220     { }
0221 };
0222 MODULE_DEVICE_TABLE(of, lgm_pwm_of_match);
0223
0224 static struct platform_driver lgm_pwm_driver = {
0225     .driver = {
0226         .name = "intel-pwm",
0227         .of_match_table = lgm_pwm_of_match,
0228     },
0229     .probe = lgm_pwm_probe,
0230 };
0231 module_platform_driver(lgm_pwm_driver);
0232
0233 MODULE_LICENSE("GPL v2");