drivers/pwm/pwm-imx27.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * simple driver for PWM (Pulse Width Modulator) controller
0004  *
0005  * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
0006  *
0007  * Limitations:
0008  * - When disabled the output is driven to 0 independent of the configured
0009  *   polarity.
0010  */
0011
0012 #include <linux/bitfield.h>
0013 #include <linux/bitops.h>
0014 #include <linux/clk.h>
0015 #include <linux/delay.h>
0016 #include <linux/err.h>
0017 #include <linux/io.h>
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/of.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pwm.h>
0023 #include <linux/slab.h>
0024
0025 #define MX3_PWMCR           0x00    /* PWM Control Register */
0026 #define MX3_PWMSR           0x04    /* PWM Status Register */
0027 #define MX3_PWMSAR          0x0C    /* PWM Sample Register */
0028 #define MX3_PWMPR           0x10    /* PWM Period Register */
0029
0030 #define MX3_PWMCR_FWM           GENMASK(27, 26)
0031 #define MX3_PWMCR_STOPEN        BIT(25)
0032 #define MX3_PWMCR_DOZEN         BIT(24)
0033 #define MX3_PWMCR_WAITEN        BIT(23)
0034 #define MX3_PWMCR_DBGEN         BIT(22)
0035 #define MX3_PWMCR_BCTR          BIT(21)
0036 #define MX3_PWMCR_HCTR          BIT(20)
0037
0038 #define MX3_PWMCR_POUTC         GENMASK(19, 18)
0039 #define MX3_PWMCR_POUTC_NORMAL      0
0040 #define MX3_PWMCR_POUTC_INVERTED    1
0041 #define MX3_PWMCR_POUTC_OFF     2
0042
0043 #define MX3_PWMCR_CLKSRC        GENMASK(17, 16)
0044 #define MX3_PWMCR_CLKSRC_OFF        0
0045 #define MX3_PWMCR_CLKSRC_IPG        1
0046 #define MX3_PWMCR_CLKSRC_IPG_HIGH   2
0047 #define MX3_PWMCR_CLKSRC_IPG_32K    3
0048
0049 #define MX3_PWMCR_PRESCALER     GENMASK(15, 4)
0050
0051 #define MX3_PWMCR_SWR           BIT(3)
0052
0053 #define MX3_PWMCR_REPEAT        GENMASK(2, 1)
0054 #define MX3_PWMCR_REPEAT_1X     0
0055 #define MX3_PWMCR_REPEAT_2X     1
0056 #define MX3_PWMCR_REPEAT_4X     2
0057 #define MX3_PWMCR_REPEAT_8X     3
0058
0059 #define MX3_PWMCR_EN            BIT(0)
0060
0061 #define MX3_PWMSR_FWE           BIT(6)
0062 #define MX3_PWMSR_CMP           BIT(5)
0063 #define MX3_PWMSR_ROV           BIT(4)
0064 #define MX3_PWMSR_FE            BIT(3)
0065
0066 #define MX3_PWMSR_FIFOAV        GENMASK(2, 0)
0067 #define MX3_PWMSR_FIFOAV_EMPTY      0
0068 #define MX3_PWMSR_FIFOAV_1WORD      1
0069 #define MX3_PWMSR_FIFOAV_2WORDS     2
0070 #define MX3_PWMSR_FIFOAV_3WORDS     3
0071 #define MX3_PWMSR_FIFOAV_4WORDS     4
0072
0073 #define MX3_PWMCR_PRESCALER_SET(x)  FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
0074 #define MX3_PWMCR_PRESCALER_GET(x)  (FIELD_GET(MX3_PWMCR_PRESCALER, \
0075                            (x)) + 1)
0076
0077 #define MX3_PWM_SWR_LOOP        5
0078
0079 /* PWMPR register value of 0xffff has the same effect as 0xfffe */
0080 #define MX3_PWMPR_MAX           0xfffe
0081
0082 struct pwm_imx27_chip {
0083     struct clk  *clk_ipg;
0084     struct clk  *clk_per;
0085     void __iomem    *mmio_base;
0086     struct pwm_chip chip;
0087
0088     /*
0089      * The driver cannot read the current duty cycle from the hardware if
0090      * the hardware is disabled. Cache the last programmed duty cycle
0091      * value to return in that case.
0092      */
0093     unsigned int duty_cycle;
0094 };
0095
0096 #define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip)
0097
0098 static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
0099 {
0100     int ret;
0101
0102     ret = clk_prepare_enable(imx->clk_ipg);
0103     if (ret)
0104         return ret;
0105
0106     ret = clk_prepare_enable(imx->clk_per);
0107     if (ret) {
0108         clk_disable_unprepare(imx->clk_ipg);
0109         return ret;
0110     }
0111
0112     return 0;
0113 }
0114
0115 static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
0116 {
0117     clk_disable_unprepare(imx->clk_per);
0118     clk_disable_unprepare(imx->clk_ipg);
0119 }
0120
0121 static void pwm_imx27_get_state(struct pwm_chip *chip,
0122                 struct pwm_device *pwm, struct pwm_state *state)
0123 {
0124     struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
0125     u32 period, prescaler, pwm_clk, val;
0126     u64 tmp;
0127     int ret;
0128
0129     ret = pwm_imx27_clk_prepare_enable(imx);
0130     if (ret < 0)
0131         return;
0132
0133     val = readl(imx->mmio_base + MX3_PWMCR);
0134
0135     if (val & MX3_PWMCR_EN)
0136         state->enabled = true;
0137     else
0138         state->enabled = false;
0139
0140     switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
0141     case MX3_PWMCR_POUTC_NORMAL:
0142         state->polarity = PWM_POLARITY_NORMAL;
0143         break;
0144     case MX3_PWMCR_POUTC_INVERTED:
0145         state->polarity = PWM_POLARITY_INVERSED;
0146         break;
0147     default:
0148         dev_warn(chip->dev, "can't set polarity, output disconnected");
0149     }
0150
0151     prescaler = MX3_PWMCR_PRESCALER_GET(val);
0152     pwm_clk = clk_get_rate(imx->clk_per);
0153     val = readl(imx->mmio_base + MX3_PWMPR);
0154     period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
0155
0156     /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
0157     tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
0158     state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);
0159
0160     /*
0161      * PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
0162      * use the cached value.
0163      */
0164     if (state->enabled)
0165         val = readl(imx->mmio_base + MX3_PWMSAR);
0166     else
0167         val = imx->duty_cycle;
0168
0169     tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
0170     state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
0171
0172     pwm_imx27_clk_disable_unprepare(imx);
0173 }
0174
0175 static void pwm_imx27_sw_reset(struct pwm_chip *chip)
0176 {
0177     struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
0178     struct device *dev = chip->dev;
0179     int wait_count = 0;
0180     u32 cr;
0181
0182     writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
0183     do {
0184         usleep_range(200, 1000);
0185         cr = readl(imx->mmio_base + MX3_PWMCR);
0186     } while ((cr & MX3_PWMCR_SWR) &&
0187          (wait_count++ < MX3_PWM_SWR_LOOP));
0188
0189     if (cr & MX3_PWMCR_SWR)
0190         dev_warn(dev, "software reset timeout\n");
0191 }
0192
0193 static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
0194                      struct pwm_device *pwm)
0195 {
0196     struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
0197     struct device *dev = chip->dev;
0198     unsigned int period_ms;
0199     int fifoav;
0200     u32 sr;
0201
0202     sr = readl(imx->mmio_base + MX3_PWMSR);
0203     fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
0204     if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
0205         period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
0206                      NSEC_PER_MSEC);
0207         msleep(period_ms);
0208
0209         sr = readl(imx->mmio_base + MX3_PWMSR);
0210         if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
0211             dev_warn(dev, "there is no free FIFO slot\n");
0212     }
0213 }
0214
0215 static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0216                const struct pwm_state *state)
0217 {
0218     unsigned long period_cycles, duty_cycles, prescale;
0219     struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
0220     struct pwm_state cstate;
0221     unsigned long long c;
0222     unsigned long long clkrate;
0223     int ret;
0224     u32 cr;
0225
0226     pwm_get_state(pwm, &cstate);
0227
0228     clkrate = clk_get_rate(imx->clk_per);
0229     c = clkrate * state->period;
0230
0231     do_div(c, NSEC_PER_SEC);
0232     period_cycles = c;
0233
0234     prescale = period_cycles / 0x10000 + 1;
0235
0236     period_cycles /= prescale;
0237     c = clkrate * state->duty_cycle;
0238     do_div(c, NSEC_PER_SEC);
0239     duty_cycles = c;
0240     duty_cycles /= prescale;
0241
0242     /*
0243      * according to imx pwm RM, the real period value should be PERIOD
0244      * value in PWMPR plus 2.
0245      */
0246     if (period_cycles > 2)
0247         period_cycles -= 2;
0248     else
0249         period_cycles = 0;
0250
0251     /*
0252      * Wait for a free FIFO slot if the PWM is already enabled, and flush
0253      * the FIFO if the PWM was disabled and is about to be enabled.
0254      */
0255     if (cstate.enabled) {
0256         pwm_imx27_wait_fifo_slot(chip, pwm);
0257     } else {
0258         ret = pwm_imx27_clk_prepare_enable(imx);
0259         if (ret)
0260             return ret;
0261
0262         pwm_imx27_sw_reset(chip);
0263     }
0264
0265     writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
0266     writel(period_cycles, imx->mmio_base + MX3_PWMPR);
0267
0268     /*
0269      * Store the duty cycle for future reference in cases where the
0270      * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
0271      */
0272     imx->duty_cycle = duty_cycles;
0273
0274     cr = MX3_PWMCR_PRESCALER_SET(prescale) |
0275          MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
0276          FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
0277          MX3_PWMCR_DBGEN;
0278
0279     if (state->polarity == PWM_POLARITY_INVERSED)
0280         cr |= FIELD_PREP(MX3_PWMCR_POUTC,
0281                 MX3_PWMCR_POUTC_INVERTED);
0282
0283     if (state->enabled)
0284         cr |= MX3_PWMCR_EN;
0285
0286     writel(cr, imx->mmio_base + MX3_PWMCR);
0287
0288     if (!state->enabled)
0289         pwm_imx27_clk_disable_unprepare(imx);
0290
0291     return 0;
0292 }
0293
0294 static const struct pwm_ops pwm_imx27_ops = {
0295     .apply = pwm_imx27_apply,
0296     .get_state = pwm_imx27_get_state,
0297     .owner = THIS_MODULE,
0298 };
0299
0300 static const struct of_device_id pwm_imx27_dt_ids[] = {
0301     { .compatible = "fsl,imx27-pwm", },
0302     { /* sentinel */ }
0303 };
0304 MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
0305
0306 static int pwm_imx27_probe(struct platform_device *pdev)
0307 {
0308     struct pwm_imx27_chip *imx;
0309     int ret;
0310     u32 pwmcr;
0311
0312     imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
0313     if (imx == NULL)
0314         return -ENOMEM;
0315
0316     imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
0317     if (IS_ERR(imx->clk_ipg))
0318         return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg),
0319                      "getting ipg clock failed\n");
0320
0321     imx->clk_per = devm_clk_get(&pdev->dev, "per");
0322     if (IS_ERR(imx->clk_per))
0323         return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per),
0324                      "failed to get peripheral clock\n");
0325
0326     imx->chip.ops = &pwm_imx27_ops;
0327     imx->chip.dev = &pdev->dev;
0328     imx->chip.npwm = 1;
0329
0330     imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
0331     if (IS_ERR(imx->mmio_base))
0332         return PTR_ERR(imx->mmio_base);
0333
0334     ret = pwm_imx27_clk_prepare_enable(imx);
0335     if (ret)
0336         return ret;
0337
0338     /* keep clks on if pwm is running */
0339     pwmcr = readl(imx->mmio_base + MX3_PWMCR);
0340     if (!(pwmcr & MX3_PWMCR_EN))
0341         pwm_imx27_clk_disable_unprepare(imx);
0342
0343     return devm_pwmchip_add(&pdev->dev, &imx->chip);
0344 }
0345
0346 static struct platform_driver imx_pwm_driver = {
0347     .driver = {
0348         .name = "pwm-imx27",
0349         .of_match_table = pwm_imx27_dt_ids,
0350     },
0351     .probe = pwm_imx27_probe,
0352 };
0353 module_platform_driver(imx_pwm_driver);
0354
0355 MODULE_LICENSE("GPL v2");
0356 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");