drivers/pwm/pwm-img.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Imagination Technologies Pulse Width Modulator driver
0004  *
0005  * Copyright (c) 2014-2015, Imagination Technologies
0006  *
0007  * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/of_device.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/pwm.h>
0020 #include <linux/regmap.h>
0021 #include <linux/slab.h>
0022
0023 /* PWM registers */
0024 #define PWM_CTRL_CFG                0x0000
0025 #define PWM_CTRL_CFG_NO_SUB_DIV         0
0026 #define PWM_CTRL_CFG_SUB_DIV0           1
0027 #define PWM_CTRL_CFG_SUB_DIV1           2
0028 #define PWM_CTRL_CFG_SUB_DIV0_DIV1      3
0029 #define PWM_CTRL_CFG_DIV_SHIFT(ch)      ((ch) * 2 + 4)
0030 #define PWM_CTRL_CFG_DIV_MASK           0x3
0031
0032 #define PWM_CH_CFG(ch)              (0x4 + (ch) * 4)
0033 #define PWM_CH_CFG_TMBASE_SHIFT         0
0034 #define PWM_CH_CFG_DUTY_SHIFT           16
0035
0036 #define PERIP_PWM_PDM_CONTROL           0x0140
0037 #define PERIP_PWM_PDM_CONTROL_CH_MASK       0x1
0038 #define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch)  ((ch) * 4)
0039
0040 #define IMG_PWM_PM_TIMEOUT          1000 /* ms */
0041
0042 /*
0043  * PWM period is specified with a timebase register,
0044  * in number of step periods. The PWM duty cycle is also
0045  * specified in step periods, in the [0, $timebase] range.
0046  * In other words, the timebase imposes the duty cycle
0047  * resolution. Therefore, let's constraint the timebase to
0048  * a minimum value to allow a sane range of duty cycle values.
0049  * Imposing a minimum timebase, will impose a maximum PWM frequency.
0050  *
0051  * The value chosen is completely arbitrary.
0052  */
0053 #define MIN_TMBASE_STEPS            16
0054
0055 #define IMG_PWM_NPWM                4
0056
0057 struct img_pwm_soc_data {
0058     u32 max_timebase;
0059 };
0060
0061 struct img_pwm_chip {
0062     struct device   *dev;
0063     struct pwm_chip chip;
0064     struct clk  *pwm_clk;
0065     struct clk  *sys_clk;
0066     void __iomem    *base;
0067     struct regmap   *periph_regs;
0068     int     max_period_ns;
0069     int     min_period_ns;
0070     const struct img_pwm_soc_data   *data;
0071     u32     suspend_ctrl_cfg;
0072     u32     suspend_ch_cfg[IMG_PWM_NPWM];
0073 };
0074
0075 static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
0076 {
0077     return container_of(chip, struct img_pwm_chip, chip);
0078 }
0079
0080 static inline void img_pwm_writel(struct img_pwm_chip *imgchip,
0081                   u32 reg, u32 val)
0082 {
0083     writel(val, imgchip->base + reg);
0084 }
0085
0086 static inline u32 img_pwm_readl(struct img_pwm_chip *imgchip, u32 reg)
0087 {
0088     return readl(imgchip->base + reg);
0089 }
0090
0091 static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
0092               int duty_ns, int period_ns)
0093 {
0094     u32 val, div, duty, timebase;
0095     unsigned long mul, output_clk_hz, input_clk_hz;
0096     struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
0097     unsigned int max_timebase = imgchip->data->max_timebase;
0098     int ret;
0099
0100     if (period_ns < imgchip->min_period_ns ||
0101         period_ns > imgchip->max_period_ns) {
0102         dev_err(chip->dev, "configured period not in range\n");
0103         return -ERANGE;
0104     }
0105
0106     input_clk_hz = clk_get_rate(imgchip->pwm_clk);
0107     output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
0108
0109     mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
0110     if (mul <= max_timebase) {
0111         div = PWM_CTRL_CFG_NO_SUB_DIV;
0112         timebase = DIV_ROUND_UP(mul, 1);
0113     } else if (mul <= max_timebase * 8) {
0114         div = PWM_CTRL_CFG_SUB_DIV0;
0115         timebase = DIV_ROUND_UP(mul, 8);
0116     } else if (mul <= max_timebase * 64) {
0117         div = PWM_CTRL_CFG_SUB_DIV1;
0118         timebase = DIV_ROUND_UP(mul, 64);
0119     } else if (mul <= max_timebase * 512) {
0120         div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
0121         timebase = DIV_ROUND_UP(mul, 512);
0122     } else {
0123         dev_err(chip->dev,
0124             "failed to configure timebase steps/divider value\n");
0125         return -EINVAL;
0126     }
0127
0128     duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
0129
0130     ret = pm_runtime_resume_and_get(chip->dev);
0131     if (ret < 0)
0132         return ret;
0133
0134     val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
0135     val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
0136     val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
0137         PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
0138     img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
0139
0140     val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
0141           (timebase << PWM_CH_CFG_TMBASE_SHIFT);
0142     img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);
0143
0144     pm_runtime_mark_last_busy(chip->dev);
0145     pm_runtime_put_autosuspend(chip->dev);
0146
0147     return 0;
0148 }
0149
0150 static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
0151 {
0152     u32 val;
0153     struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
0154     int ret;
0155
0156     ret = pm_runtime_resume_and_get(chip->dev);
0157     if (ret < 0)
0158         return ret;
0159
0160     val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
0161     val |= BIT(pwm->hwpwm);
0162     img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
0163
0164     regmap_update_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,
0165                PERIP_PWM_PDM_CONTROL_CH_MASK <<
0166                PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
0167
0168     return 0;
0169 }
0170
0171 static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
0172 {
0173     u32 val;
0174     struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
0175
0176     val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
0177     val &= ~BIT(pwm->hwpwm);
0178     img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
0179
0180     pm_runtime_mark_last_busy(chip->dev);
0181     pm_runtime_put_autosuspend(chip->dev);
0182 }
0183
0184 static int img_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0185              const struct pwm_state *state)
0186 {
0187     int err;
0188
0189     if (state->polarity != PWM_POLARITY_NORMAL)
0190         return -EINVAL;
0191
0192     if (!state->enabled) {
0193         if (pwm->state.enabled)
0194             img_pwm_disable(chip, pwm);
0195
0196         return 0;
0197     }
0198
0199     err = img_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
0200     if (err)
0201         return err;
0202
0203     if (!pwm->state.enabled)
0204         err = img_pwm_enable(chip, pwm);
0205
0206     return err;
0207 }
0208
0209 static const struct pwm_ops img_pwm_ops = {
0210     .apply = img_pwm_apply,
0211     .owner = THIS_MODULE,
0212 };
0213
0214 static const struct img_pwm_soc_data pistachio_pwm = {
0215     .max_timebase = 255,
0216 };
0217
0218 static const struct of_device_id img_pwm_of_match[] = {
0219     {
0220         .compatible = "img,pistachio-pwm",
0221         .data = &pistachio_pwm,
0222     },
0223     { }
0224 };
0225 MODULE_DEVICE_TABLE(of, img_pwm_of_match);
0226
0227 static int img_pwm_runtime_suspend(struct device *dev)
0228 {
0229     struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
0230
0231     clk_disable_unprepare(imgchip->pwm_clk);
0232     clk_disable_unprepare(imgchip->sys_clk);
0233
0234     return 0;
0235 }
0236
0237 static int img_pwm_runtime_resume(struct device *dev)
0238 {
0239     struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
0240     int ret;
0241
0242     ret = clk_prepare_enable(imgchip->sys_clk);
0243     if (ret < 0) {
0244         dev_err(dev, "could not prepare or enable sys clock\n");
0245         return ret;
0246     }
0247
0248     ret = clk_prepare_enable(imgchip->pwm_clk);
0249     if (ret < 0) {
0250         dev_err(dev, "could not prepare or enable pwm clock\n");
0251         clk_disable_unprepare(imgchip->sys_clk);
0252         return ret;
0253     }
0254
0255     return 0;
0256 }
0257
0258 static int img_pwm_probe(struct platform_device *pdev)
0259 {
0260     int ret;
0261     u64 val;
0262     unsigned long clk_rate;
0263     struct img_pwm_chip *imgchip;
0264     const struct of_device_id *of_dev_id;
0265
0266     imgchip = devm_kzalloc(&pdev->dev, sizeof(*imgchip), GFP_KERNEL);
0267     if (!imgchip)
0268         return -ENOMEM;
0269
0270     imgchip->dev = &pdev->dev;
0271
0272     imgchip->base = devm_platform_ioremap_resource(pdev, 0);
0273     if (IS_ERR(imgchip->base))
0274         return PTR_ERR(imgchip->base);
0275
0276     of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
0277     if (!of_dev_id)
0278         return -ENODEV;
0279     imgchip->data = of_dev_id->data;
0280
0281     imgchip->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
0282                                    "img,cr-periph");
0283     if (IS_ERR(imgchip->periph_regs))
0284         return PTR_ERR(imgchip->periph_regs);
0285
0286     imgchip->sys_clk = devm_clk_get(&pdev->dev, "sys");
0287     if (IS_ERR(imgchip->sys_clk)) {
0288         dev_err(&pdev->dev, "failed to get system clock\n");
0289         return PTR_ERR(imgchip->sys_clk);
0290     }
0291
0292     imgchip->pwm_clk = devm_clk_get(&pdev->dev, "imgchip");
0293     if (IS_ERR(imgchip->pwm_clk)) {
0294         dev_err(&pdev->dev, "failed to get imgchip clock\n");
0295         return PTR_ERR(imgchip->pwm_clk);
0296     }
0297
0298     platform_set_drvdata(pdev, imgchip);
0299
0300     pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
0301     pm_runtime_use_autosuspend(&pdev->dev);
0302     pm_runtime_enable(&pdev->dev);
0303     if (!pm_runtime_enabled(&pdev->dev)) {
0304         ret = img_pwm_runtime_resume(&pdev->dev);
0305         if (ret)
0306             goto err_pm_disable;
0307     }
0308
0309     clk_rate = clk_get_rate(imgchip->pwm_clk);
0310     if (!clk_rate) {
0311         dev_err(&pdev->dev, "imgchip clock has no frequency\n");
0312         ret = -EINVAL;
0313         goto err_suspend;
0314     }
0315
0316     /* The maximum input clock divider is 512 */
0317     val = (u64)NSEC_PER_SEC * 512 * imgchip->data->max_timebase;
0318     do_div(val, clk_rate);
0319     imgchip->max_period_ns = val;
0320
0321     val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
0322     do_div(val, clk_rate);
0323     imgchip->min_period_ns = val;
0324
0325     imgchip->chip.dev = &pdev->dev;
0326     imgchip->chip.ops = &img_pwm_ops;
0327     imgchip->chip.npwm = IMG_PWM_NPWM;
0328
0329     ret = pwmchip_add(&imgchip->chip);
0330     if (ret < 0) {
0331         dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
0332         goto err_suspend;
0333     }
0334
0335     return 0;
0336
0337 err_suspend:
0338     if (!pm_runtime_enabled(&pdev->dev))
0339         img_pwm_runtime_suspend(&pdev->dev);
0340 err_pm_disable:
0341     pm_runtime_disable(&pdev->dev);
0342     pm_runtime_dont_use_autosuspend(&pdev->dev);
0343     return ret;
0344 }
0345
0346 static int img_pwm_remove(struct platform_device *pdev)
0347 {
0348     struct img_pwm_chip *imgchip = platform_get_drvdata(pdev);
0349
0350     pm_runtime_disable(&pdev->dev);
0351     if (!pm_runtime_status_suspended(&pdev->dev))
0352         img_pwm_runtime_suspend(&pdev->dev);
0353
0354     pwmchip_remove(&imgchip->chip);
0355
0356     return 0;
0357 }
0358
0359 #ifdef CONFIG_PM_SLEEP
0360 static int img_pwm_suspend(struct device *dev)
0361 {
0362     struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
0363     int i, ret;
0364
0365     if (pm_runtime_status_suspended(dev)) {
0366         ret = img_pwm_runtime_resume(dev);
0367         if (ret)
0368             return ret;
0369     }
0370
0371     for (i = 0; i < imgchip->chip.npwm; i++)
0372         imgchip->suspend_ch_cfg[i] = img_pwm_readl(imgchip,
0373                                PWM_CH_CFG(i));
0374
0375     imgchip->suspend_ctrl_cfg = img_pwm_readl(imgchip, PWM_CTRL_CFG);
0376
0377     img_pwm_runtime_suspend(dev);
0378
0379     return 0;
0380 }
0381
0382 static int img_pwm_resume(struct device *dev)
0383 {
0384     struct img_pwm_chip *imgchip = dev_get_drvdata(dev);
0385     int ret;
0386     int i;
0387
0388     ret = img_pwm_runtime_resume(dev);
0389     if (ret)
0390         return ret;
0391
0392     for (i = 0; i < imgchip->chip.npwm; i++)
0393         img_pwm_writel(imgchip, PWM_CH_CFG(i),
0394                    imgchip->suspend_ch_cfg[i]);
0395
0396     img_pwm_writel(imgchip, PWM_CTRL_CFG, imgchip->suspend_ctrl_cfg);
0397
0398     for (i = 0; i < imgchip->chip.npwm; i++)
0399         if (imgchip->suspend_ctrl_cfg & BIT(i))
0400             regmap_update_bits(imgchip->periph_regs,
0401                        PERIP_PWM_PDM_CONTROL,
0402                        PERIP_PWM_PDM_CONTROL_CH_MASK <<
0403                        PERIP_PWM_PDM_CONTROL_CH_SHIFT(i),
0404                        0);
0405
0406     if (pm_runtime_status_suspended(dev))
0407         img_pwm_runtime_suspend(dev);
0408
0409     return 0;
0410 }
0411 #endif /* CONFIG_PM */
0412
0413 static const struct dev_pm_ops img_pwm_pm_ops = {
0414     SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
0415                img_pwm_runtime_resume,
0416                NULL)
0417     SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
0418 };
0419
0420 static struct platform_driver img_pwm_driver = {
0421     .driver = {
0422         .name = "img-pwm",
0423         .pm = &img_pwm_pm_ops,
0424         .of_match_table = img_pwm_of_match,
0425     },
0426     .probe = img_pwm_probe,
0427     .remove = img_pwm_remove,
0428 };
0429 module_platform_driver(img_pwm_driver);
0430
0431 MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
0432 MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
0433 MODULE_LICENSE("GPL v2");