drivers/pwm/pwm-hibvt.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * PWM Controller Driver for HiSilicon BVT SoCs
0004  *
0005  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
0006  */
0007
0008 #include <linux/bitops.h>
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pwm.h>
0016 #include <linux/reset.h>
0017
0018 #define PWM_CFG0_ADDR(x)    (((x) * 0x20) + 0x0)
0019 #define PWM_CFG1_ADDR(x)    (((x) * 0x20) + 0x4)
0020 #define PWM_CFG2_ADDR(x)    (((x) * 0x20) + 0x8)
0021 #define PWM_CTRL_ADDR(x)    (((x) * 0x20) + 0xC)
0022
0023 #define PWM_ENABLE_SHIFT    0
0024 #define PWM_ENABLE_MASK     BIT(0)
0025
0026 #define PWM_POLARITY_SHIFT  1
0027 #define PWM_POLARITY_MASK   BIT(1)
0028
0029 #define PWM_KEEP_SHIFT      2
0030 #define PWM_KEEP_MASK       BIT(2)
0031
0032 #define PWM_PERIOD_MASK     GENMASK(31, 0)
0033 #define PWM_DUTY_MASK       GENMASK(31, 0)
0034
0035 struct hibvt_pwm_chip {
0036     struct pwm_chip chip;
0037     struct clk *clk;
0038     void __iomem *base;
0039     struct reset_control *rstc;
0040     const struct hibvt_pwm_soc *soc;
0041 };
0042
0043 struct hibvt_pwm_soc {
0044     u32 num_pwms;
0045     bool quirk_force_enable;
0046 };
0047
0048 static const struct hibvt_pwm_soc hi3516cv300_soc_info = {
0049     .num_pwms = 4,
0050 };
0051
0052 static const struct hibvt_pwm_soc hi3519v100_soc_info = {
0053     .num_pwms = 8,
0054 };
0055
0056 static const struct hibvt_pwm_soc hi3559v100_shub_soc_info = {
0057     .num_pwms = 8,
0058     .quirk_force_enable = true,
0059 };
0060
0061 static const struct hibvt_pwm_soc hi3559v100_soc_info = {
0062     .num_pwms = 2,
0063     .quirk_force_enable = true,
0064 };
0065
0066 static inline struct hibvt_pwm_chip *to_hibvt_pwm_chip(struct pwm_chip *chip)
0067 {
0068     return container_of(chip, struct hibvt_pwm_chip, chip);
0069 }
0070
0071 static void hibvt_pwm_set_bits(void __iomem *base, u32 offset,
0072                     u32 mask, u32 data)
0073 {
0074     void __iomem *address = base + offset;
0075     u32 value;
0076
0077     value = readl(address);
0078     value &= ~mask;
0079     value |= (data & mask);
0080     writel(value, address);
0081 }
0082
0083 static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
0084 {
0085     struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
0086
0087     hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
0088             PWM_ENABLE_MASK, 0x1);
0089 }
0090
0091 static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
0092 {
0093     struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
0094
0095     hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
0096             PWM_ENABLE_MASK, 0x0);
0097 }
0098
0099 static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
0100                     int duty_cycle_ns, int period_ns)
0101 {
0102     struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
0103     u32 freq, period, duty;
0104
0105     freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
0106
0107     period = div_u64(freq * period_ns, 1000);
0108     duty = div_u64(period * duty_cycle_ns, period_ns);
0109
0110     hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),
0111             PWM_PERIOD_MASK, period);
0112
0113     hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),
0114             PWM_DUTY_MASK, duty);
0115 }
0116
0117 static void hibvt_pwm_set_polarity(struct pwm_chip *chip,
0118                     struct pwm_device *pwm,
0119                     enum pwm_polarity polarity)
0120 {
0121     struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
0122
0123     if (polarity == PWM_POLARITY_INVERSED)
0124         hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
0125                 PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT));
0126     else
0127         hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
0128                 PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT));
0129 }
0130
0131 static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
0132                 struct pwm_state *state)
0133 {
0134     struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
0135     void __iomem *base;
0136     u32 freq, value;
0137
0138     freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
0139     base = hi_pwm_chip->base;
0140
0141     value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));
0142     state->period = div_u64(value * 1000, freq);
0143
0144     value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));
0145     state->duty_cycle = div_u64(value * 1000, freq);
0146
0147     value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
0148     state->enabled = (PWM_ENABLE_MASK & value);
0149 }
0150
0151 static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0152                const struct pwm_state *state)
0153 {
0154     struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
0155
0156     if (state->polarity != pwm->state.polarity)
0157         hibvt_pwm_set_polarity(chip, pwm, state->polarity);
0158
0159     if (state->period != pwm->state.period ||
0160         state->duty_cycle != pwm->state.duty_cycle) {
0161         hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);
0162
0163         /*
0164          * Some implementations require the PWM to be enabled twice
0165          * each time the duty cycle is refreshed.
0166          */
0167         if (hi_pwm_chip->soc->quirk_force_enable && state->enabled)
0168             hibvt_pwm_enable(chip, pwm);
0169     }
0170
0171     if (state->enabled != pwm->state.enabled) {
0172         if (state->enabled)
0173             hibvt_pwm_enable(chip, pwm);
0174         else
0175             hibvt_pwm_disable(chip, pwm);
0176     }
0177
0178     return 0;
0179 }
0180
0181 static const struct pwm_ops hibvt_pwm_ops = {
0182     .get_state = hibvt_pwm_get_state,
0183     .apply = hibvt_pwm_apply,
0184
0185     .owner = THIS_MODULE,
0186 };
0187
0188 static int hibvt_pwm_probe(struct platform_device *pdev)
0189 {
0190     const struct hibvt_pwm_soc *soc =
0191                 of_device_get_match_data(&pdev->dev);
0192     struct hibvt_pwm_chip *pwm_chip;
0193     int ret, i;
0194
0195     pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL);
0196     if (pwm_chip == NULL)
0197         return -ENOMEM;
0198
0199     pwm_chip->clk = devm_clk_get(&pdev->dev, NULL);
0200     if (IS_ERR(pwm_chip->clk)) {
0201         dev_err(&pdev->dev, "getting clock failed with %ld\n",
0202                 PTR_ERR(pwm_chip->clk));
0203         return PTR_ERR(pwm_chip->clk);
0204     }
0205
0206     pwm_chip->chip.ops = &hibvt_pwm_ops;
0207     pwm_chip->chip.dev = &pdev->dev;
0208     pwm_chip->chip.npwm = soc->num_pwms;
0209     pwm_chip->soc = soc;
0210
0211     pwm_chip->base = devm_platform_ioremap_resource(pdev, 0);
0212     if (IS_ERR(pwm_chip->base))
0213         return PTR_ERR(pwm_chip->base);
0214
0215     ret = clk_prepare_enable(pwm_chip->clk);
0216     if (ret < 0)
0217         return ret;
0218
0219     pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
0220     if (IS_ERR(pwm_chip->rstc)) {
0221         clk_disable_unprepare(pwm_chip->clk);
0222         return PTR_ERR(pwm_chip->rstc);
0223     }
0224
0225     reset_control_assert(pwm_chip->rstc);
0226     msleep(30);
0227     reset_control_deassert(pwm_chip->rstc);
0228
0229     ret = pwmchip_add(&pwm_chip->chip);
0230     if (ret < 0) {
0231         clk_disable_unprepare(pwm_chip->clk);
0232         return ret;
0233     }
0234
0235     for (i = 0; i < pwm_chip->chip.npwm; i++) {
0236         hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i),
0237                 PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT));
0238     }
0239
0240     platform_set_drvdata(pdev, pwm_chip);
0241
0242     return 0;
0243 }
0244
0245 static int hibvt_pwm_remove(struct platform_device *pdev)
0246 {
0247     struct hibvt_pwm_chip *pwm_chip;
0248
0249     pwm_chip = platform_get_drvdata(pdev);
0250
0251     pwmchip_remove(&pwm_chip->chip);
0252
0253     reset_control_assert(pwm_chip->rstc);
0254     msleep(30);
0255     reset_control_deassert(pwm_chip->rstc);
0256
0257     clk_disable_unprepare(pwm_chip->clk);
0258
0259     return 0;
0260 }
0261
0262 static const struct of_device_id hibvt_pwm_of_match[] = {
0263     { .compatible = "hisilicon,hi3516cv300-pwm",
0264       .data = &hi3516cv300_soc_info },
0265     { .compatible = "hisilicon,hi3519v100-pwm",
0266       .data = &hi3519v100_soc_info },
0267     { .compatible = "hisilicon,hi3559v100-shub-pwm",
0268       .data = &hi3559v100_shub_soc_info },
0269     { .compatible = "hisilicon,hi3559v100-pwm",
0270       .data = &hi3559v100_soc_info },
0271     {  }
0272 };
0273 MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match);
0274
0275 static struct platform_driver hibvt_pwm_driver = {
0276     .driver = {
0277         .name = "hibvt-pwm",
0278         .of_match_table = hibvt_pwm_of_match,
0279     },
0280     .probe = hibvt_pwm_probe,
0281     .remove = hibvt_pwm_remove,
0282 };
0283 module_platform_driver(hibvt_pwm_driver);
0284
0285 MODULE_AUTHOR("Jian Yuan");
0286 MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver");
0287 MODULE_LICENSE("GPL");