drivers/pwm/pwm-fsl-ftm.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Freescale FlexTimer Module (FTM) PWM Driver
0004  *
0005  *  Copyright 2012-2013 Freescale Semiconductor, Inc.
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/mutex.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_device.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm.h>
0018 #include <linux/pwm.h>
0019 #include <linux/regmap.h>
0020 #include <linux/slab.h>
0021 #include <linux/fsl/ftm.h>
0022
0023 #define FTM_SC_CLK(c)   (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
0024
0025 enum fsl_pwm_clk {
0026     FSL_PWM_CLK_SYS,
0027     FSL_PWM_CLK_FIX,
0028     FSL_PWM_CLK_EXT,
0029     FSL_PWM_CLK_CNTEN,
0030     FSL_PWM_CLK_MAX
0031 };
0032
0033 struct fsl_ftm_soc {
0034     bool has_enable_bits;
0035 };
0036
0037 struct fsl_pwm_periodcfg {
0038     enum fsl_pwm_clk clk_select;
0039     unsigned int clk_ps;
0040     unsigned int mod_period;
0041 };
0042
0043 struct fsl_pwm_chip {
0044     struct pwm_chip chip;
0045     struct mutex lock;
0046     struct regmap *regmap;
0047
0048     /* This value is valid iff a pwm is running */
0049     struct fsl_pwm_periodcfg period;
0050
0051     struct clk *ipg_clk;
0052     struct clk *clk[FSL_PWM_CLK_MAX];
0053
0054     const struct fsl_ftm_soc *soc;
0055 };
0056
0057 static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
0058 {
0059     return container_of(chip, struct fsl_pwm_chip, chip);
0060 }
0061
0062 static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
0063 {
0064     u32 val;
0065
0066     regmap_read(fpc->regmap, FTM_FMS, &val);
0067     if (val & FTM_FMS_WPEN)
0068         regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS,
0069                    FTM_MODE_WPDIS);
0070 }
0071
0072 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
0073 {
0074     regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN);
0075 }
0076
0077 static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
0078                     const struct fsl_pwm_periodcfg *b)
0079 {
0080     if (a->clk_select != b->clk_select)
0081         return false;
0082     if (a->clk_ps != b->clk_ps)
0083         return false;
0084     if (a->mod_period != b->mod_period)
0085         return false;
0086     return true;
0087 }
0088
0089 static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
0090 {
0091     int ret;
0092     struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
0093
0094     ret = clk_prepare_enable(fpc->ipg_clk);
0095     if (!ret && fpc->soc->has_enable_bits) {
0096         mutex_lock(&fpc->lock);
0097         regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
0098                    BIT(pwm->hwpwm + 16));
0099         mutex_unlock(&fpc->lock);
0100     }
0101
0102     return ret;
0103 }
0104
0105 static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
0106 {
0107     struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
0108
0109     if (fpc->soc->has_enable_bits) {
0110         mutex_lock(&fpc->lock);
0111         regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
0112                    0);
0113         mutex_unlock(&fpc->lock);
0114     }
0115
0116     clk_disable_unprepare(fpc->ipg_clk);
0117 }
0118
0119 static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
0120                       unsigned int ticks)
0121 {
0122     unsigned long rate;
0123     unsigned long long exval;
0124
0125     rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
0126     exval = ticks;
0127     exval *= 1000000000UL;
0128     do_div(exval, rate >> fpc->period.clk_ps);
0129     return exval;
0130 }
0131
0132 static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
0133                      unsigned int period_ns,
0134                      enum fsl_pwm_clk index,
0135                      struct fsl_pwm_periodcfg *periodcfg
0136                      )
0137 {
0138     unsigned long long c;
0139     unsigned int ps;
0140
0141     c = clk_get_rate(fpc->clk[index]);
0142     c = c * period_ns;
0143     do_div(c, 1000000000UL);
0144
0145     if (c == 0)
0146         return false;
0147
0148     for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
0149         if (c <= 0x10000) {
0150             periodcfg->clk_select = index;
0151             periodcfg->clk_ps = ps;
0152             periodcfg->mod_period = c - 1;
0153             return true;
0154         }
0155     }
0156     return false;
0157 }
0158
0159 static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
0160                      unsigned int period_ns,
0161                      struct fsl_pwm_periodcfg *periodcfg)
0162 {
0163     enum fsl_pwm_clk m0, m1;
0164     unsigned long fix_rate, ext_rate;
0165     bool ret;
0166
0167     ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
0168                        periodcfg);
0169     if (ret)
0170         return true;
0171
0172     fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
0173     ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
0174
0175     if (fix_rate > ext_rate) {
0176         m0 = FSL_PWM_CLK_FIX;
0177         m1 = FSL_PWM_CLK_EXT;
0178     } else {
0179         m0 = FSL_PWM_CLK_EXT;
0180         m1 = FSL_PWM_CLK_FIX;
0181     }
0182
0183     ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
0184     if (ret)
0185         return true;
0186
0187     return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
0188 }
0189
0190 static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
0191                        unsigned int duty_ns)
0192 {
0193     unsigned long long duty;
0194
0195     unsigned int period = fpc->period.mod_period + 1;
0196     unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
0197
0198     duty = (unsigned long long)duty_ns * period;
0199     do_div(duty, period_ns);
0200
0201     return (unsigned int)duty;
0202 }
0203
0204 static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
0205                        struct pwm_device *pwm)
0206 {
0207     u32 val;
0208
0209     regmap_read(fpc->regmap, FTM_OUTMASK, &val);
0210     if (~val & 0xFF)
0211         return true;
0212     else
0213         return false;
0214 }
0215
0216 static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
0217                      struct pwm_device *pwm)
0218 {
0219     u32 val;
0220
0221     regmap_read(fpc->regmap, FTM_OUTMASK, &val);
0222     if (~(val | BIT(pwm->hwpwm)) & 0xFF)
0223         return true;
0224     else
0225         return false;
0226 }
0227
0228 static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
0229                 struct pwm_device *pwm,
0230                 const struct pwm_state *newstate)
0231 {
0232     unsigned int duty;
0233     u32 reg_polarity;
0234
0235     struct fsl_pwm_periodcfg periodcfg;
0236     bool do_write_period = false;
0237
0238     if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
0239         dev_err(fpc->chip.dev, "failed to calculate new period\n");
0240         return -EINVAL;
0241     }
0242
0243     if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
0244         do_write_period = true;
0245     /*
0246      * The Freescale FTM controller supports only a single period for
0247      * all PWM channels, therefore verify if the newly computed period
0248      * is different than the current period being used. In such case
0249      * we allow to change the period only if no other pwm is running.
0250      */
0251     else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
0252         if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
0253             dev_err(fpc->chip.dev,
0254                 "Cannot change period for PWM %u, disable other PWMs first\n",
0255                 pwm->hwpwm);
0256             return -EBUSY;
0257         }
0258         if (fpc->period.clk_select != periodcfg.clk_select) {
0259             int ret;
0260             enum fsl_pwm_clk oldclk = fpc->period.clk_select;
0261             enum fsl_pwm_clk newclk = periodcfg.clk_select;
0262
0263             ret = clk_prepare_enable(fpc->clk[newclk]);
0264             if (ret)
0265                 return ret;
0266             clk_disable_unprepare(fpc->clk[oldclk]);
0267         }
0268         do_write_period = true;
0269     }
0270
0271     ftm_clear_write_protection(fpc);
0272
0273     if (do_write_period) {
0274         regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
0275                    FTM_SC_CLK(periodcfg.clk_select));
0276         regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
0277                    periodcfg.clk_ps);
0278         regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
0279
0280         fpc->period = periodcfg;
0281     }
0282
0283     duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
0284
0285     regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
0286              FTM_CSC_MSB | FTM_CSC_ELSB);
0287     regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
0288
0289     reg_polarity = 0;
0290     if (newstate->polarity == PWM_POLARITY_INVERSED)
0291         reg_polarity = BIT(pwm->hwpwm);
0292
0293     regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
0294
0295     ftm_set_write_protection(fpc);
0296
0297     return 0;
0298 }
0299
0300 static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0301              const struct pwm_state *newstate)
0302 {
0303     struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
0304     struct pwm_state *oldstate = &pwm->state;
0305     int ret = 0;
0306
0307     /*
0308      * oldstate to newstate : action
0309      *
0310      * disabled to disabled : ignore
0311      * enabled to disabled : disable
0312      * enabled to enabled : update settings
0313      * disabled to enabled : update settings + enable
0314      */
0315
0316     mutex_lock(&fpc->lock);
0317
0318     if (!newstate->enabled) {
0319         if (oldstate->enabled) {
0320             regmap_update_bits(fpc->regmap, FTM_OUTMASK,
0321                        BIT(pwm->hwpwm), BIT(pwm->hwpwm));
0322             clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
0323             clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
0324         }
0325
0326         goto end_mutex;
0327     }
0328
0329     ret = fsl_pwm_apply_config(fpc, pwm, newstate);
0330     if (ret)
0331         goto end_mutex;
0332
0333     /* check if need to enable */
0334     if (!oldstate->enabled) {
0335         ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
0336         if (ret)
0337             goto end_mutex;
0338
0339         ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
0340         if (ret) {
0341             clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
0342             goto end_mutex;
0343         }
0344
0345         regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
0346                    0);
0347     }
0348
0349 end_mutex:
0350     mutex_unlock(&fpc->lock);
0351     return ret;
0352 }
0353
0354 static const struct pwm_ops fsl_pwm_ops = {
0355     .request = fsl_pwm_request,
0356     .free = fsl_pwm_free,
0357     .apply = fsl_pwm_apply,
0358     .owner = THIS_MODULE,
0359 };
0360
0361 static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
0362 {
0363     int ret;
0364
0365     ret = clk_prepare_enable(fpc->ipg_clk);
0366     if (ret)
0367         return ret;
0368
0369     regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
0370     regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
0371     regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
0372
0373     clk_disable_unprepare(fpc->ipg_clk);
0374
0375     return 0;
0376 }
0377
0378 static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
0379 {
0380     switch (reg) {
0381     case FTM_FMS:
0382     case FTM_MODE:
0383     case FTM_CNT:
0384         return true;
0385     }
0386     return false;
0387 }
0388
0389 static const struct regmap_config fsl_pwm_regmap_config = {
0390     .reg_bits = 32,
0391     .reg_stride = 4,
0392     .val_bits = 32,
0393
0394     .max_register = FTM_PWMLOAD,
0395     .volatile_reg = fsl_pwm_volatile_reg,
0396     .cache_type = REGCACHE_FLAT,
0397 };
0398
0399 static int fsl_pwm_probe(struct platform_device *pdev)
0400 {
0401     struct fsl_pwm_chip *fpc;
0402     void __iomem *base;
0403     int ret;
0404
0405     fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
0406     if (!fpc)
0407         return -ENOMEM;
0408
0409     mutex_init(&fpc->lock);
0410
0411     fpc->soc = of_device_get_match_data(&pdev->dev);
0412     fpc->chip.dev = &pdev->dev;
0413
0414     base = devm_platform_ioremap_resource(pdev, 0);
0415     if (IS_ERR(base))
0416         return PTR_ERR(base);
0417
0418     fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
0419                         &fsl_pwm_regmap_config);
0420     if (IS_ERR(fpc->regmap)) {
0421         dev_err(&pdev->dev, "regmap init failed\n");
0422         return PTR_ERR(fpc->regmap);
0423     }
0424
0425     fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
0426     if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
0427         dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
0428         return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
0429     }
0430
0431     fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
0432     if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
0433         return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
0434
0435     fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
0436     if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
0437         return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
0438
0439     fpc->clk[FSL_PWM_CLK_CNTEN] =
0440                 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
0441     if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
0442         return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
0443
0444     /*
0445      * ipg_clk is the interface clock for the IP. If not provided, use the
0446      * ftm_sys clock as the default.
0447      */
0448     fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
0449     if (IS_ERR(fpc->ipg_clk))
0450         fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
0451
0452
0453     fpc->chip.ops = &fsl_pwm_ops;
0454     fpc->chip.npwm = 8;
0455
0456     ret = devm_pwmchip_add(&pdev->dev, &fpc->chip);
0457     if (ret < 0) {
0458         dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
0459         return ret;
0460     }
0461
0462     platform_set_drvdata(pdev, fpc);
0463
0464     return fsl_pwm_init(fpc);
0465 }
0466
0467 #ifdef CONFIG_PM_SLEEP
0468 static int fsl_pwm_suspend(struct device *dev)
0469 {
0470     struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
0471     int i;
0472
0473     regcache_cache_only(fpc->regmap, true);
0474     regcache_mark_dirty(fpc->regmap);
0475
0476     for (i = 0; i < fpc->chip.npwm; i++) {
0477         struct pwm_device *pwm = &fpc->chip.pwms[i];
0478
0479         if (!test_bit(PWMF_REQUESTED, &pwm->flags))
0480             continue;
0481
0482         clk_disable_unprepare(fpc->ipg_clk);
0483
0484         if (!pwm_is_enabled(pwm))
0485             continue;
0486
0487         clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
0488         clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
0489     }
0490
0491     return 0;
0492 }
0493
0494 static int fsl_pwm_resume(struct device *dev)
0495 {
0496     struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
0497     int i;
0498
0499     for (i = 0; i < fpc->chip.npwm; i++) {
0500         struct pwm_device *pwm = &fpc->chip.pwms[i];
0501
0502         if (!test_bit(PWMF_REQUESTED, &pwm->flags))
0503             continue;
0504
0505         clk_prepare_enable(fpc->ipg_clk);
0506
0507         if (!pwm_is_enabled(pwm))
0508             continue;
0509
0510         clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
0511         clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
0512     }
0513
0514     /* restore all registers from cache */
0515     regcache_cache_only(fpc->regmap, false);
0516     regcache_sync(fpc->regmap);
0517
0518     return 0;
0519 }
0520 #endif
0521
0522 static const struct dev_pm_ops fsl_pwm_pm_ops = {
0523     SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
0524 };
0525
0526 static const struct fsl_ftm_soc vf610_ftm_pwm = {
0527     .has_enable_bits = false,
0528 };
0529
0530 static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
0531     .has_enable_bits = true,
0532 };
0533
0534 static const struct of_device_id fsl_pwm_dt_ids[] = {
0535     { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
0536     { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
0537     { /* sentinel */ }
0538 };
0539 MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
0540
0541 static struct platform_driver fsl_pwm_driver = {
0542     .driver = {
0543         .name = "fsl-ftm-pwm",
0544         .of_match_table = fsl_pwm_dt_ids,
0545         .pm = &fsl_pwm_pm_ops,
0546     },
0547     .probe = fsl_pwm_probe,
0548 };
0549 module_platform_driver(fsl_pwm_driver);
0550
0551 MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
0552 MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
0553 MODULE_ALIAS("platform:fsl-ftm-pwm");
0554 MODULE_LICENSE("GPL");