drivers/pwm/pwm-crc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2015 Intel Corporation. All rights reserved.
0004  *
0005  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
0006  */
0007
0008 #include <linux/platform_device.h>
0009 #include <linux/regmap.h>
0010 #include <linux/mfd/intel_soc_pmic.h>
0011 #include <linux/pwm.h>
0012
0013 #define PWM0_CLK_DIV        0x4B
0014 #define  PWM_OUTPUT_ENABLE  BIT(7)
0015 #define  PWM_DIV_CLK_0      0x00 /* DIVIDECLK = BASECLK */
0016 #define  PWM_DIV_CLK_100    0x63 /* DIVIDECLK = BASECLK/100 */
0017 #define  PWM_DIV_CLK_128    0x7F /* DIVIDECLK = BASECLK/128 */
0018
0019 #define PWM0_DUTY_CYCLE     0x4E
0020 #define BACKLIGHT_EN        0x51
0021
0022 #define PWM_MAX_LEVEL       0xFF
0023
0024 #define PWM_BASE_CLK_MHZ    6   /* 6 MHz */
0025 #define PWM_MAX_PERIOD_NS   5461334 /* 183 Hz */
0026
0027 /**
0028  * struct crystalcove_pwm - Crystal Cove PWM controller
0029  * @chip: the abstract pwm_chip structure.
0030  * @regmap: the regmap from the parent device.
0031  */
0032 struct crystalcove_pwm {
0033     struct pwm_chip chip;
0034     struct regmap *regmap;
0035 };
0036
0037 static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc)
0038 {
0039     return container_of(pc, struct crystalcove_pwm, chip);
0040 }
0041
0042 static int crc_pwm_calc_clk_div(int period_ns)
0043 {
0044     int clk_div;
0045
0046     clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
0047     /* clk_div 1 - 128, maps to register values 0-127 */
0048     if (clk_div > 0)
0049         clk_div--;
0050
0051     return clk_div;
0052 }
0053
0054 static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0055              const struct pwm_state *state)
0056 {
0057     struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
0058     struct device *dev = crc_pwm->chip.dev;
0059     int err;
0060
0061     if (state->period > PWM_MAX_PERIOD_NS) {
0062         dev_err(dev, "un-supported period_ns\n");
0063         return -EINVAL;
0064     }
0065
0066     if (state->polarity != PWM_POLARITY_NORMAL)
0067         return -EINVAL;
0068
0069     if (pwm_is_enabled(pwm) && !state->enabled) {
0070         err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
0071         if (err) {
0072             dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
0073             return err;
0074         }
0075     }
0076
0077     if (pwm_get_duty_cycle(pwm) != state->duty_cycle ||
0078         pwm_get_period(pwm) != state->period) {
0079         u64 level = state->duty_cycle * PWM_MAX_LEVEL;
0080
0081         do_div(level, state->period);
0082
0083         err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
0084         if (err) {
0085             dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n", err);
0086             return err;
0087         }
0088     }
0089
0090     if (pwm_is_enabled(pwm) && state->enabled &&
0091         pwm_get_period(pwm) != state->period) {
0092         /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */
0093         err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0);
0094         if (err) {
0095             dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
0096             return err;
0097         }
0098     }
0099
0100     if (pwm_get_period(pwm) != state->period ||
0101         pwm_is_enabled(pwm) != state->enabled) {
0102         int clk_div = crc_pwm_calc_clk_div(state->period);
0103         int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0;
0104
0105         err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
0106                    clk_div | pwm_output_enable);
0107         if (err) {
0108             dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
0109             return err;
0110         }
0111     }
0112
0113     if (!pwm_is_enabled(pwm) && state->enabled) {
0114         err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
0115         if (err) {
0116             dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
0117             return err;
0118         }
0119     }
0120
0121     return 0;
0122 }
0123
0124 static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
0125                   struct pwm_state *state)
0126 {
0127     struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
0128     struct device *dev = crc_pwm->chip.dev;
0129     unsigned int clk_div, clk_div_reg, duty_cycle_reg;
0130     int error;
0131
0132     error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
0133     if (error) {
0134         dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
0135         return;
0136     }
0137
0138     error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
0139     if (error) {
0140         dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
0141         return;
0142     }
0143
0144     clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
0145
0146     state->period =
0147         DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);
0148     state->duty_cycle =
0149         DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
0150     state->polarity = PWM_POLARITY_NORMAL;
0151     state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);
0152 }
0153
0154 static const struct pwm_ops crc_pwm_ops = {
0155     .apply = crc_pwm_apply,
0156     .get_state = crc_pwm_get_state,
0157 };
0158
0159 static int crystalcove_pwm_probe(struct platform_device *pdev)
0160 {
0161     struct crystalcove_pwm *pwm;
0162     struct device *dev = pdev->dev.parent;
0163     struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
0164
0165     pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
0166     if (!pwm)
0167         return -ENOMEM;
0168
0169     pwm->chip.dev = &pdev->dev;
0170     pwm->chip.ops = &crc_pwm_ops;
0171     pwm->chip.npwm = 1;
0172
0173     /* get the PMIC regmap */
0174     pwm->regmap = pmic->regmap;
0175
0176     return devm_pwmchip_add(&pdev->dev, &pwm->chip);
0177 }
0178
0179 static struct platform_driver crystalcove_pwm_driver = {
0180     .probe = crystalcove_pwm_probe,
0181     .driver = {
0182         .name = "crystal_cove_pwm",
0183     },
0184 };
0185
0186 builtin_platform_driver(crystalcove_pwm_driver);