drivers/pwm/pwm-bcm-kona.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2014 Broadcom Corporation
0003
0004 #include <linux/clk.h>
0005 #include <linux/delay.h>
0006 #include <linux/err.h>
0007 #include <linux/io.h>
0008 #include <linux/ioport.h>
0009 #include <linux/math64.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/pwm.h>
0014 #include <linux/slab.h>
0015 #include <linux/types.h>
0016
0017 /*
0018  * The Kona PWM has some unusual characteristics.  Here are the main points.
0019  *
0020  * 1) There is no disable bit and the hardware docs advise programming a zero
0021  *    duty to achieve output equivalent to that of a normal disable operation.
0022  *
0023  * 2) Changes to prescale, duty, period, and polarity do not take effect until
0024  *    a subsequent rising edge of the trigger bit.
0025  *
0026  * 3) If the smooth bit and trigger bit are both low, the output is a constant
0027  *    high signal.  Otherwise, the earlier waveform continues to be output.
0028  *
0029  * 4) If the smooth bit is set on the rising edge of the trigger bit, output
0030  *    will transition to the new settings on a period boundary (which could be
0031  *    seconds away).  If the smooth bit is clear, new settings will be applied
0032  *    as soon as possible (the hardware always has a 400ns delay).
0033  *
0034  * 5) When the external clock that feeds the PWM is disabled, output is pegged
0035  *    high or low depending on its state at that exact instant.
0036  */
0037
0038 #define PWM_CONTROL_OFFSET          0x00000000
0039 #define PWM_CONTROL_SMOOTH_SHIFT(chan)      (24 + (chan))
0040 #define PWM_CONTROL_TYPE_SHIFT(chan)        (16 + (chan))
0041 #define PWM_CONTROL_POLARITY_SHIFT(chan)    (8 + (chan))
0042 #define PWM_CONTROL_TRIGGER_SHIFT(chan)     (chan)
0043
0044 #define PRESCALE_OFFSET             0x00000004
0045 #define PRESCALE_SHIFT(chan)            ((chan) << 2)
0046 #define PRESCALE_MASK(chan)         (0x7 << PRESCALE_SHIFT(chan))
0047 #define PRESCALE_MIN                0x00000000
0048 #define PRESCALE_MAX                0x00000007
0049
0050 #define PERIOD_COUNT_OFFSET(chan)       (0x00000008 + ((chan) << 3))
0051 #define PERIOD_COUNT_MIN            0x00000002
0052 #define PERIOD_COUNT_MAX            0x00ffffff
0053
0054 #define DUTY_CYCLE_HIGH_OFFSET(chan)        (0x0000000c + ((chan) << 3))
0055 #define DUTY_CYCLE_HIGH_MIN         0x00000000
0056 #define DUTY_CYCLE_HIGH_MAX         0x00ffffff
0057
0058 struct kona_pwmc {
0059     struct pwm_chip chip;
0060     void __iomem *base;
0061     struct clk *clk;
0062 };
0063
0064 static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)
0065 {
0066     return container_of(_chip, struct kona_pwmc, chip);
0067 }
0068
0069 /*
0070  * Clear trigger bit but set smooth bit to maintain old output.
0071  */
0072 static void kona_pwmc_prepare_for_settings(struct kona_pwmc *kp,
0073     unsigned int chan)
0074 {
0075     unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
0076
0077     value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
0078     value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
0079     writel(value, kp->base + PWM_CONTROL_OFFSET);
0080
0081     /*
0082      * There must be a min 400ns delay between clearing trigger and setting
0083      * it. Failing to do this may result in no PWM signal.
0084      */
0085     ndelay(400);
0086 }
0087
0088 static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
0089 {
0090     unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
0091
0092     /* Set trigger bit and clear smooth bit to apply new settings */
0093     value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
0094     value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
0095     writel(value, kp->base + PWM_CONTROL_OFFSET);
0096
0097     /* Trigger bit must be held high for at least 400 ns. */
0098     ndelay(400);
0099 }
0100
0101 static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
0102                 u64 duty_ns, u64 period_ns)
0103 {
0104     struct kona_pwmc *kp = to_kona_pwmc(chip);
0105     u64 div, rate;
0106     unsigned long prescale = PRESCALE_MIN, pc, dc;
0107     unsigned int value, chan = pwm->hwpwm;
0108
0109     /*
0110      * Find period count, duty count and prescale to suit duty_ns and
0111      * period_ns. This is done according to formulas described below:
0112      *
0113      * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
0114      * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
0115      *
0116      * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
0117      * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
0118      */
0119
0120     rate = clk_get_rate(kp->clk);
0121
0122     while (1) {
0123         div = 1000000000;
0124         div *= 1 + prescale;
0125         pc = mul_u64_u64_div_u64(rate, period_ns, div);
0126         dc = mul_u64_u64_div_u64(rate, duty_ns, div);
0127
0128         /* If duty_ns or period_ns are not achievable then return */
0129         if (pc < PERIOD_COUNT_MIN)
0130             return -EINVAL;
0131
0132         /* If pc and dc are in bounds, the calculation is done */
0133         if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
0134             break;
0135
0136         /* Otherwise, increase prescale and recalculate pc and dc */
0137         if (++prescale > PRESCALE_MAX)
0138             return -EINVAL;
0139     }
0140
0141     kona_pwmc_prepare_for_settings(kp, chan);
0142
0143     value = readl(kp->base + PRESCALE_OFFSET);
0144     value &= ~PRESCALE_MASK(chan);
0145     value |= prescale << PRESCALE_SHIFT(chan);
0146     writel(value, kp->base + PRESCALE_OFFSET);
0147
0148     writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
0149
0150     writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
0151
0152     kona_pwmc_apply_settings(kp, chan);
0153
0154     return 0;
0155 }
0156
0157 static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
0158                   enum pwm_polarity polarity)
0159 {
0160     struct kona_pwmc *kp = to_kona_pwmc(chip);
0161     unsigned int chan = pwm->hwpwm;
0162     unsigned int value;
0163     int ret;
0164
0165     ret = clk_prepare_enable(kp->clk);
0166     if (ret < 0) {
0167         dev_err(chip->dev, "failed to enable clock: %d\n", ret);
0168         return ret;
0169     }
0170
0171     kona_pwmc_prepare_for_settings(kp, chan);
0172
0173     value = readl(kp->base + PWM_CONTROL_OFFSET);
0174
0175     if (polarity == PWM_POLARITY_NORMAL)
0176         value |= 1 << PWM_CONTROL_POLARITY_SHIFT(chan);
0177     else
0178         value &= ~(1 << PWM_CONTROL_POLARITY_SHIFT(chan));
0179
0180     writel(value, kp->base + PWM_CONTROL_OFFSET);
0181
0182     kona_pwmc_apply_settings(kp, chan);
0183
0184     clk_disable_unprepare(kp->clk);
0185
0186     return 0;
0187 }
0188
0189 static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
0190 {
0191     struct kona_pwmc *kp = to_kona_pwmc(chip);
0192     int ret;
0193
0194     ret = clk_prepare_enable(kp->clk);
0195     if (ret < 0) {
0196         dev_err(chip->dev, "failed to enable clock: %d\n", ret);
0197         return ret;
0198     }
0199
0200     return 0;
0201 }
0202
0203 static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
0204 {
0205     struct kona_pwmc *kp = to_kona_pwmc(chip);
0206     unsigned int chan = pwm->hwpwm;
0207     unsigned int value;
0208
0209     kona_pwmc_prepare_for_settings(kp, chan);
0210
0211     /* Simulate a disable by configuring for zero duty */
0212     writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
0213     writel(0, kp->base + PERIOD_COUNT_OFFSET(chan));
0214
0215     /* Set prescale to 0 for this channel */
0216     value = readl(kp->base + PRESCALE_OFFSET);
0217     value &= ~PRESCALE_MASK(chan);
0218     writel(value, kp->base + PRESCALE_OFFSET);
0219
0220     kona_pwmc_apply_settings(kp, chan);
0221
0222     clk_disable_unprepare(kp->clk);
0223 }
0224
0225 static int kona_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0226                const struct pwm_state *state)
0227 {
0228     int err;
0229     struct kona_pwmc *kp = to_kona_pwmc(chip);
0230     bool enabled = pwm->state.enabled;
0231
0232     if (state->polarity != pwm->state.polarity) {
0233         if (enabled) {
0234             kona_pwmc_disable(chip, pwm);
0235             enabled = false;
0236         }
0237
0238         err = kona_pwmc_set_polarity(chip, pwm, state->polarity);
0239         if (err)
0240             return err;
0241
0242         pwm->state.polarity = state->polarity;
0243     }
0244
0245     if (!state->enabled) {
0246         if (enabled)
0247             kona_pwmc_disable(chip, pwm);
0248         return 0;
0249     } else if (!enabled) {
0250         /*
0251          * This is a bit special here, usually the PWM should only be
0252          * enabled when duty and period are setup. But before this
0253          * driver was converted to .apply it was done the other way
0254          * around and so this behaviour was kept even though this might
0255          * result in a glitch. This might be improvable by someone with
0256          * hardware and/or documentation.
0257          */
0258         err = kona_pwmc_enable(chip, pwm);
0259         if (err)
0260             return err;
0261     }
0262
0263     err = kona_pwmc_config(pwm->chip, pwm, state->duty_cycle, state->period);
0264     if (err && !pwm->state.enabled)
0265         clk_disable_unprepare(kp->clk);
0266
0267     return err;
0268 }
0269
0270 static const struct pwm_ops kona_pwm_ops = {
0271     .apply = kona_pwmc_apply,
0272     .owner = THIS_MODULE,
0273 };
0274
0275 static int kona_pwmc_probe(struct platform_device *pdev)
0276 {
0277     struct kona_pwmc *kp;
0278     unsigned int chan;
0279     unsigned int value = 0;
0280     int ret = 0;
0281
0282     kp = devm_kzalloc(&pdev->dev, sizeof(*kp), GFP_KERNEL);
0283     if (kp == NULL)
0284         return -ENOMEM;
0285
0286     kp->chip.dev = &pdev->dev;
0287     kp->chip.ops = &kona_pwm_ops;
0288     kp->chip.npwm = 6;
0289
0290     kp->base = devm_platform_ioremap_resource(pdev, 0);
0291     if (IS_ERR(kp->base))
0292         return PTR_ERR(kp->base);
0293
0294     kp->clk = devm_clk_get(&pdev->dev, NULL);
0295     if (IS_ERR(kp->clk)) {
0296         dev_err(&pdev->dev, "failed to get clock: %ld\n",
0297             PTR_ERR(kp->clk));
0298         return PTR_ERR(kp->clk);
0299     }
0300
0301     ret = clk_prepare_enable(kp->clk);
0302     if (ret < 0) {
0303         dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
0304         return ret;
0305     }
0306
0307     /* Set push/pull for all channels */
0308     for (chan = 0; chan < kp->chip.npwm; chan++)
0309         value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
0310
0311     writel(value, kp->base + PWM_CONTROL_OFFSET);
0312
0313     clk_disable_unprepare(kp->clk);
0314
0315     ret = devm_pwmchip_add(&pdev->dev, &kp->chip);
0316     if (ret < 0)
0317         dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
0318
0319     return ret;
0320 }
0321
0322 static const struct of_device_id bcm_kona_pwmc_dt[] = {
0323     { .compatible = "brcm,kona-pwm" },
0324     { },
0325 };
0326 MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt);
0327
0328 static struct platform_driver kona_pwmc_driver = {
0329     .driver = {
0330         .name = "bcm-kona-pwm",
0331         .of_match_table = bcm_kona_pwmc_dt,
0332     },
0333     .probe = kona_pwmc_probe,
0334 };
0335 module_platform_driver(kona_pwmc_driver);
0336
0337 MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
0338 MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
0339 MODULE_DESCRIPTION("Broadcom Kona PWM driver");
0340 MODULE_LICENSE("GPL v2");