drivers/pwm/pwm-atmel.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for Atmel Pulse Width Modulation Controller
0004  *
0005  * Copyright (C) 2013 Atmel Corporation
0006  *       Bo Shen <voice.shen@atmel.com>
0007  *
0008  * Links to reference manuals for the supported PWM chips can be found in
0009  * Documentation/arm/microchip.rst.
0010  *
0011  * Limitations:
0012  * - Periods start with the inactive level.
0013  * - Hardware has to be stopped in general to update settings.
0014  *
0015  * Software bugs/possible improvements:
0016  * - When atmel_pwm_apply() is called with state->enabled=false a change in
0017  *   state->polarity isn't honored.
0018  * - Instead of sleeping to wait for a completed period, the interrupt
0019  *   functionality could be used.
0020  */
0021
0022 #include <linux/clk.h>
0023 #include <linux/delay.h>
0024 #include <linux/err.h>
0025 #include <linux/io.h>
0026 #include <linux/module.h>
0027 #include <linux/of.h>
0028 #include <linux/of_device.h>
0029 #include <linux/platform_device.h>
0030 #include <linux/pwm.h>
0031 #include <linux/slab.h>
0032
0033 /* The following is global registers for PWM controller */
0034 #define PWM_ENA         0x04
0035 #define PWM_DIS         0x08
0036 #define PWM_SR          0x0C
0037 #define PWM_ISR         0x1C
0038 /* Bit field in SR */
0039 #define PWM_SR_ALL_CH_ON    0x0F
0040
0041 /* The following register is PWM channel related registers */
0042 #define PWM_CH_REG_OFFSET   0x200
0043 #define PWM_CH_REG_SIZE     0x20
0044
0045 #define PWM_CMR         0x0
0046 /* Bit field in CMR */
0047 #define PWM_CMR_CPOL        (1 << 9)
0048 #define PWM_CMR_UPD_CDTY    (1 << 10)
0049 #define PWM_CMR_CPRE_MSK    0xF
0050
0051 /* The following registers for PWM v1 */
0052 #define PWMV1_CDTY      0x04
0053 #define PWMV1_CPRD      0x08
0054 #define PWMV1_CUPD      0x10
0055
0056 /* The following registers for PWM v2 */
0057 #define PWMV2_CDTY      0x04
0058 #define PWMV2_CDTYUPD       0x08
0059 #define PWMV2_CPRD      0x0C
0060 #define PWMV2_CPRDUPD       0x10
0061
0062 #define PWM_MAX_PRES        10
0063
0064 struct atmel_pwm_registers {
0065     u8 period;
0066     u8 period_upd;
0067     u8 duty;
0068     u8 duty_upd;
0069 };
0070
0071 struct atmel_pwm_config {
0072     u32 period_bits;
0073 };
0074
0075 struct atmel_pwm_data {
0076     struct atmel_pwm_registers regs;
0077     struct atmel_pwm_config cfg;
0078 };
0079
0080 struct atmel_pwm_chip {
0081     struct pwm_chip chip;
0082     struct clk *clk;
0083     void __iomem *base;
0084     const struct atmel_pwm_data *data;
0085
0086     /*
0087      * The hardware supports a mechanism to update a channel's duty cycle at
0088      * the end of the currently running period. When such an update is
0089      * pending we delay disabling the PWM until the new configuration is
0090      * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
0091      * might not result in an inactive output.
0092      * This bitmask tracks for which channels an update is pending in
0093      * hardware.
0094      */
0095     u32 update_pending;
0096
0097     /* Protects .update_pending */
0098     spinlock_t lock;
0099 };
0100
0101 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
0102 {
0103     return container_of(chip, struct atmel_pwm_chip, chip);
0104 }
0105
0106 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
0107                   unsigned long offset)
0108 {
0109     return readl_relaxed(chip->base + offset);
0110 }
0111
0112 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
0113                     unsigned long offset, unsigned long val)
0114 {
0115     writel_relaxed(val, chip->base + offset);
0116 }
0117
0118 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
0119                      unsigned int ch, unsigned long offset)
0120 {
0121     unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
0122
0123     return atmel_pwm_readl(chip, base + offset);
0124 }
0125
0126 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
0127                        unsigned int ch, unsigned long offset,
0128                        unsigned long val)
0129 {
0130     unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
0131
0132     atmel_pwm_writel(chip, base + offset, val);
0133 }
0134
0135 static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
0136 {
0137     /*
0138      * Each channel that has its bit in ISR set started a new period since
0139      * ISR was cleared and so there is no more update pending.  Note that
0140      * reading ISR clears it, so this needs to handle all channels to not
0141      * loose information.
0142      */
0143     u32 isr = atmel_pwm_readl(chip, PWM_ISR);
0144
0145     chip->update_pending &= ~isr;
0146 }
0147
0148 static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
0149 {
0150     spin_lock(&chip->lock);
0151
0152     /*
0153      * Clear pending flags in hardware because otherwise there might still
0154      * be a stale flag in ISR.
0155      */
0156     atmel_pwm_update_pending(chip);
0157
0158     chip->update_pending |= (1 << ch);
0159
0160     spin_unlock(&chip->lock);
0161 }
0162
0163 static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
0164 {
0165     int ret = 0;
0166
0167     spin_lock(&chip->lock);
0168
0169     if (chip->update_pending & (1 << ch)) {
0170         atmel_pwm_update_pending(chip);
0171
0172         if (chip->update_pending & (1 << ch))
0173             ret = 1;
0174     }
0175
0176     spin_unlock(&chip->lock);
0177
0178     return ret;
0179 }
0180
0181 static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
0182 {
0183     unsigned long timeout = jiffies + 2 * HZ;
0184     int ret;
0185
0186     while ((ret = atmel_pwm_test_pending(chip, ch)) &&
0187            time_before(jiffies, timeout))
0188         usleep_range(10, 100);
0189
0190     return ret ? -ETIMEDOUT : 0;
0191 }
0192
0193 static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
0194                          unsigned long clkrate,
0195                          const struct pwm_state *state,
0196                          unsigned long *cprd, u32 *pres)
0197 {
0198     struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
0199     unsigned long long cycles = state->period;
0200     int shift;
0201
0202     /* Calculate the period cycles and prescale value */
0203     cycles *= clkrate;
0204     do_div(cycles, NSEC_PER_SEC);
0205
0206     /*
0207      * The register for the period length is cfg.period_bits bits wide.
0208      * So for each bit the number of clock cycles is wider divide the input
0209      * clock frequency by two using pres and shift cprd accordingly.
0210      */
0211     shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
0212
0213     if (shift > PWM_MAX_PRES) {
0214         dev_err(chip->dev, "pres exceeds the maximum value\n");
0215         return -EINVAL;
0216     } else if (shift > 0) {
0217         *pres = shift;
0218         cycles >>= *pres;
0219     } else {
0220         *pres = 0;
0221     }
0222
0223     *cprd = cycles;
0224
0225     return 0;
0226 }
0227
0228 static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
0229                      unsigned long clkrate, unsigned long cprd,
0230                      u32 pres, unsigned long *cdty)
0231 {
0232     unsigned long long cycles = state->duty_cycle;
0233
0234     cycles *= clkrate;
0235     do_div(cycles, NSEC_PER_SEC);
0236     cycles >>= pres;
0237     *cdty = cprd - cycles;
0238 }
0239
0240 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
0241                   unsigned long cdty)
0242 {
0243     struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
0244     u32 val;
0245
0246     if (atmel_pwm->data->regs.duty_upd ==
0247         atmel_pwm->data->regs.period_upd) {
0248         val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
0249         val &= ~PWM_CMR_UPD_CDTY;
0250         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
0251     }
0252
0253     atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
0254                 atmel_pwm->data->regs.duty_upd, cdty);
0255     atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
0256 }
0257
0258 static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
0259                     struct pwm_device *pwm,
0260                     unsigned long cprd, unsigned long cdty)
0261 {
0262     struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
0263
0264     atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
0265                 atmel_pwm->data->regs.duty, cdty);
0266     atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
0267                 atmel_pwm->data->regs.period, cprd);
0268 }
0269
0270 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
0271                   bool disable_clk)
0272 {
0273     struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
0274     unsigned long timeout;
0275
0276     atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
0277
0278     atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
0279
0280     /*
0281      * Wait for the PWM channel disable operation to be effective before
0282      * stopping the clock.
0283      */
0284     timeout = jiffies + 2 * HZ;
0285
0286     while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
0287            time_before(jiffies, timeout))
0288         usleep_range(10, 100);
0289
0290     if (disable_clk)
0291         clk_disable(atmel_pwm->clk);
0292 }
0293
0294 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0295                const struct pwm_state *state)
0296 {
0297     struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
0298     struct pwm_state cstate;
0299     unsigned long cprd, cdty;
0300     u32 pres, val;
0301     int ret;
0302
0303     pwm_get_state(pwm, &cstate);
0304
0305     if (state->enabled) {
0306         unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
0307
0308         if (cstate.enabled &&
0309             cstate.polarity == state->polarity &&
0310             cstate.period == state->period) {
0311             u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
0312
0313             cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
0314                           atmel_pwm->data->regs.period);
0315             pres = cmr & PWM_CMR_CPRE_MSK;
0316
0317             atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
0318             atmel_pwm_update_cdty(chip, pwm, cdty);
0319             return 0;
0320         }
0321
0322         ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
0323                             &pres);
0324         if (ret) {
0325             dev_err(chip->dev,
0326                 "failed to calculate cprd and prescaler\n");
0327             return ret;
0328         }
0329
0330         atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
0331
0332         if (cstate.enabled) {
0333             atmel_pwm_disable(chip, pwm, false);
0334         } else {
0335             ret = clk_enable(atmel_pwm->clk);
0336             if (ret) {
0337                 dev_err(chip->dev, "failed to enable clock\n");
0338                 return ret;
0339             }
0340         }
0341
0342         /* It is necessary to preserve CPOL, inside CMR */
0343         val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
0344         val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
0345         if (state->polarity == PWM_POLARITY_NORMAL)
0346             val &= ~PWM_CMR_CPOL;
0347         else
0348             val |= PWM_CMR_CPOL;
0349         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
0350         atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
0351         atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
0352     } else if (cstate.enabled) {
0353         atmel_pwm_disable(chip, pwm, true);
0354     }
0355
0356     return 0;
0357 }
0358
0359 static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
0360                 struct pwm_state *state)
0361 {
0362     struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
0363     u32 sr, cmr;
0364
0365     sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
0366     cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
0367
0368     if (sr & (1 << pwm->hwpwm)) {
0369         unsigned long rate = clk_get_rate(atmel_pwm->clk);
0370         u32 cdty, cprd, pres;
0371         u64 tmp;
0372
0373         pres = cmr & PWM_CMR_CPRE_MSK;
0374
0375         cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
0376                       atmel_pwm->data->regs.period);
0377         tmp = (u64)cprd * NSEC_PER_SEC;
0378         tmp <<= pres;
0379         state->period = DIV64_U64_ROUND_UP(tmp, rate);
0380
0381         /* Wait for an updated duty_cycle queued in hardware */
0382         atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
0383
0384         cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
0385                       atmel_pwm->data->regs.duty);
0386         tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
0387         tmp <<= pres;
0388         state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
0389
0390         state->enabled = true;
0391     } else {
0392         state->enabled = false;
0393     }
0394
0395     if (cmr & PWM_CMR_CPOL)
0396         state->polarity = PWM_POLARITY_INVERSED;
0397     else
0398         state->polarity = PWM_POLARITY_NORMAL;
0399 }
0400
0401 static const struct pwm_ops atmel_pwm_ops = {
0402     .apply = atmel_pwm_apply,
0403     .get_state = atmel_pwm_get_state,
0404     .owner = THIS_MODULE,
0405 };
0406
0407 static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
0408     .regs = {
0409         .period     = PWMV1_CPRD,
0410         .period_upd = PWMV1_CUPD,
0411         .duty       = PWMV1_CDTY,
0412         .duty_upd   = PWMV1_CUPD,
0413     },
0414     .cfg = {
0415         /* 16 bits to keep period and duty. */
0416         .period_bits    = 16,
0417     },
0418 };
0419
0420 static const struct atmel_pwm_data atmel_sama5_pwm_data = {
0421     .regs = {
0422         .period     = PWMV2_CPRD,
0423         .period_upd = PWMV2_CPRDUPD,
0424         .duty       = PWMV2_CDTY,
0425         .duty_upd   = PWMV2_CDTYUPD,
0426     },
0427     .cfg = {
0428         /* 16 bits to keep period and duty. */
0429         .period_bits    = 16,
0430     },
0431 };
0432
0433 static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
0434     .regs = {
0435         .period     = PWMV1_CPRD,
0436         .period_upd = PWMV1_CUPD,
0437         .duty       = PWMV1_CDTY,
0438         .duty_upd   = PWMV1_CUPD,
0439     },
0440     .cfg = {
0441         /* 32 bits to keep period and duty. */
0442         .period_bits    = 32,
0443     },
0444 };
0445
0446 static const struct of_device_id atmel_pwm_dt_ids[] = {
0447     {
0448         .compatible = "atmel,at91sam9rl-pwm",
0449         .data = &atmel_sam9rl_pwm_data,
0450     }, {
0451         .compatible = "atmel,sama5d3-pwm",
0452         .data = &atmel_sama5_pwm_data,
0453     }, {
0454         .compatible = "atmel,sama5d2-pwm",
0455         .data = &atmel_sama5_pwm_data,
0456     }, {
0457         .compatible = "microchip,sam9x60-pwm",
0458         .data = &mchp_sam9x60_pwm_data,
0459     }, {
0460         /* sentinel */
0461     },
0462 };
0463 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
0464
0465 static int atmel_pwm_probe(struct platform_device *pdev)
0466 {
0467     struct atmel_pwm_chip *atmel_pwm;
0468     int ret;
0469
0470     atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
0471     if (!atmel_pwm)
0472         return -ENOMEM;
0473
0474     atmel_pwm->data = of_device_get_match_data(&pdev->dev);
0475
0476     atmel_pwm->update_pending = 0;
0477     spin_lock_init(&atmel_pwm->lock);
0478
0479     atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
0480     if (IS_ERR(atmel_pwm->base))
0481         return PTR_ERR(atmel_pwm->base);
0482
0483     atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
0484     if (IS_ERR(atmel_pwm->clk))
0485         return PTR_ERR(atmel_pwm->clk);
0486
0487     ret = clk_prepare(atmel_pwm->clk);
0488     if (ret) {
0489         dev_err(&pdev->dev, "failed to prepare PWM clock\n");
0490         return ret;
0491     }
0492
0493     atmel_pwm->chip.dev = &pdev->dev;
0494     atmel_pwm->chip.ops = &atmel_pwm_ops;
0495     atmel_pwm->chip.npwm = 4;
0496
0497     ret = pwmchip_add(&atmel_pwm->chip);
0498     if (ret < 0) {
0499         dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
0500         goto unprepare_clk;
0501     }
0502
0503     platform_set_drvdata(pdev, atmel_pwm);
0504
0505     return ret;
0506
0507 unprepare_clk:
0508     clk_unprepare(atmel_pwm->clk);
0509     return ret;
0510 }
0511
0512 static int atmel_pwm_remove(struct platform_device *pdev)
0513 {
0514     struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
0515
0516     pwmchip_remove(&atmel_pwm->chip);
0517
0518     clk_unprepare(atmel_pwm->clk);
0519
0520     return 0;
0521 }
0522
0523 static struct platform_driver atmel_pwm_driver = {
0524     .driver = {
0525         .name = "atmel-pwm",
0526         .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
0527     },
0528     .probe = atmel_pwm_probe,
0529     .remove = atmel_pwm_remove,
0530 };
0531 module_platform_driver(atmel_pwm_driver);
0532
0533 MODULE_ALIAS("platform:atmel-pwm");
0534 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
0535 MODULE_DESCRIPTION("Atmel PWM driver");
0536 MODULE_LICENSE("GPL v2");