drivers/ptp/ptp_idt82p33.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * PTP hardware clock driver for the IDT 82P33XXX family of clocks.
0004  *
0005  * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
0006  */
0007 #ifndef PTP_IDT82P33_H
0008 #define PTP_IDT82P33_H
0009
0010 #include <linux/ktime.h>
0011 #include <linux/mfd/idt82p33_reg.h>
0012 #include <linux/regmap.h>
0013
0014 #define FW_FILENAME "idt82p33xxx.bin"
0015 #define MAX_PHC_PLL (2)
0016 #define TOD_BYTE_COUNT  (10)
0017 #define DCO_MAX_PPB     (92000)
0018 #define MAX_MEASURMENT_COUNT    (5)
0019 #define SNAP_THRESHOLD_NS   (10000)
0020 #define IMMEDIATE_SNAP_THRESHOLD_NS (50000)
0021 #define DDCO_THRESHOLD_NS   (5)
0022 #define IDT82P33_MAX_WRITE_COUNT    (512)
0023 #define PEROUT_ENABLE_OUTPUT_MASK   (0xdeadbeef)
0024
0025 #define PLLMASK_ADDR_HI 0xFF
0026 #define PLLMASK_ADDR_LO 0xA5
0027
0028 #define PLL0_OUTMASK_ADDR_HI    0xFF
0029 #define PLL0_OUTMASK_ADDR_LO    0xB0
0030
0031 #define PLL1_OUTMASK_ADDR_HI    0xFF
0032 #define PLL1_OUTMASK_ADDR_LO    0xB2
0033
0034 #define PLL2_OUTMASK_ADDR_HI    0xFF
0035 #define PLL2_OUTMASK_ADDR_LO    0xB4
0036
0037 #define PLL3_OUTMASK_ADDR_HI    0xFF
0038 #define PLL3_OUTMASK_ADDR_LO    0xB6
0039
0040 #define DEFAULT_PLL_MASK    (0x01)
0041 #define DEFAULT_OUTPUT_MASK_PLL0    (0xc0)
0042 #define DEFAULT_OUTPUT_MASK_PLL1    DEFAULT_OUTPUT_MASK_PLL0
0043
0044 /**
0045  * @brief Maximum absolute value for write phase offset in femtoseconds
0046  */
0047 #define WRITE_PHASE_OFFSET_LIMIT (20000052084ll)
0048
0049 /** @brief Phase offset resolution
0050  *
0051  *  DPLL phase offset = 10^15 fs / ( System Clock  * 2^13)
0052  *                    = 10^15 fs / ( 1638400000 * 2^23)
0053  *                    = 74.5058059692382 fs
0054  */
0055 #define IDT_T0DPLL_PHASE_RESOL 74506
0056
0057 /* PTP Hardware Clock interface */
0058 struct idt82p33_channel {
0059     struct ptp_clock_info   caps;
0060     struct ptp_clock    *ptp_clock;
0061     struct idt82p33     *idt82p33;
0062     enum pll_mode       pll_mode;
0063     s32         current_freq_ppb;
0064     u8          output_mask;
0065     u16         dpll_tod_cnfg;
0066     u16         dpll_tod_trigger;
0067     u16         dpll_tod_sts;
0068     u16         dpll_mode_cnfg;
0069     u16         dpll_freq_cnfg;
0070     u16         dpll_phase_cnfg;
0071     u16         dpll_sync_cnfg;
0072     u16         dpll_input_mode_cnfg;
0073 };
0074
0075 struct idt82p33 {
0076     struct idt82p33_channel channel[MAX_PHC_PLL];
0077     struct device       *dev;
0078     u8          pll_mask;
0079     /* Mutex to protect operations from being interrupted */
0080     struct mutex        *lock;
0081     struct regmap       *regmap;
0082     struct device       *mfd;
0083     /* Overhead calculation for adjtime */
0084     ktime_t         start_time;
0085     int         calculate_overhead_flag;
0086     s64         tod_write_overhead_ns;
0087 };
0088
0089 /* firmware interface */
0090 struct idt82p33_fwrc {
0091     u8 hiaddr;
0092     u8 loaddr;
0093     u8 value;
0094     u8 reserved;
0095 } __packed;
0096
0097 #endif /* PTP_IDT82P33_H */