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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (C) 2018 Integrated Device Technology, Inc
0004 //
0005 
0006 #define pr_fmt(fmt) "IDT_82p33xxx: " fmt
0007 
0008 #include <linux/firmware.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/module.h>
0011 #include <linux/ptp_clock_kernel.h>
0012 #include <linux/delay.h>
0013 #include <linux/jiffies.h>
0014 #include <linux/kernel.h>
0015 #include <linux/timekeeping.h>
0016 #include <linux/bitops.h>
0017 #include <linux/of.h>
0018 #include <linux/mfd/rsmu.h>
0019 #include <linux/mfd/idt82p33_reg.h>
0020 
0021 #include "ptp_private.h"
0022 #include "ptp_idt82p33.h"
0023 
0024 MODULE_DESCRIPTION("Driver for IDT 82p33xxx clock devices");
0025 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
0026 MODULE_VERSION("1.0");
0027 MODULE_LICENSE("GPL");
0028 MODULE_FIRMWARE(FW_FILENAME);
0029 
0030 /* Module Parameters */
0031 static u32 phase_snap_threshold = SNAP_THRESHOLD_NS;
0032 module_param(phase_snap_threshold, uint, 0);
0033 MODULE_PARM_DESC(phase_snap_threshold,
0034 "threshold (10000ns by default) below which adjtime would use double dco");
0035 
0036 static char *firmware;
0037 module_param(firmware, charp, 0);
0038 
0039 static inline int idt82p33_read(struct idt82p33 *idt82p33, u16 regaddr,
0040                 u8 *buf, u16 count)
0041 {
0042     return regmap_bulk_read(idt82p33->regmap, regaddr, buf, count);
0043 }
0044 
0045 static inline int idt82p33_write(struct idt82p33 *idt82p33, u16 regaddr,
0046                  u8 *buf, u16 count)
0047 {
0048     return regmap_bulk_write(idt82p33->regmap, regaddr, buf, count);
0049 }
0050 
0051 static void idt82p33_byte_array_to_timespec(struct timespec64 *ts,
0052                         u8 buf[TOD_BYTE_COUNT])
0053 {
0054     time64_t sec;
0055     s32 nsec;
0056     u8 i;
0057 
0058     nsec = buf[3];
0059     for (i = 0; i < 3; i++) {
0060         nsec <<= 8;
0061         nsec |= buf[2 - i];
0062     }
0063 
0064     sec = buf[9];
0065     for (i = 0; i < 5; i++) {
0066         sec <<= 8;
0067         sec |= buf[8 - i];
0068     }
0069 
0070     ts->tv_sec = sec;
0071     ts->tv_nsec = nsec;
0072 }
0073 
0074 static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts,
0075                         u8 buf[TOD_BYTE_COUNT])
0076 {
0077     time64_t sec;
0078     s32 nsec;
0079     u8 i;
0080 
0081     nsec = ts->tv_nsec;
0082     sec = ts->tv_sec;
0083 
0084     for (i = 0; i < 4; i++) {
0085         buf[i] = nsec & 0xff;
0086         nsec >>= 8;
0087     }
0088 
0089     for (i = 4; i < TOD_BYTE_COUNT; i++) {
0090         buf[i] = sec & 0xff;
0091         sec >>= 8;
0092     }
0093 }
0094 
0095 static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
0096                   enum pll_mode mode)
0097 {
0098     struct idt82p33 *idt82p33 = channel->idt82p33;
0099     u8 dpll_mode;
0100     int err;
0101 
0102     if (channel->pll_mode == mode)
0103         return 0;
0104 
0105     err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
0106                 &dpll_mode, sizeof(dpll_mode));
0107     if (err)
0108         return err;
0109 
0110     dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
0111 
0112     dpll_mode |= (mode << PLL_MODE_SHIFT);
0113 
0114     err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
0115                  &dpll_mode, sizeof(dpll_mode));
0116     if (err)
0117         return err;
0118 
0119     channel->pll_mode = mode;
0120 
0121     return 0;
0122 }
0123 
0124 static int _idt82p33_gettime(struct idt82p33_channel *channel,
0125                  struct timespec64 *ts)
0126 {
0127     struct idt82p33 *idt82p33 = channel->idt82p33;
0128     u8 buf[TOD_BYTE_COUNT];
0129     u8 trigger;
0130     int err;
0131 
0132     trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
0133                   HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
0134 
0135 
0136     err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
0137                  &trigger, sizeof(trigger));
0138 
0139     if (err)
0140         return err;
0141 
0142     if (idt82p33->calculate_overhead_flag)
0143         idt82p33->start_time = ktime_get_raw();
0144 
0145     err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
0146 
0147     if (err)
0148         return err;
0149 
0150     idt82p33_byte_array_to_timespec(ts, buf);
0151 
0152     return 0;
0153 }
0154 
0155 /*
0156  *   TOD Trigger:
0157  *   Bits[7:4] Write 0x9, MSB write
0158  *   Bits[3:0] Read 0x9, LSB read
0159  */
0160 
0161 static int _idt82p33_settime(struct idt82p33_channel *channel,
0162                  struct timespec64 const *ts)
0163 {
0164     struct idt82p33 *idt82p33 = channel->idt82p33;
0165     struct timespec64 local_ts = *ts;
0166     char buf[TOD_BYTE_COUNT];
0167     s64 dynamic_overhead_ns;
0168     unsigned char trigger;
0169     int err;
0170     u8 i;
0171 
0172     trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
0173                   HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
0174 
0175     err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
0176             &trigger, sizeof(trigger));
0177 
0178     if (err)
0179         return err;
0180 
0181     if (idt82p33->calculate_overhead_flag) {
0182         dynamic_overhead_ns = ktime_to_ns(ktime_get_raw())
0183                     - ktime_to_ns(idt82p33->start_time);
0184 
0185         timespec64_add_ns(&local_ts, dynamic_overhead_ns);
0186 
0187         idt82p33->calculate_overhead_flag = 0;
0188     }
0189 
0190     idt82p33_timespec_to_byte_array(&local_ts, buf);
0191 
0192     /*
0193      * Store the new time value.
0194      */
0195     for (i = 0; i < TOD_BYTE_COUNT; i++) {
0196         err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
0197                      &buf[i], sizeof(buf[i]));
0198         if (err)
0199             return err;
0200     }
0201 
0202     return err;
0203 }
0204 
0205 static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns)
0206 {
0207     struct idt82p33 *idt82p33 = channel->idt82p33;
0208     struct timespec64 ts;
0209     s64 now_ns;
0210     int err;
0211 
0212     idt82p33->calculate_overhead_flag = 1;
0213 
0214     err = _idt82p33_gettime(channel, &ts);
0215 
0216     if (err)
0217         return err;
0218 
0219     now_ns = timespec64_to_ns(&ts);
0220     now_ns += delta_ns + idt82p33->tod_write_overhead_ns;
0221 
0222     ts = ns_to_timespec64(now_ns);
0223 
0224     err = _idt82p33_settime(channel, &ts);
0225 
0226     return err;
0227 }
0228 
0229 static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
0230 {
0231     struct idt82p33 *idt82p33 = channel->idt82p33;
0232     unsigned char buf[5] = {0};
0233     int err, i;
0234     s64 fcw;
0235 
0236     if (scaled_ppm == channel->current_freq_ppb)
0237         return 0;
0238 
0239     /*
0240      * Frequency Control Word unit is: 1.68 * 10^-10 ppm
0241      *
0242      * adjfreq:
0243      *       ppb * 10^9
0244      * FCW = ----------
0245      *          168
0246      *
0247      * adjfine:
0248      *       scaled_ppm * 5^12
0249      * FCW = -------------
0250      *         168 * 2^4
0251      */
0252 
0253     fcw = scaled_ppm * 244140625ULL;
0254     fcw = div_s64(fcw, 2688);
0255 
0256     for (i = 0; i < 5; i++) {
0257         buf[i] = fcw & 0xff;
0258         fcw >>= 8;
0259     }
0260 
0261     err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
0262 
0263     if (err)
0264         return err;
0265 
0266     err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
0267                  buf, sizeof(buf));
0268 
0269     if (err == 0)
0270         channel->current_freq_ppb = scaled_ppm;
0271 
0272     return err;
0273 }
0274 
0275 static int idt82p33_measure_one_byte_write_overhead(
0276         struct idt82p33_channel *channel, s64 *overhead_ns)
0277 {
0278     struct idt82p33 *idt82p33 = channel->idt82p33;
0279     ktime_t start, stop;
0280     s64 total_ns;
0281     u8 trigger;
0282     int err;
0283     u8 i;
0284 
0285     total_ns = 0;
0286     *overhead_ns = 0;
0287     trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
0288                   HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
0289 
0290     for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
0291 
0292         start = ktime_get_raw();
0293 
0294         err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
0295                      &trigger, sizeof(trigger));
0296 
0297         stop = ktime_get_raw();
0298 
0299         if (err)
0300             return err;
0301 
0302         total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
0303     }
0304 
0305     *overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT);
0306 
0307     return err;
0308 }
0309 
0310 static int idt82p33_measure_tod_write_9_byte_overhead(
0311             struct idt82p33_channel *channel)
0312 {
0313     struct idt82p33 *idt82p33 = channel->idt82p33;
0314     u8 buf[TOD_BYTE_COUNT];
0315     ktime_t start, stop;
0316     s64 total_ns;
0317     int err = 0;
0318     u8 i, j;
0319 
0320     total_ns = 0;
0321     idt82p33->tod_write_overhead_ns = 0;
0322 
0323     for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
0324 
0325         start = ktime_get_raw();
0326 
0327         /* Need one less byte for applicable overhead */
0328         for (j = 0; j < (TOD_BYTE_COUNT - 1); j++) {
0329             err = idt82p33_write(idt82p33,
0330                          channel->dpll_tod_cnfg + i,
0331                          &buf[i], sizeof(buf[i]));
0332             if (err)
0333                 return err;
0334         }
0335 
0336         stop = ktime_get_raw();
0337 
0338         total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
0339     }
0340 
0341     idt82p33->tod_write_overhead_ns = div_s64(total_ns,
0342                           MAX_MEASURMENT_COUNT);
0343 
0344     return err;
0345 }
0346 
0347 static int idt82p33_measure_settime_gettime_gap_overhead(
0348         struct idt82p33_channel *channel, s64 *overhead_ns)
0349 {
0350     struct timespec64 ts1 = {0, 0};
0351     struct timespec64 ts2;
0352     int err;
0353 
0354     *overhead_ns = 0;
0355 
0356     err = _idt82p33_settime(channel, &ts1);
0357 
0358     if (err)
0359         return err;
0360 
0361     err = _idt82p33_gettime(channel, &ts2);
0362 
0363     if (!err)
0364         *overhead_ns = timespec64_to_ns(&ts2) - timespec64_to_ns(&ts1);
0365 
0366     return err;
0367 }
0368 
0369 static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
0370 {
0371     s64 trailing_overhead_ns, one_byte_write_ns, gap_ns;
0372     struct idt82p33 *idt82p33 = channel->idt82p33;
0373     int err;
0374 
0375     idt82p33->tod_write_overhead_ns = 0;
0376 
0377     err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);
0378 
0379     if (err) {
0380         dev_err(idt82p33->dev,
0381             "Failed in %s with err %d!\n", __func__, err);
0382         return err;
0383     }
0384 
0385     err = idt82p33_measure_one_byte_write_overhead(channel,
0386                                &one_byte_write_ns);
0387 
0388     if (err)
0389         return err;
0390 
0391     err = idt82p33_measure_tod_write_9_byte_overhead(channel);
0392 
0393     if (err)
0394         return err;
0395 
0396     trailing_overhead_ns = gap_ns - (2 * one_byte_write_ns);
0397 
0398     idt82p33->tod_write_overhead_ns -= trailing_overhead_ns;
0399 
0400     return err;
0401 }
0402 
0403 static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33,
0404                     u8 page,
0405                     u8 offset,
0406                     u8 val)
0407 {
0408     int err = 0;
0409 
0410     if (page == PLLMASK_ADDR_HI && offset == PLLMASK_ADDR_LO) {
0411         if ((val & 0xfc) || !(val & 0x3)) {
0412             dev_err(idt82p33->dev,
0413                 "Invalid PLL mask 0x%x\n", val);
0414             err = -EINVAL;
0415         } else {
0416             idt82p33->pll_mask = val;
0417         }
0418     } else if (page == PLL0_OUTMASK_ADDR_HI &&
0419         offset == PLL0_OUTMASK_ADDR_LO) {
0420         idt82p33->channel[0].output_mask = val;
0421     } else if (page == PLL1_OUTMASK_ADDR_HI &&
0422         offset == PLL1_OUTMASK_ADDR_LO) {
0423         idt82p33->channel[1].output_mask = val;
0424     }
0425 
0426     return err;
0427 }
0428 
0429 static void idt82p33_display_masks(struct idt82p33 *idt82p33)
0430 {
0431     u8 mask, i;
0432 
0433     dev_info(idt82p33->dev,
0434          "pllmask = 0x%02x\n", idt82p33->pll_mask);
0435 
0436     for (i = 0; i < MAX_PHC_PLL; i++) {
0437         mask = 1 << i;
0438 
0439         if (mask & idt82p33->pll_mask)
0440             dev_info(idt82p33->dev,
0441                  "PLL%d output_mask = 0x%04x\n",
0442                  i, idt82p33->channel[i].output_mask);
0443     }
0444 }
0445 
0446 static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
0447 {
0448     struct idt82p33 *idt82p33 = channel->idt82p33;
0449     u8 sync_cnfg;
0450     int err;
0451 
0452     err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
0453                 &sync_cnfg, sizeof(sync_cnfg));
0454     if (err)
0455         return err;
0456 
0457     sync_cnfg &= ~SYNC_TOD;
0458     if (enable)
0459         sync_cnfg |= SYNC_TOD;
0460 
0461     return idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
0462                   &sync_cnfg, sizeof(sync_cnfg));
0463 }
0464 
0465 static int idt82p33_output_enable(struct idt82p33_channel *channel,
0466                   bool enable, unsigned int outn)
0467 {
0468     struct idt82p33 *idt82p33 = channel->idt82p33;
0469     int err;
0470     u8 val;
0471 
0472     err = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
0473     if (err)
0474         return err;
0475     if (enable)
0476         val &= ~SQUELCH_ENABLE;
0477     else
0478         val |= SQUELCH_ENABLE;
0479 
0480     return idt82p33_write(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
0481 }
0482 
0483 static int idt82p33_output_mask_enable(struct idt82p33_channel *channel,
0484                        bool enable)
0485 {
0486     u16 mask;
0487     int err;
0488     u8 outn;
0489 
0490     mask = channel->output_mask;
0491     outn = 0;
0492 
0493     while (mask) {
0494         if (mask & 0x1) {
0495             err = idt82p33_output_enable(channel, enable, outn);
0496             if (err)
0497                 return err;
0498         }
0499 
0500         mask >>= 0x1;
0501         outn++;
0502     }
0503 
0504     return 0;
0505 }
0506 
0507 static int idt82p33_perout_enable(struct idt82p33_channel *channel,
0508                   bool enable,
0509                   struct ptp_perout_request *perout)
0510 {
0511     unsigned int flags = perout->flags;
0512 
0513     /* Enable/disable output based on output_mask */
0514     if (flags == PEROUT_ENABLE_OUTPUT_MASK)
0515         return idt82p33_output_mask_enable(channel, enable);
0516 
0517     /* Enable/disable individual output instead */
0518     return idt82p33_output_enable(channel, enable, perout->index);
0519 }
0520 
0521 static int idt82p33_enable_tod(struct idt82p33_channel *channel)
0522 {
0523     struct idt82p33 *idt82p33 = channel->idt82p33;
0524     struct timespec64 ts = {0, 0};
0525     int err;
0526 
0527     err = idt82p33_measure_tod_write_overhead(channel);
0528 
0529     if (err) {
0530         dev_err(idt82p33->dev,
0531             "Failed in %s with err %d!\n", __func__, err);
0532         return err;
0533     }
0534 
0535     err = _idt82p33_settime(channel, &ts);
0536 
0537     if (err)
0538         return err;
0539 
0540     return idt82p33_sync_tod(channel, true);
0541 }
0542 
0543 static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
0544 {
0545     struct idt82p33_channel *channel;
0546     u8 i;
0547 
0548     for (i = 0; i < MAX_PHC_PLL; i++) {
0549 
0550         channel = &idt82p33->channel[i];
0551 
0552         if (channel->ptp_clock)
0553             ptp_clock_unregister(channel->ptp_clock);
0554     }
0555 }
0556 
0557 static int idt82p33_enable(struct ptp_clock_info *ptp,
0558                struct ptp_clock_request *rq, int on)
0559 {
0560     struct idt82p33_channel *channel =
0561             container_of(ptp, struct idt82p33_channel, caps);
0562     struct idt82p33 *idt82p33 = channel->idt82p33;
0563     int err = -EOPNOTSUPP;
0564 
0565     mutex_lock(idt82p33->lock);
0566 
0567     if (rq->type == PTP_CLK_REQ_PEROUT) {
0568         if (!on)
0569             err = idt82p33_perout_enable(channel, false,
0570                              &rq->perout);
0571         /* Only accept a 1-PPS aligned to the second. */
0572         else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
0573              rq->perout.period.nsec)
0574             err = -ERANGE;
0575         else
0576             err = idt82p33_perout_enable(channel, true,
0577                              &rq->perout);
0578     }
0579 
0580     mutex_unlock(idt82p33->lock);
0581 
0582     if (err)
0583         dev_err(idt82p33->dev,
0584             "Failed in %s with err %d!\n", __func__, err);
0585     return err;
0586 }
0587 
0588 static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns)
0589 {
0590     struct idt82p33_channel *channel =
0591         container_of(ptp, struct idt82p33_channel, caps);
0592     struct idt82p33 *idt82p33 = channel->idt82p33;
0593     s64 offset_regval, offset_fs;
0594     u8 val[4] = {0};
0595     int err;
0596 
0597     offset_fs = (s64)(-offset_ns) * 1000000;
0598 
0599     if (offset_fs > WRITE_PHASE_OFFSET_LIMIT)
0600         offset_fs = WRITE_PHASE_OFFSET_LIMIT;
0601     else if (offset_fs < -WRITE_PHASE_OFFSET_LIMIT)
0602         offset_fs = -WRITE_PHASE_OFFSET_LIMIT;
0603 
0604     /* Convert from phaseoffset_fs to register value */
0605     offset_regval = div_s64(offset_fs * 1000, IDT_T0DPLL_PHASE_RESOL);
0606 
0607     val[0] = offset_regval & 0xFF;
0608     val[1] = (offset_regval >> 8) & 0xFF;
0609     val[2] = (offset_regval >> 16) & 0xFF;
0610     val[3] = (offset_regval >> 24) & 0x1F;
0611     val[3] |= PH_OFFSET_EN;
0612 
0613     mutex_lock(idt82p33->lock);
0614 
0615     err = idt82p33_dpll_set_mode(channel, PLL_MODE_WPH);
0616     if (err) {
0617         dev_err(idt82p33->dev,
0618             "Failed in %s with err %d!\n", __func__, err);
0619         goto out;
0620     }
0621 
0622     err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val,
0623                  sizeof(val));
0624 
0625 out:
0626     mutex_unlock(idt82p33->lock);
0627     return err;
0628 }
0629 
0630 static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
0631 {
0632     struct idt82p33_channel *channel =
0633             container_of(ptp, struct idt82p33_channel, caps);
0634     struct idt82p33 *idt82p33 = channel->idt82p33;
0635     int err;
0636 
0637     mutex_lock(idt82p33->lock);
0638     err = _idt82p33_adjfine(channel, scaled_ppm);
0639     mutex_unlock(idt82p33->lock);
0640     if (err)
0641         dev_err(idt82p33->dev,
0642             "Failed in %s with err %d!\n", __func__, err);
0643 
0644     return err;
0645 }
0646 
0647 static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
0648 {
0649     struct idt82p33_channel *channel =
0650             container_of(ptp, struct idt82p33_channel, caps);
0651     struct idt82p33 *idt82p33 = channel->idt82p33;
0652     int err;
0653 
0654     mutex_lock(idt82p33->lock);
0655 
0656     if (abs(delta_ns) < phase_snap_threshold) {
0657         mutex_unlock(idt82p33->lock);
0658         return 0;
0659     }
0660 
0661     err = _idt82p33_adjtime(channel, delta_ns);
0662 
0663     mutex_unlock(idt82p33->lock);
0664 
0665     if (err)
0666         dev_err(idt82p33->dev,
0667             "Failed in %s with err %d!\n", __func__, err);
0668     return err;
0669 }
0670 
0671 static int idt82p33_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
0672 {
0673     struct idt82p33_channel *channel =
0674             container_of(ptp, struct idt82p33_channel, caps);
0675     struct idt82p33 *idt82p33 = channel->idt82p33;
0676     int err;
0677 
0678     mutex_lock(idt82p33->lock);
0679     err = _idt82p33_gettime(channel, ts);
0680     mutex_unlock(idt82p33->lock);
0681 
0682     if (err)
0683         dev_err(idt82p33->dev,
0684             "Failed in %s with err %d!\n", __func__, err);
0685     return err;
0686 }
0687 
0688 static int idt82p33_settime(struct ptp_clock_info *ptp,
0689                 const struct timespec64 *ts)
0690 {
0691     struct idt82p33_channel *channel =
0692             container_of(ptp, struct idt82p33_channel, caps);
0693     struct idt82p33 *idt82p33 = channel->idt82p33;
0694     int err;
0695 
0696     mutex_lock(idt82p33->lock);
0697     err = _idt82p33_settime(channel, ts);
0698     mutex_unlock(idt82p33->lock);
0699 
0700     if (err)
0701         dev_err(idt82p33->dev,
0702             "Failed in %s with err %d!\n", __func__, err);
0703     return err;
0704 }
0705 
0706 static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
0707 {
0708     switch (index) {
0709     case 0:
0710         channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
0711         channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
0712         channel->dpll_tod_sts = DPLL1_TOD_STS;
0713         channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
0714         channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
0715         channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
0716         channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
0717         channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
0718         break;
0719     case 1:
0720         channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
0721         channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
0722         channel->dpll_tod_sts = DPLL2_TOD_STS;
0723         channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
0724         channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
0725         channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
0726         channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
0727         channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
0728         break;
0729     default:
0730         return -EINVAL;
0731     }
0732 
0733     channel->current_freq_ppb = 0;
0734 
0735     return 0;
0736 }
0737 
0738 static void idt82p33_caps_init(struct ptp_clock_info *caps)
0739 {
0740     caps->owner = THIS_MODULE;
0741     caps->max_adj = DCO_MAX_PPB;
0742     caps->n_per_out = 11;
0743     caps->adjphase = idt82p33_adjwritephase;
0744     caps->adjfine = idt82p33_adjfine;
0745     caps->adjtime = idt82p33_adjtime;
0746     caps->gettime64 = idt82p33_gettime;
0747     caps->settime64 = idt82p33_settime;
0748     caps->enable = idt82p33_enable;
0749 }
0750 
0751 static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
0752 {
0753     struct idt82p33_channel *channel;
0754     int err;
0755 
0756     if (!(index < MAX_PHC_PLL))
0757         return -EINVAL;
0758 
0759     channel = &idt82p33->channel[index];
0760 
0761     err = idt82p33_channel_init(channel, index);
0762     if (err) {
0763         dev_err(idt82p33->dev,
0764             "Channel_init failed in %s with err %d!\n",
0765             __func__, err);
0766         return err;
0767     }
0768 
0769     channel->idt82p33 = idt82p33;
0770 
0771     idt82p33_caps_init(&channel->caps);
0772     snprintf(channel->caps.name, sizeof(channel->caps.name),
0773          "IDT 82P33 PLL%u", index);
0774 
0775     channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
0776 
0777     if (IS_ERR(channel->ptp_clock)) {
0778         err = PTR_ERR(channel->ptp_clock);
0779         channel->ptp_clock = NULL;
0780         return err;
0781     }
0782 
0783     if (!channel->ptp_clock)
0784         return -ENOTSUPP;
0785 
0786     err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
0787     if (err) {
0788         dev_err(idt82p33->dev,
0789             "Dpll_set_mode failed in %s with err %d!\n",
0790             __func__, err);
0791         return err;
0792     }
0793 
0794     err = idt82p33_enable_tod(channel);
0795     if (err) {
0796         dev_err(idt82p33->dev,
0797             "Enable_tod failed in %s with err %d!\n",
0798             __func__, err);
0799         return err;
0800     }
0801 
0802     dev_info(idt82p33->dev, "PLL%d registered as ptp%d\n",
0803          index, channel->ptp_clock->index);
0804 
0805     return 0;
0806 }
0807 
0808 static int idt82p33_load_firmware(struct idt82p33 *idt82p33)
0809 {
0810     const struct firmware *fw;
0811     struct idt82p33_fwrc *rec;
0812     u8 loaddr, page, val;
0813     int err;
0814     s32 len;
0815 
0816     dev_dbg(idt82p33->dev, "requesting firmware '%s'\n", FW_FILENAME);
0817 
0818     err = request_firmware(&fw, FW_FILENAME, idt82p33->dev);
0819 
0820     if (err) {
0821         dev_err(idt82p33->dev,
0822             "Failed in %s with err %d!\n", __func__, err);
0823         return err;
0824     }
0825 
0826     dev_dbg(idt82p33->dev, "firmware size %zu bytes\n", fw->size);
0827 
0828     rec = (struct idt82p33_fwrc *) fw->data;
0829 
0830     for (len = fw->size; len > 0; len -= sizeof(*rec)) {
0831 
0832         if (rec->reserved) {
0833             dev_err(idt82p33->dev,
0834                 "bad firmware, reserved field non-zero\n");
0835             err = -EINVAL;
0836         } else {
0837             val = rec->value;
0838             loaddr = rec->loaddr;
0839             page = rec->hiaddr;
0840 
0841             rec++;
0842 
0843             err = idt82p33_check_and_set_masks(idt82p33, page,
0844                                loaddr, val);
0845         }
0846 
0847         if (err == 0) {
0848             /* Page size 128, last 4 bytes of page skipped */
0849             if (loaddr > 0x7b)
0850                 continue;
0851 
0852             err = idt82p33_write(idt82p33, REG_ADDR(page, loaddr),
0853                          &val, sizeof(val));
0854         }
0855 
0856         if (err)
0857             goto out;
0858     }
0859 
0860     idt82p33_display_masks(idt82p33);
0861 out:
0862     release_firmware(fw);
0863     return err;
0864 }
0865 
0866 
0867 static int idt82p33_probe(struct platform_device *pdev)
0868 {
0869     struct rsmu_ddata *ddata = dev_get_drvdata(pdev->dev.parent);
0870     struct idt82p33 *idt82p33;
0871     int err;
0872     u8 i;
0873 
0874     idt82p33 = devm_kzalloc(&pdev->dev,
0875                 sizeof(struct idt82p33), GFP_KERNEL);
0876     if (!idt82p33)
0877         return -ENOMEM;
0878 
0879     idt82p33->dev = &pdev->dev;
0880     idt82p33->mfd = pdev->dev.parent;
0881     idt82p33->lock = &ddata->lock;
0882     idt82p33->regmap = ddata->regmap;
0883     idt82p33->tod_write_overhead_ns = 0;
0884     idt82p33->calculate_overhead_flag = 0;
0885     idt82p33->pll_mask = DEFAULT_PLL_MASK;
0886     idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
0887     idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
0888 
0889     mutex_lock(idt82p33->lock);
0890 
0891     err = idt82p33_load_firmware(idt82p33);
0892 
0893     if (err)
0894         dev_warn(idt82p33->dev,
0895              "loading firmware failed with %d\n", err);
0896 
0897     if (idt82p33->pll_mask) {
0898         for (i = 0; i < MAX_PHC_PLL; i++) {
0899             if (idt82p33->pll_mask & (1 << i)) {
0900                 err = idt82p33_enable_channel(idt82p33, i);
0901                 if (err) {
0902                     dev_err(idt82p33->dev,
0903                         "Failed in %s with err %d!\n",
0904                         __func__, err);
0905                     break;
0906                 }
0907             }
0908         }
0909     } else {
0910         dev_err(idt82p33->dev,
0911             "no PLLs flagged as PHCs, nothing to do\n");
0912         err = -ENODEV;
0913     }
0914 
0915     mutex_unlock(idt82p33->lock);
0916 
0917     if (err) {
0918         idt82p33_ptp_clock_unregister_all(idt82p33);
0919         return err;
0920     }
0921 
0922     platform_set_drvdata(pdev, idt82p33);
0923 
0924     return 0;
0925 }
0926 
0927 static int idt82p33_remove(struct platform_device *pdev)
0928 {
0929     struct idt82p33 *idt82p33 = platform_get_drvdata(pdev);
0930 
0931     idt82p33_ptp_clock_unregister_all(idt82p33);
0932 
0933     return 0;
0934 }
0935 
0936 static struct platform_driver idt82p33_driver = {
0937     .driver = {
0938         .name = "82p33x1x-phc",
0939     },
0940     .probe = idt82p33_probe,
0941     .remove = idt82p33_remove,
0942 };
0943 
0944 module_platform_driver(idt82p33_driver);
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