drivers/ptp/ptp_clockmatrix.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
0004  * synchronization devices.
0005  *
0006  * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
0007  */
0008 #ifndef PTP_IDTCLOCKMATRIX_H
0009 #define PTP_IDTCLOCKMATRIX_H
0010
0011 #include <linux/ktime.h>
0012 #include <linux/mfd/idt8a340_reg.h>
0013 #include <linux/ptp_clock.h>
0014 #include <linux/regmap.h>
0015
0016 #define FW_FILENAME "idtcm.bin"
0017 #define MAX_TOD     (4)
0018 #define MAX_PLL     (8)
0019 #define MAX_REF_CLK (16)
0020
0021 #define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
0022
0023 #define TOD_MASK_ADDR       (0xFFA5)
0024 #define DEFAULT_TOD_MASK    (0x04)
0025
0026 #define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
0027 #define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))
0028
0029 #define TOD0_PTP_PLL_ADDR       (0xFFA8)
0030 #define TOD1_PTP_PLL_ADDR       (0xFFA9)
0031 #define TOD2_PTP_PLL_ADDR       (0xFFAA)
0032 #define TOD3_PTP_PLL_ADDR       (0xFFAB)
0033
0034 #define TOD0_OUT_ALIGN_MASK_ADDR    (0xFFB0)
0035 #define TOD1_OUT_ALIGN_MASK_ADDR    (0xFFB2)
0036 #define TOD2_OUT_ALIGN_MASK_ADDR    (0xFFB4)
0037 #define TOD3_OUT_ALIGN_MASK_ADDR    (0xFFB6)
0038
0039 #define DEFAULT_OUTPUT_MASK_PLL0    (0x003)
0040 #define DEFAULT_OUTPUT_MASK_PLL1    (0x00c)
0041 #define DEFAULT_OUTPUT_MASK_PLL2    (0x030)
0042 #define DEFAULT_OUTPUT_MASK_PLL3    (0x0c0)
0043
0044 #define DEFAULT_TOD0_PTP_PLL        (0)
0045 #define DEFAULT_TOD1_PTP_PLL        (1)
0046 #define DEFAULT_TOD2_PTP_PLL        (2)
0047 #define DEFAULT_TOD3_PTP_PLL        (3)
0048
0049 #define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED   (150000)
0050 #define PHASE_PULL_IN_THRESHOLD_NS      (15000)
0051 #define TOD_WRITE_OVERHEAD_COUNT_MAX        (2)
0052 #define TOD_BYTE_COUNT              (11)
0053
0054 #define LOCK_TIMEOUT_MS         (2000)
0055 #define LOCK_POLL_INTERVAL_MS       (10)
0056
0057 #define IDTCM_MAX_WRITE_COUNT       (512)
0058
0059 #define PHASE_PULL_IN_MAX_PPB       (144000)
0060 #define PHASE_PULL_IN_MIN_THRESHOLD_NS  (2)
0061
0062 /*
0063  * Return register address based on passed in firmware version
0064  */
0065 #define IDTCM_FW_REG(FW, VER, REG)  (((FW) < (VER)) ? (REG) : (REG##_##VER))
0066 enum fw_version {
0067     V_DEFAULT = 0,
0068     V487 = 1,
0069     V520 = 2,
0070 };
0071
0072 /* PTP PLL Mode */
0073 enum ptp_pll_mode {
0074     PTP_PLL_MODE_MIN = 0,
0075     PTP_PLL_MODE_WRITE_FREQUENCY = PTP_PLL_MODE_MIN,
0076     PTP_PLL_MODE_WRITE_PHASE,
0077     PTP_PLL_MODE_UNSUPPORTED,
0078     PTP_PLL_MODE_MAX = PTP_PLL_MODE_UNSUPPORTED,
0079 };
0080
0081 struct idtcm;
0082
0083 struct idtcm_channel {
0084     struct ptp_clock_info   caps;
0085     struct ptp_clock    *ptp_clock;
0086     struct idtcm        *idtcm;
0087     u16         dpll_phase;
0088     u16         dpll_freq;
0089     u16         dpll_n;
0090     u16         dpll_ctrl_n;
0091     u16         dpll_phase_pull_in;
0092     u16         tod_read_primary;
0093     u16         tod_read_secondary;
0094     u16         tod_write;
0095     u16         tod_n;
0096     u16         hw_dpll_n;
0097     u8          sync_src;
0098     enum ptp_pll_mode   mode;
0099     int         (*configure_write_frequency)(struct idtcm_channel *channel);
0100     int         (*configure_write_phase)(struct idtcm_channel *channel);
0101     int         (*do_phase_pull_in)(struct idtcm_channel *channel,
0102                             s32 offset_ns, u32 max_ffo_ppb);
0103     s32         current_freq_scaled_ppm;
0104     bool            phase_pull_in;
0105     u32         dco_delay;
0106     /* last input trigger for extts */
0107     u8          refn;
0108     u8          pll;
0109     u8          tod;
0110     u16         output_mask;
0111 };
0112
0113 struct idtcm {
0114     struct idtcm_channel    channel[MAX_TOD];
0115     struct device       *dev;
0116     u8          tod_mask;
0117     char            version[16];
0118     enum fw_version     fw_ver;
0119     /* Polls for external time stamps */
0120     u8          extts_mask;
0121     bool            extts_single_shot;
0122     struct delayed_work extts_work;
0123     /* Remember the ptp channel to report extts */
0124     struct idtcm_channel    *event_channel[MAX_TOD];
0125     /* Mutex to protect operations from being interrupted */
0126     struct mutex        *lock;
0127     struct device       *mfd;
0128     struct regmap       *regmap;
0129     /* Overhead calculation for adjtime */
0130     u8          calculate_overhead_flag;
0131     s64         tod_write_overhead_ns;
0132     ktime_t         start_time;
0133 };
0134
0135 struct idtcm_fwrc {
0136     u8 hiaddr;
0137     u8 loaddr;
0138     u8 value;
0139     u8 reserved;
0140 } __packed;
0141
0142 #endif /* PTP_IDTCLOCKMATRIX_H */