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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
0004  * synchronization devices.
0005  *
0006  * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
0007  */
0008 #include <linux/firmware.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/module.h>
0011 #include <linux/ptp_clock_kernel.h>
0012 #include <linux/delay.h>
0013 #include <linux/jiffies.h>
0014 #include <linux/kernel.h>
0015 #include <linux/timekeeping.h>
0016 #include <linux/string.h>
0017 #include <linux/of.h>
0018 #include <linux/mfd/rsmu.h>
0019 #include <linux/mfd/idt8a340_reg.h>
0020 #include <asm/unaligned.h>
0021 
0022 #include "ptp_private.h"
0023 #include "ptp_clockmatrix.h"
0024 
0025 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
0026 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
0027 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
0028 MODULE_VERSION("1.0");
0029 MODULE_LICENSE("GPL");
0030 
0031 /*
0032  * The name of the firmware file to be loaded
0033  * over-rides any automatic selection
0034  */
0035 static char *firmware;
0036 module_param(firmware, charp, 0);
0037 
0038 #define SETTIME_CORRECTION (0)
0039 #define EXTTS_PERIOD_MS (95)
0040 
0041 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
0042 
0043 static inline int idtcm_read(struct idtcm *idtcm,
0044                  u16 module,
0045                  u16 regaddr,
0046                  u8 *buf,
0047                  u16 count)
0048 {
0049     return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count);
0050 }
0051 
0052 static inline int idtcm_write(struct idtcm *idtcm,
0053                   u16 module,
0054                   u16 regaddr,
0055                   u8 *buf,
0056                   u16 count)
0057 {
0058     return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count);
0059 }
0060 
0061 static int contains_full_configuration(struct idtcm *idtcm,
0062                        const struct firmware *fw)
0063 {
0064     struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
0065     u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
0066     s32 full_count;
0067     s32 count = 0;
0068     u16 regaddr;
0069     u8 loaddr;
0070     s32 len;
0071 
0072     /* 4 bytes skipped every 0x80 */
0073     full_count = (scratch - GPIO_USER_CONTROL) -
0074              ((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4;
0075 
0076     /* If the firmware contains 'full configuration' SM_RESET can be used
0077      * to ensure proper configuration.
0078      *
0079      * Full configuration is defined as the number of programmable
0080      * bytes within the configuration range minus page offset addr range.
0081      */
0082     for (len = fw->size; len > 0; len -= sizeof(*rec)) {
0083         regaddr = rec->hiaddr << 8;
0084         regaddr |= rec->loaddr;
0085 
0086         loaddr = rec->loaddr;
0087 
0088         rec++;
0089 
0090         /* Top (status registers) and bottom are read-only */
0091         if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
0092             continue;
0093 
0094         /* Page size 128, last 4 bytes of page skipped */
0095         if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
0096             continue;
0097 
0098         count++;
0099     }
0100 
0101     return (count >= full_count);
0102 }
0103 
0104 static int char_array_to_timespec(u8 *buf,
0105                   u8 count,
0106                   struct timespec64 *ts)
0107 {
0108     u8 i;
0109     u64 nsec;
0110     time64_t sec;
0111 
0112     if (count < TOD_BYTE_COUNT)
0113         return 1;
0114 
0115     /* Sub-nanoseconds are in buf[0]. */
0116     nsec = buf[4];
0117     for (i = 0; i < 3; i++) {
0118         nsec <<= 8;
0119         nsec |= buf[3 - i];
0120     }
0121 
0122     sec = buf[10];
0123     for (i = 0; i < 5; i++) {
0124         sec <<= 8;
0125         sec |= buf[9 - i];
0126     }
0127 
0128     ts->tv_sec = sec;
0129     ts->tv_nsec = nsec;
0130 
0131     return 0;
0132 }
0133 
0134 static int timespec_to_char_array(struct timespec64 const *ts,
0135                   u8 *buf,
0136                   u8 count)
0137 {
0138     u8 i;
0139     s32 nsec;
0140     time64_t sec;
0141 
0142     if (count < TOD_BYTE_COUNT)
0143         return 1;
0144 
0145     nsec = ts->tv_nsec;
0146     sec = ts->tv_sec;
0147 
0148     /* Sub-nanoseconds are in buf[0]. */
0149     buf[0] = 0;
0150     for (i = 1; i < 5; i++) {
0151         buf[i] = nsec & 0xff;
0152         nsec >>= 8;
0153     }
0154 
0155     for (i = 5; i < TOD_BYTE_COUNT; i++) {
0156 
0157         buf[i] = sec & 0xff;
0158         sec >>= 8;
0159     }
0160 
0161     return 0;
0162 }
0163 
0164 static int idtcm_strverscmp(const char *version1, const char *version2)
0165 {
0166     u8 ver1[3], ver2[3];
0167     int i;
0168 
0169     if (sscanf(version1, "%hhu.%hhu.%hhu",
0170            &ver1[0], &ver1[1], &ver1[2]) != 3)
0171         return -1;
0172     if (sscanf(version2, "%hhu.%hhu.%hhu",
0173            &ver2[0], &ver2[1], &ver2[2]) != 3)
0174         return -1;
0175 
0176     for (i = 0; i < 3; i++) {
0177         if (ver1[i] > ver2[i])
0178             return 1;
0179         if (ver1[i] < ver2[i])
0180             return -1;
0181     }
0182 
0183     return 0;
0184 }
0185 
0186 static enum fw_version idtcm_fw_version(const char *version)
0187 {
0188     enum fw_version ver = V_DEFAULT;
0189 
0190     if (idtcm_strverscmp(version, "4.8.7") >= 0)
0191         ver = V487;
0192 
0193     if (idtcm_strverscmp(version, "5.2.0") >= 0)
0194         ver = V520;
0195 
0196     return ver;
0197 }
0198 
0199 static int clear_boot_status(struct idtcm *idtcm)
0200 {
0201     u8 buf[4] = {0};
0202 
0203     return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
0204 }
0205 
0206 static int read_boot_status(struct idtcm *idtcm, u32 *status)
0207 {
0208     int err;
0209     u8 buf[4] = {0};
0210 
0211     err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
0212 
0213     *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
0214 
0215     return err;
0216 }
0217 
0218 static int wait_for_boot_status_ready(struct idtcm *idtcm)
0219 {
0220     u32 status = 0;
0221     u8 i = 30;  /* 30 * 100ms = 3s */
0222     int err;
0223 
0224     do {
0225         err = read_boot_status(idtcm, &status);
0226         if (err)
0227             return err;
0228 
0229         if (status == 0xA0)
0230             return 0;
0231 
0232         msleep(100);
0233         i--;
0234 
0235     } while (i);
0236 
0237     dev_warn(idtcm->dev, "%s timed out", __func__);
0238 
0239     return -EBUSY;
0240 }
0241 
0242 static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref)
0243 {
0244     struct idtcm *idtcm = channel->idtcm;
0245     u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
0246     u8 val = 0;
0247     int err;
0248 
0249     val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT);
0250     val |= (ref << WR_REF_INDEX_SHIFT);
0251 
0252     err = idtcm_write(idtcm, channel->tod_read_secondary,
0253               TOD_READ_SECONDARY_SEL_CFG_0, &val, sizeof(val));
0254     if (err)
0255         return err;
0256 
0257     val = 0 | (SCSR_TOD_READ_TRIG_SEL_REFCLK << TOD_READ_TRIGGER_SHIFT);
0258 
0259     err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,
0260               &val, sizeof(val));
0261     if (err)
0262         dev_err(idtcm->dev, "%s: err = %d", __func__, err);
0263 
0264     return err;
0265 }
0266 
0267 static bool is_single_shot(u8 mask)
0268 {
0269     /* Treat single bit ToD masks as continuous trigger */
0270     return !(mask <= 8 && is_power_of_2(mask));
0271 }
0272 
0273 static int idtcm_extts_enable(struct idtcm_channel *channel,
0274                   struct ptp_clock_request *rq, int on)
0275 {
0276     u8 index = rq->extts.index;
0277     struct idtcm *idtcm;
0278     u8 mask = 1 << index;
0279     int err = 0;
0280     u8 old_mask;
0281     int ref;
0282 
0283     idtcm = channel->idtcm;
0284     old_mask = idtcm->extts_mask;
0285 
0286     /* Reject requests with unsupported flags */
0287     if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
0288                 PTP_RISING_EDGE |
0289                 PTP_FALLING_EDGE |
0290                 PTP_STRICT_FLAGS))
0291         return -EOPNOTSUPP;
0292 
0293     /* Reject requests to enable time stamping on falling edge */
0294     if ((rq->extts.flags & PTP_ENABLE_FEATURE) &&
0295         (rq->extts.flags & PTP_FALLING_EDGE))
0296         return -EOPNOTSUPP;
0297 
0298     if (index >= MAX_TOD)
0299         return -EINVAL;
0300 
0301     if (on) {
0302         /* Support triggering more than one TOD_0/1/2/3 by same pin */
0303         /* Use the pin configured for the channel */
0304         ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->tod);
0305 
0306         if (ref < 0) {
0307             dev_err(idtcm->dev, "%s: No valid pin found for TOD%d!\n",
0308                 __func__, channel->tod);
0309             return -EBUSY;
0310         }
0311 
0312         err = arm_tod_read_trig_sel_refclk(&idtcm->channel[index], ref);
0313 
0314         if (err == 0) {
0315             idtcm->extts_mask |= mask;
0316             idtcm->event_channel[index] = channel;
0317             idtcm->channel[index].refn = ref;
0318             idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
0319 
0320             if (old_mask)
0321                 return 0;
0322 
0323             schedule_delayed_work(&idtcm->extts_work,
0324                           msecs_to_jiffies(EXTTS_PERIOD_MS));
0325         }
0326     } else {
0327         idtcm->extts_mask &= ~mask;
0328         idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
0329 
0330         if (idtcm->extts_mask == 0)
0331             cancel_delayed_work(&idtcm->extts_work);
0332     }
0333 
0334     return err;
0335 }
0336 
0337 static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
0338 {
0339     return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status,
0340               sizeof(u8));
0341 }
0342 
0343 static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status)
0344 {
0345     return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8));
0346 }
0347 
0348 static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
0349 {
0350     unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS);
0351     u8 apll = 0;
0352     u8 dpll = 0;
0353     int err;
0354 
0355     do {
0356         err = read_sys_apll_status(idtcm, &apll);
0357         if (err)
0358             return err;
0359 
0360         err = read_sys_dpll_status(idtcm, &dpll);
0361         if (err)
0362             return err;
0363 
0364         apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK;
0365         dpll &= DPLL_SYS_STATE_MASK;
0366 
0367         if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED &&
0368             dpll == DPLL_STATE_LOCKED) {
0369             return 0;
0370         } else if (dpll == DPLL_STATE_FREERUN ||
0371                dpll == DPLL_STATE_HOLDOVER ||
0372                dpll == DPLL_STATE_OPEN_LOOP) {
0373             dev_warn(idtcm->dev,
0374                 "No wait state: DPLL_SYS_STATE %d", dpll);
0375             return -EPERM;
0376         }
0377 
0378         msleep(LOCK_POLL_INTERVAL_MS);
0379     } while (time_is_after_jiffies(timeout));
0380 
0381     dev_warn(idtcm->dev,
0382          "%d ms lock timeout: SYS APLL Loss Lock %d  SYS DPLL state %d",
0383          LOCK_TIMEOUT_MS, apll, dpll);
0384 
0385     return -ETIME;
0386 }
0387 
0388 static void wait_for_chip_ready(struct idtcm *idtcm)
0389 {
0390     if (wait_for_boot_status_ready(idtcm))
0391         dev_warn(idtcm->dev, "BOOT_STATUS != 0xA0");
0392 
0393     if (wait_for_sys_apll_dpll_lock(idtcm))
0394         dev_warn(idtcm->dev,
0395              "Continuing while SYS APLL/DPLL is not locked");
0396 }
0397 
0398 static int _idtcm_gettime_triggered(struct idtcm_channel *channel,
0399                     struct timespec64 *ts)
0400 {
0401     struct idtcm *idtcm = channel->idtcm;
0402     u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
0403     u8 buf[TOD_BYTE_COUNT];
0404     u8 trigger;
0405     int err;
0406 
0407     err = idtcm_read(idtcm, channel->tod_read_secondary,
0408              tod_read_cmd, &trigger, sizeof(trigger));
0409     if (err)
0410         return err;
0411 
0412     if (trigger & TOD_READ_TRIGGER_MASK)
0413         return -EBUSY;
0414 
0415     err = idtcm_read(idtcm, channel->tod_read_secondary,
0416              TOD_READ_SECONDARY_BASE, buf, sizeof(buf));
0417     if (err)
0418         return err;
0419 
0420     return char_array_to_timespec(buf, sizeof(buf), ts);
0421 }
0422 
0423 static int _idtcm_gettime(struct idtcm_channel *channel,
0424               struct timespec64 *ts, u8 timeout)
0425 {
0426     struct idtcm *idtcm = channel->idtcm;
0427     u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
0428     u8 buf[TOD_BYTE_COUNT];
0429     u8 trigger;
0430     int err;
0431 
0432     /* wait trigger to be 0 */
0433     do {
0434         if (timeout-- == 0)
0435             return -EIO;
0436 
0437         if (idtcm->calculate_overhead_flag)
0438             idtcm->start_time = ktime_get_raw();
0439 
0440         err = idtcm_read(idtcm, channel->tod_read_primary,
0441                  tod_read_cmd, &trigger,
0442                  sizeof(trigger));
0443         if (err)
0444             return err;
0445     } while (trigger & TOD_READ_TRIGGER_MASK);
0446 
0447     err = idtcm_read(idtcm, channel->tod_read_primary,
0448              TOD_READ_PRIMARY_BASE, buf, sizeof(buf));
0449     if (err)
0450         return err;
0451 
0452     err = char_array_to_timespec(buf, sizeof(buf), ts);
0453 
0454     return err;
0455 }
0456 
0457 static int idtcm_extts_check_channel(struct idtcm *idtcm, u8 todn)
0458 {
0459     struct idtcm_channel *ptp_channel, *extts_channel;
0460     struct ptp_clock_event event;
0461     struct timespec64 ts;
0462     u32 dco_delay = 0;
0463     int err;
0464 
0465     extts_channel = &idtcm->channel[todn];
0466     ptp_channel = idtcm->event_channel[todn];
0467 
0468     if (extts_channel == ptp_channel)
0469         dco_delay = ptp_channel->dco_delay;
0470 
0471     err = _idtcm_gettime_triggered(extts_channel, &ts);
0472     if (err)
0473         return err;
0474 
0475     /* Triggered - save timestamp */
0476     event.type = PTP_CLOCK_EXTTS;
0477     event.index = todn;
0478     event.timestamp = timespec64_to_ns(&ts) - dco_delay;
0479     ptp_clock_event(ptp_channel->ptp_clock, &event);
0480 
0481     return err;
0482 }
0483 
0484 static int _idtcm_gettime_immediate(struct idtcm_channel *channel,
0485                     struct timespec64 *ts)
0486 {
0487     struct idtcm *idtcm = channel->idtcm;
0488 
0489     u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
0490     u8 val = (SCSR_TOD_READ_TRIG_SEL_IMMEDIATE << TOD_READ_TRIGGER_SHIFT);
0491     int err;
0492 
0493     err = idtcm_write(idtcm, channel->tod_read_primary,
0494               tod_read_cmd, &val, sizeof(val));
0495     if (err)
0496         return err;
0497 
0498     return _idtcm_gettime(channel, ts, 10);
0499 }
0500 
0501 static int _sync_pll_output(struct idtcm *idtcm,
0502                 u8 pll,
0503                 u8 sync_src,
0504                 u8 qn,
0505                 u8 qn_plus_1)
0506 {
0507     int err;
0508     u8 val;
0509     u16 sync_ctrl0;
0510     u16 sync_ctrl1;
0511     u8 temp;
0512 
0513     if (qn == 0 && qn_plus_1 == 0)
0514         return 0;
0515 
0516     switch (pll) {
0517     case 0:
0518         sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
0519         sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
0520         break;
0521     case 1:
0522         sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
0523         sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
0524         break;
0525     case 2:
0526         sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
0527         sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
0528         break;
0529     case 3:
0530         sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
0531         sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
0532         break;
0533     case 4:
0534         sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
0535         sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
0536         break;
0537     case 5:
0538         sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
0539         sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
0540         break;
0541     case 6:
0542         sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
0543         sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
0544         break;
0545     case 7:
0546         sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
0547         sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
0548         break;
0549     default:
0550         return -EINVAL;
0551     }
0552 
0553     val = SYNCTRL1_MASTER_SYNC_RST;
0554 
0555     /* Place master sync in reset */
0556     err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
0557     if (err)
0558         return err;
0559 
0560     err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
0561     if (err)
0562         return err;
0563 
0564     /* Set sync trigger mask */
0565     val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
0566 
0567     if (qn)
0568         val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
0569 
0570     if (qn_plus_1)
0571         val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
0572 
0573     err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
0574     if (err)
0575         return err;
0576 
0577     /* PLL5 can have OUT8 as second additional output. */
0578     if (pll == 5 && qn_plus_1 != 0) {
0579         err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
0580                  &temp, sizeof(temp));
0581         if (err)
0582             return err;
0583 
0584         temp &= ~(Q9_TO_Q8_SYNC_TRIG);
0585 
0586         err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
0587                   &temp, sizeof(temp));
0588         if (err)
0589             return err;
0590 
0591         temp |= Q9_TO_Q8_SYNC_TRIG;
0592 
0593         err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
0594                   &temp, sizeof(temp));
0595         if (err)
0596             return err;
0597     }
0598 
0599     /* PLL6 can have OUT11 as second additional output. */
0600     if (pll == 6 && qn_plus_1 != 0) {
0601         err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
0602                  &temp, sizeof(temp));
0603         if (err)
0604             return err;
0605 
0606         temp &= ~(Q10_TO_Q11_SYNC_TRIG);
0607 
0608         err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
0609                   &temp, sizeof(temp));
0610         if (err)
0611             return err;
0612 
0613         temp |= Q10_TO_Q11_SYNC_TRIG;
0614 
0615         err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
0616                   &temp, sizeof(temp));
0617         if (err)
0618             return err;
0619     }
0620 
0621     /* Place master sync out of reset */
0622     val &= ~(SYNCTRL1_MASTER_SYNC_RST);
0623     err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
0624 
0625     return err;
0626 }
0627 
0628 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
0629 {
0630     struct idtcm *idtcm = channel->idtcm;
0631     u8 pll;
0632     u8 qn;
0633     u8 qn_plus_1;
0634     int err = 0;
0635     u8 out8_mux = 0;
0636     u8 out11_mux = 0;
0637     u8 temp;
0638     u16 output_mask = channel->output_mask;
0639 
0640     err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
0641              &temp, sizeof(temp));
0642     if (err)
0643         return err;
0644 
0645     if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
0646         Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
0647         out8_mux = 1;
0648 
0649     err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
0650              &temp, sizeof(temp));
0651     if (err)
0652         return err;
0653 
0654     if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
0655         Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
0656         out11_mux = 1;
0657 
0658     for (pll = 0; pll < 8; pll++) {
0659         qn = 0;
0660         qn_plus_1 = 0;
0661 
0662         if (pll < 4) {
0663             /* First 4 pll has 2 outputs */
0664             qn = output_mask & 0x1;
0665             output_mask = output_mask >> 1;
0666             qn_plus_1 = output_mask & 0x1;
0667             output_mask = output_mask >> 1;
0668         } else if (pll == 4) {
0669             if (out8_mux == 0) {
0670                 qn = output_mask & 0x1;
0671                 output_mask = output_mask >> 1;
0672             }
0673         } else if (pll == 5) {
0674             if (out8_mux) {
0675                 qn_plus_1 = output_mask & 0x1;
0676                 output_mask = output_mask >> 1;
0677             }
0678             qn = output_mask & 0x1;
0679             output_mask = output_mask >> 1;
0680         } else if (pll == 6) {
0681             qn = output_mask & 0x1;
0682             output_mask = output_mask >> 1;
0683             if (out11_mux) {
0684                 qn_plus_1 = output_mask & 0x1;
0685                 output_mask = output_mask >> 1;
0686             }
0687         } else if (pll == 7) {
0688             if (out11_mux == 0) {
0689                 qn = output_mask & 0x1;
0690                 output_mask = output_mask >> 1;
0691             }
0692         }
0693 
0694         if (qn != 0 || qn_plus_1 != 0)
0695             err = _sync_pll_output(idtcm, pll, channel->sync_src,
0696                            qn, qn_plus_1);
0697 
0698         if (err)
0699             return err;
0700     }
0701 
0702     return err;
0703 }
0704 
0705 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
0706                   struct timespec64 const *ts,
0707                   enum hw_tod_write_trig_sel wr_trig)
0708 {
0709     struct idtcm *idtcm = channel->idtcm;
0710     u8 buf[TOD_BYTE_COUNT];
0711     u8 cmd;
0712     int err;
0713     struct timespec64 local_ts = *ts;
0714     s64 total_overhead_ns;
0715 
0716     /* Configure HW TOD write trigger. */
0717     err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
0718              &cmd, sizeof(cmd));
0719     if (err)
0720         return err;
0721 
0722     cmd &= ~(0x0f);
0723     cmd |= wr_trig | 0x08;
0724 
0725     err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
0726               &cmd, sizeof(cmd));
0727     if (err)
0728         return err;
0729 
0730     if (wr_trig  != HW_TOD_WR_TRIG_SEL_MSB) {
0731         err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
0732         if (err)
0733             return err;
0734 
0735         err = idtcm_write(idtcm, channel->hw_dpll_n,
0736                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
0737         if (err)
0738             return err;
0739     }
0740 
0741     /* ARM HW TOD write trigger. */
0742     cmd &= ~(0x08);
0743 
0744     err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
0745               &cmd, sizeof(cmd));
0746 
0747     if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
0748         if (idtcm->calculate_overhead_flag) {
0749             /* Assumption: I2C @ 400KHz */
0750             ktime_t diff = ktime_sub(ktime_get_raw(),
0751                          idtcm->start_time);
0752             total_overhead_ns =  ktime_to_ns(diff)
0753                          + idtcm->tod_write_overhead_ns
0754                          + SETTIME_CORRECTION;
0755 
0756             timespec64_add_ns(&local_ts, total_overhead_ns);
0757 
0758             idtcm->calculate_overhead_flag = 0;
0759         }
0760 
0761         err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
0762         if (err)
0763             return err;
0764 
0765         err = idtcm_write(idtcm, channel->hw_dpll_n,
0766                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
0767     }
0768 
0769     return err;
0770 }
0771 
0772 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
0773                     struct timespec64 const *ts,
0774                     enum scsr_tod_write_trig_sel wr_trig,
0775                     enum scsr_tod_write_type_sel wr_type)
0776 {
0777     struct idtcm *idtcm = channel->idtcm;
0778     unsigned char buf[TOD_BYTE_COUNT], cmd;
0779     struct timespec64 local_ts = *ts;
0780     int err, count = 0;
0781 
0782     timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
0783 
0784     err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
0785     if (err)
0786         return err;
0787 
0788     err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
0789               buf, sizeof(buf));
0790     if (err)
0791         return err;
0792 
0793     /* Trigger the write operation. */
0794     err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
0795              &cmd, sizeof(cmd));
0796     if (err)
0797         return err;
0798 
0799     cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
0800     cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
0801     cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
0802     cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
0803 
0804     err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
0805                &cmd, sizeof(cmd));
0806     if (err)
0807         return err;
0808 
0809     /* Wait for the operation to complete. */
0810     while (1) {
0811         /* pps trigger takes up to 1 sec to complete */
0812         if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
0813             msleep(50);
0814 
0815         err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
0816                  &cmd, sizeof(cmd));
0817         if (err)
0818             return err;
0819 
0820         if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
0821             break;
0822 
0823         if (++count > 20) {
0824             dev_err(idtcm->dev,
0825                 "Timed out waiting for the write counter");
0826             return -EIO;
0827         }
0828     }
0829 
0830     return 0;
0831 }
0832 
0833 static int get_output_base_addr(enum fw_version ver, u8 outn)
0834 {
0835     int base;
0836 
0837     switch (outn) {
0838     case 0:
0839         base = IDTCM_FW_REG(ver, V520, OUTPUT_0);
0840         break;
0841     case 1:
0842         base = IDTCM_FW_REG(ver, V520, OUTPUT_1);
0843         break;
0844     case 2:
0845         base = IDTCM_FW_REG(ver, V520, OUTPUT_2);
0846         break;
0847     case 3:
0848         base = IDTCM_FW_REG(ver, V520, OUTPUT_3);
0849         break;
0850     case 4:
0851         base = IDTCM_FW_REG(ver, V520, OUTPUT_4);
0852         break;
0853     case 5:
0854         base = IDTCM_FW_REG(ver, V520, OUTPUT_5);
0855         break;
0856     case 6:
0857         base = IDTCM_FW_REG(ver, V520, OUTPUT_6);
0858         break;
0859     case 7:
0860         base = IDTCM_FW_REG(ver, V520, OUTPUT_7);
0861         break;
0862     case 8:
0863         base = IDTCM_FW_REG(ver, V520, OUTPUT_8);
0864         break;
0865     case 9:
0866         base = IDTCM_FW_REG(ver, V520, OUTPUT_9);
0867         break;
0868     case 10:
0869         base = IDTCM_FW_REG(ver, V520, OUTPUT_10);
0870         break;
0871     case 11:
0872         base = IDTCM_FW_REG(ver, V520, OUTPUT_11);
0873         break;
0874     default:
0875         base = -EINVAL;
0876     }
0877 
0878     return base;
0879 }
0880 
0881 static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
0882                      struct timespec64 const *ts)
0883 {
0884     struct idtcm *idtcm = channel->idtcm;
0885     int err;
0886 
0887     err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
0888     if (err) {
0889         dev_err(idtcm->dev,
0890             "%s: Set HW ToD failed", __func__);
0891         return err;
0892     }
0893 
0894     return idtcm_sync_pps_output(channel);
0895 }
0896 
0897 static int _idtcm_settime(struct idtcm_channel *channel,
0898               struct timespec64 const *ts,
0899               enum scsr_tod_write_type_sel wr_type)
0900 {
0901     return _idtcm_set_dpll_scsr_tod(channel, ts,
0902                     SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
0903                     wr_type);
0904 }
0905 
0906 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
0907                       s32 offset_ns)
0908 {
0909     int err;
0910     int i;
0911     struct idtcm *idtcm = channel->idtcm;
0912     u8 buf[4];
0913 
0914     for (i = 0; i < 4; i++) {
0915         buf[i] = 0xff & (offset_ns);
0916         offset_ns >>= 8;
0917     }
0918 
0919     err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
0920               buf, sizeof(buf));
0921 
0922     return err;
0923 }
0924 
0925 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
0926                            u32 max_ffo_ppb)
0927 {
0928     int err;
0929     u8 i;
0930     struct idtcm *idtcm = channel->idtcm;
0931     u8 buf[3];
0932 
0933     if (max_ffo_ppb & 0xff000000)
0934         max_ffo_ppb = 0;
0935 
0936     for (i = 0; i < 3; i++) {
0937         buf[i] = 0xff & (max_ffo_ppb);
0938         max_ffo_ppb >>= 8;
0939     }
0940 
0941     err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
0942               PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
0943 
0944     return err;
0945 }
0946 
0947 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
0948 {
0949     int err;
0950     struct idtcm *idtcm = channel->idtcm;
0951     u8 buf;
0952 
0953     err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
0954              &buf, sizeof(buf));
0955     if (err)
0956         return err;
0957 
0958     if (buf == 0) {
0959         buf = 0x01;
0960         err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
0961                   PULL_IN_CTRL, &buf, sizeof(buf));
0962     } else {
0963         err = -EBUSY;
0964     }
0965 
0966     return err;
0967 }
0968 
0969 static int do_phase_pull_in_fw(struct idtcm_channel *channel,
0970                    s32 offset_ns,
0971                    u32 max_ffo_ppb)
0972 {
0973     int err;
0974 
0975     err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
0976     if (err)
0977         return err;
0978 
0979     err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
0980     if (err)
0981         return err;
0982 
0983     err = idtcm_start_phase_pull_in(channel);
0984 
0985     return err;
0986 }
0987 
0988 static int set_tod_write_overhead(struct idtcm_channel *channel)
0989 {
0990     struct idtcm *idtcm = channel->idtcm;
0991     s64 current_ns = 0;
0992     s64 lowest_ns = 0;
0993     int err;
0994     u8 i;
0995     ktime_t start;
0996     ktime_t stop;
0997     ktime_t diff;
0998 
0999     char buf[TOD_BYTE_COUNT] = {0};
1000 
1001     /* Set page offset */
1002     idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
1003             buf, sizeof(buf));
1004 
1005     for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
1006         start = ktime_get_raw();
1007 
1008         err = idtcm_write(idtcm, channel->hw_dpll_n,
1009                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
1010         if (err)
1011             return err;
1012 
1013         stop = ktime_get_raw();
1014 
1015         diff = ktime_sub(stop, start);
1016 
1017         current_ns = ktime_to_ns(diff);
1018 
1019         if (i == 0) {
1020             lowest_ns = current_ns;
1021         } else {
1022             if (current_ns < lowest_ns)
1023                 lowest_ns = current_ns;
1024         }
1025     }
1026 
1027     idtcm->tod_write_overhead_ns = lowest_ns;
1028 
1029     return err;
1030 }
1031 
1032 static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
1033 {
1034     int err;
1035     struct idtcm *idtcm = channel->idtcm;
1036     struct timespec64 ts;
1037     s64 now;
1038 
1039     if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) {
1040         err = channel->do_phase_pull_in(channel, delta, 0);
1041     } else {
1042         idtcm->calculate_overhead_flag = 1;
1043 
1044         err = set_tod_write_overhead(channel);
1045         if (err)
1046             return err;
1047 
1048         err = _idtcm_gettime_immediate(channel, &ts);
1049         if (err)
1050             return err;
1051 
1052         now = timespec64_to_ns(&ts);
1053         now += delta;
1054 
1055         ts = ns_to_timespec64(now);
1056 
1057         err = _idtcm_settime_deprecated(channel, &ts);
1058     }
1059 
1060     return err;
1061 }
1062 
1063 static int idtcm_state_machine_reset(struct idtcm *idtcm)
1064 {
1065     u8 byte = SM_RESET_CMD;
1066     u32 status = 0;
1067     int err;
1068     u8 i;
1069 
1070     clear_boot_status(idtcm);
1071 
1072     err = idtcm_write(idtcm, RESET_CTRL,
1073               IDTCM_FW_REG(idtcm->fw_ver, V520, SM_RESET),
1074               &byte, sizeof(byte));
1075 
1076     if (!err) {
1077         for (i = 0; i < 30; i++) {
1078             msleep_interruptible(100);
1079             read_boot_status(idtcm, &status);
1080 
1081             if (status == 0xA0) {
1082                 dev_dbg(idtcm->dev,
1083                     "SM_RESET completed in %d ms", i * 100);
1084                 break;
1085             }
1086         }
1087 
1088         if (!status)
1089             dev_err(idtcm->dev,
1090                 "Timed out waiting for CM_RESET to complete");
1091     }
1092 
1093     return err;
1094 }
1095 
1096 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
1097 {
1098     return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
1099 }
1100 
1101 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
1102 {
1103     int err;
1104     u8 buf[2] = {0};
1105 
1106     err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
1107 
1108     *product_id = (buf[1] << 8) | buf[0];
1109 
1110     return err;
1111 }
1112 
1113 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
1114 {
1115     int err;
1116     u8 buf = 0;
1117 
1118     err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
1119 
1120     *major = buf >> 1;
1121 
1122     return err;
1123 }
1124 
1125 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
1126 {
1127     return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
1128 }
1129 
1130 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
1131 {
1132     return idtcm_read(idtcm,
1133               GENERAL_STATUS,
1134               HOTFIX_REL,
1135               hotfix,
1136               sizeof(u8));
1137 }
1138 
1139 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
1140                          u8 *config_select)
1141 {
1142     return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
1143               config_select, sizeof(u8));
1144 }
1145 
1146 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
1147 {
1148     int err = 0;
1149 
1150     switch (addr) {
1151     case TOD0_OUT_ALIGN_MASK_ADDR:
1152         SET_U16_LSB(idtcm->channel[0].output_mask, val);
1153         break;
1154     case TOD0_OUT_ALIGN_MASK_ADDR + 1:
1155         SET_U16_MSB(idtcm->channel[0].output_mask, val);
1156         break;
1157     case TOD1_OUT_ALIGN_MASK_ADDR:
1158         SET_U16_LSB(idtcm->channel[1].output_mask, val);
1159         break;
1160     case TOD1_OUT_ALIGN_MASK_ADDR + 1:
1161         SET_U16_MSB(idtcm->channel[1].output_mask, val);
1162         break;
1163     case TOD2_OUT_ALIGN_MASK_ADDR:
1164         SET_U16_LSB(idtcm->channel[2].output_mask, val);
1165         break;
1166     case TOD2_OUT_ALIGN_MASK_ADDR + 1:
1167         SET_U16_MSB(idtcm->channel[2].output_mask, val);
1168         break;
1169     case TOD3_OUT_ALIGN_MASK_ADDR:
1170         SET_U16_LSB(idtcm->channel[3].output_mask, val);
1171         break;
1172     case TOD3_OUT_ALIGN_MASK_ADDR + 1:
1173         SET_U16_MSB(idtcm->channel[3].output_mask, val);
1174         break;
1175     default:
1176         err = -EFAULT; /* Bad address */;
1177         break;
1178     }
1179 
1180     return err;
1181 }
1182 
1183 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1184 {
1185     if (index >= MAX_TOD) {
1186         dev_err(idtcm->dev, "ToD%d not supported", index);
1187         return -EINVAL;
1188     }
1189 
1190     if (pll >= MAX_PLL) {
1191         dev_err(idtcm->dev, "Pll%d not supported", pll);
1192         return -EINVAL;
1193     }
1194 
1195     idtcm->channel[index].pll = pll;
1196 
1197     return 0;
1198 }
1199 
1200 static int check_and_set_masks(struct idtcm *idtcm,
1201                    u16 regaddr,
1202                    u8 val)
1203 {
1204     int err = 0;
1205 
1206     switch (regaddr) {
1207     case TOD_MASK_ADDR:
1208         if ((val & 0xf0) || !(val & 0x0f)) {
1209             dev_err(idtcm->dev, "Invalid TOD mask 0x%02x", val);
1210             err = -EINVAL;
1211         } else {
1212             idtcm->tod_mask = val;
1213         }
1214         break;
1215     case TOD0_PTP_PLL_ADDR:
1216         err = set_tod_ptp_pll(idtcm, 0, val);
1217         break;
1218     case TOD1_PTP_PLL_ADDR:
1219         err = set_tod_ptp_pll(idtcm, 1, val);
1220         break;
1221     case TOD2_PTP_PLL_ADDR:
1222         err = set_tod_ptp_pll(idtcm, 2, val);
1223         break;
1224     case TOD3_PTP_PLL_ADDR:
1225         err = set_tod_ptp_pll(idtcm, 3, val);
1226         break;
1227     default:
1228         err = set_pll_output_mask(idtcm, regaddr, val);
1229         break;
1230     }
1231 
1232     return err;
1233 }
1234 
1235 static void display_pll_and_masks(struct idtcm *idtcm)
1236 {
1237     u8 i;
1238     u8 mask;
1239 
1240     dev_dbg(idtcm->dev, "tod_mask = 0x%02x", idtcm->tod_mask);
1241 
1242     for (i = 0; i < MAX_TOD; i++) {
1243         mask = 1 << i;
1244 
1245         if (mask & idtcm->tod_mask)
1246             dev_dbg(idtcm->dev,
1247                 "TOD%d pll = %d    output_mask = 0x%04x",
1248                 i, idtcm->channel[i].pll,
1249                 idtcm->channel[i].output_mask);
1250     }
1251 }
1252 
1253 static int idtcm_load_firmware(struct idtcm *idtcm,
1254                    struct device *dev)
1255 {
1256     u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
1257     char fname[128] = FW_FILENAME;
1258     const struct firmware *fw;
1259     struct idtcm_fwrc *rec;
1260     u32 regaddr;
1261     int err;
1262     s32 len;
1263     u8 val;
1264     u8 loaddr;
1265 
1266     if (firmware) /* module parameter */
1267         snprintf(fname, sizeof(fname), "%s", firmware);
1268 
1269     dev_info(idtcm->dev, "requesting firmware '%s'", fname);
1270 
1271     err = request_firmware(&fw, fname, dev);
1272     if (err) {
1273         dev_err(idtcm->dev,
1274             "Failed at line %d in %s!", __LINE__, __func__);
1275         return err;
1276     }
1277 
1278     dev_dbg(idtcm->dev, "firmware size %zu bytes", fw->size);
1279 
1280     rec = (struct idtcm_fwrc *) fw->data;
1281 
1282     if (contains_full_configuration(idtcm, fw))
1283         idtcm_state_machine_reset(idtcm);
1284 
1285     for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1286         if (rec->reserved) {
1287             dev_err(idtcm->dev,
1288                 "bad firmware, reserved field non-zero");
1289             err = -EINVAL;
1290         } else {
1291             regaddr = rec->hiaddr << 8;
1292             regaddr |= rec->loaddr;
1293 
1294             val = rec->value;
1295             loaddr = rec->loaddr;
1296 
1297             rec++;
1298 
1299             err = check_and_set_masks(idtcm, regaddr, val);
1300         }
1301 
1302         if (err != -EINVAL) {
1303             err = 0;
1304 
1305             /* Top (status registers) and bottom are read-only */
1306             if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
1307                 continue;
1308 
1309             /* Page size 128, last 4 bytes of page skipped */
1310             if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
1311                 continue;
1312 
1313             err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1314         }
1315 
1316         if (err)
1317             goto out;
1318     }
1319 
1320     display_pll_and_masks(idtcm);
1321 
1322 out:
1323     release_firmware(fw);
1324     return err;
1325 }
1326 
1327 static int idtcm_output_enable(struct idtcm_channel *channel,
1328                    bool enable, unsigned int outn)
1329 {
1330     struct idtcm *idtcm = channel->idtcm;
1331     int base;
1332     int err;
1333     u8 val;
1334 
1335     base = get_output_base_addr(idtcm->fw_ver, outn);
1336 
1337     if (!(base > 0)) {
1338         dev_err(idtcm->dev,
1339             "%s - Unsupported out%d", __func__, outn);
1340         return base;
1341     }
1342 
1343     err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1344     if (err)
1345         return err;
1346 
1347     if (enable)
1348         val |= SQUELCH_DISABLE;
1349     else
1350         val &= ~SQUELCH_DISABLE;
1351 
1352     return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1353 }
1354 
1355 static int idtcm_perout_enable(struct idtcm_channel *channel,
1356                    struct ptp_perout_request *perout,
1357                    bool enable)
1358 {
1359     struct idtcm *idtcm = channel->idtcm;
1360     struct timespec64 ts = {0, 0};
1361     int err;
1362 
1363     err = idtcm_output_enable(channel, enable, perout->index);
1364 
1365     if (err) {
1366         dev_err(idtcm->dev, "Unable to set output enable");
1367         return err;
1368     }
1369 
1370     /* Align output to internal 1 PPS */
1371     return _idtcm_settime(channel, &ts, SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS);
1372 }
1373 
1374 static int idtcm_get_pll_mode(struct idtcm_channel *channel,
1375                   enum pll_mode *mode)
1376 {
1377     struct idtcm *idtcm = channel->idtcm;
1378     int err;
1379     u8 dpll_mode;
1380 
1381     err = idtcm_read(idtcm, channel->dpll_n,
1382              IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1383              &dpll_mode, sizeof(dpll_mode));
1384     if (err)
1385         return err;
1386 
1387     *mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
1388 
1389     return 0;
1390 }
1391 
1392 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1393                   enum pll_mode mode)
1394 {
1395     struct idtcm *idtcm = channel->idtcm;
1396     int err;
1397     u8 dpll_mode;
1398 
1399     err = idtcm_read(idtcm, channel->dpll_n,
1400              IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1401              &dpll_mode, sizeof(dpll_mode));
1402     if (err)
1403         return err;
1404 
1405     dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1406 
1407     dpll_mode |= (mode << PLL_MODE_SHIFT);
1408 
1409     err = idtcm_write(idtcm, channel->dpll_n,
1410               IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1411               &dpll_mode, sizeof(dpll_mode));
1412     return err;
1413 }
1414 
1415 static int idtcm_get_manual_reference(struct idtcm_channel *channel,
1416                       enum manual_reference *ref)
1417 {
1418     struct idtcm *idtcm = channel->idtcm;
1419     u8 dpll_manu_ref_cfg;
1420     int err;
1421 
1422     err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1423              DPLL_CTRL_DPLL_MANU_REF_CFG,
1424              &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1425     if (err)
1426         return err;
1427 
1428     dpll_manu_ref_cfg &= (MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT);
1429 
1430     *ref = dpll_manu_ref_cfg >> MANUAL_REFERENCE_SHIFT;
1431 
1432     return 0;
1433 }
1434 
1435 static int idtcm_set_manual_reference(struct idtcm_channel *channel,
1436                       enum manual_reference ref)
1437 {
1438     struct idtcm *idtcm = channel->idtcm;
1439     u8 dpll_manu_ref_cfg;
1440     int err;
1441 
1442     err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1443              DPLL_CTRL_DPLL_MANU_REF_CFG,
1444              &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1445     if (err)
1446         return err;
1447 
1448     dpll_manu_ref_cfg &= ~(MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT);
1449 
1450     dpll_manu_ref_cfg |= (ref << MANUAL_REFERENCE_SHIFT);
1451 
1452     err = idtcm_write(idtcm, channel->dpll_ctrl_n,
1453               DPLL_CTRL_DPLL_MANU_REF_CFG,
1454               &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1455 
1456     return err;
1457 }
1458 
1459 static int configure_dpll_mode_write_frequency(struct idtcm_channel *channel)
1460 {
1461     struct idtcm *idtcm = channel->idtcm;
1462     int err;
1463 
1464     err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1465 
1466     if (err)
1467         dev_err(idtcm->dev, "Failed to set pll mode to write frequency");
1468     else
1469         channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1470 
1471     return err;
1472 }
1473 
1474 static int configure_dpll_mode_write_phase(struct idtcm_channel *channel)
1475 {
1476     struct idtcm *idtcm = channel->idtcm;
1477     int err;
1478 
1479     err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1480 
1481     if (err)
1482         dev_err(idtcm->dev, "Failed to set pll mode to write phase");
1483     else
1484         channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1485 
1486     return err;
1487 }
1488 
1489 static int configure_manual_reference_write_frequency(struct idtcm_channel *channel)
1490 {
1491     struct idtcm *idtcm = channel->idtcm;
1492     int err;
1493 
1494     err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_FREQUENCY);
1495 
1496     if (err)
1497         dev_err(idtcm->dev, "Failed to set manual reference to write frequency");
1498     else
1499         channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1500 
1501     return err;
1502 }
1503 
1504 static int configure_manual_reference_write_phase(struct idtcm_channel *channel)
1505 {
1506     struct idtcm *idtcm = channel->idtcm;
1507     int err;
1508 
1509     err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_PHASE);
1510 
1511     if (err)
1512         dev_err(idtcm->dev, "Failed to set manual reference to write phase");
1513     else
1514         channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1515 
1516     return err;
1517 }
1518 
1519 static int idtcm_stop_phase_pull_in(struct idtcm_channel *channel)
1520 {
1521     int err;
1522 
1523     err = _idtcm_adjfine(channel, channel->current_freq_scaled_ppm);
1524     if (err)
1525         return err;
1526 
1527     channel->phase_pull_in = false;
1528 
1529     return 0;
1530 }
1531 
1532 static long idtcm_work_handler(struct ptp_clock_info *ptp)
1533 {
1534     struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1535     struct idtcm *idtcm = channel->idtcm;
1536 
1537     mutex_lock(idtcm->lock);
1538 
1539     (void)idtcm_stop_phase_pull_in(channel);
1540 
1541     mutex_unlock(idtcm->lock);
1542 
1543     /* Return a negative value here to not reschedule */
1544     return -1;
1545 }
1546 
1547 static s32 phase_pull_in_scaled_ppm(s32 current_ppm, s32 phase_pull_in_ppb)
1548 {
1549     /* ppb = scaled_ppm * 125 / 2^13 */
1550     /* scaled_ppm = ppb * 2^13 / 125 */
1551 
1552     s64 max_scaled_ppm = div_s64((s64)PHASE_PULL_IN_MAX_PPB << 13, 125);
1553     s64 scaled_ppm = div_s64((s64)phase_pull_in_ppb << 13, 125);
1554 
1555     current_ppm += scaled_ppm;
1556 
1557     if (current_ppm > max_scaled_ppm)
1558         current_ppm = max_scaled_ppm;
1559     else if (current_ppm < -max_scaled_ppm)
1560         current_ppm = -max_scaled_ppm;
1561 
1562     return current_ppm;
1563 }
1564 
1565 static int do_phase_pull_in_sw(struct idtcm_channel *channel,
1566                    s32 delta_ns,
1567                    u32 max_ffo_ppb)
1568 {
1569     s32 current_ppm = channel->current_freq_scaled_ppm;
1570     u32 duration_ms = MSEC_PER_SEC;
1571     s32 delta_ppm;
1572     s32 ppb;
1573     int err;
1574 
1575     /* If the ToD correction is less than PHASE_PULL_IN_MIN_THRESHOLD_NS,
1576      * skip. The error introduced by the ToD adjustment procedure would
1577      * be bigger than the required ToD correction
1578      */
1579     if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS)
1580         return 0;
1581 
1582     if (max_ffo_ppb == 0)
1583         max_ffo_ppb = PHASE_PULL_IN_MAX_PPB;
1584 
1585     /* For most cases, keep phase pull-in duration 1 second */
1586     ppb = delta_ns;
1587     while (abs(ppb) > max_ffo_ppb) {
1588         duration_ms *= 2;
1589         ppb /= 2;
1590     }
1591 
1592     delta_ppm = phase_pull_in_scaled_ppm(current_ppm, ppb);
1593 
1594     err = _idtcm_adjfine(channel, delta_ppm);
1595 
1596     if (err)
1597         return err;
1598 
1599     /* schedule the worker to cancel phase pull-in */
1600     ptp_schedule_worker(channel->ptp_clock,
1601                 msecs_to_jiffies(duration_ms) - 1);
1602 
1603     channel->phase_pull_in = true;
1604 
1605     return 0;
1606 }
1607 
1608 static int initialize_operating_mode_with_manual_reference(struct idtcm_channel *channel,
1609                                enum manual_reference ref)
1610 {
1611     struct idtcm *idtcm = channel->idtcm;
1612 
1613     channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1614     channel->configure_write_frequency = configure_manual_reference_write_frequency;
1615     channel->configure_write_phase = configure_manual_reference_write_phase;
1616     channel->do_phase_pull_in = do_phase_pull_in_sw;
1617 
1618     switch (ref) {
1619     case MANU_REF_WRITE_PHASE:
1620         channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1621         break;
1622     case MANU_REF_WRITE_FREQUENCY:
1623         channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1624         break;
1625     default:
1626         dev_warn(idtcm->dev,
1627              "Unsupported MANUAL_REFERENCE: 0x%02x", ref);
1628     }
1629 
1630     return 0;
1631 }
1632 
1633 static int initialize_operating_mode_with_pll_mode(struct idtcm_channel *channel,
1634                            enum pll_mode mode)
1635 {
1636     struct idtcm *idtcm = channel->idtcm;
1637     int err = 0;
1638 
1639     channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1640     channel->configure_write_frequency = configure_dpll_mode_write_frequency;
1641     channel->configure_write_phase = configure_dpll_mode_write_phase;
1642     channel->do_phase_pull_in = do_phase_pull_in_fw;
1643 
1644     switch (mode) {
1645     case  PLL_MODE_WRITE_PHASE:
1646         channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1647         break;
1648     case PLL_MODE_WRITE_FREQUENCY:
1649         channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1650         break;
1651     default:
1652         dev_err(idtcm->dev,
1653             "Unsupported PLL_MODE: 0x%02x", mode);
1654         err = -EINVAL;
1655     }
1656 
1657     return err;
1658 }
1659 
1660 static int initialize_dco_operating_mode(struct idtcm_channel *channel)
1661 {
1662     enum manual_reference ref = MANU_REF_XO_DPLL;
1663     enum pll_mode mode = PLL_MODE_DISABLED;
1664     struct idtcm *idtcm = channel->idtcm;
1665     int err;
1666 
1667     channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1668 
1669     err = idtcm_get_pll_mode(channel, &mode);
1670     if (err) {
1671         dev_err(idtcm->dev, "Unable to read pll mode!");
1672         return err;
1673     }
1674 
1675     if (mode == PLL_MODE_PLL) {
1676         err = idtcm_get_manual_reference(channel, &ref);
1677         if (err) {
1678             dev_err(idtcm->dev, "Unable to read manual reference!");
1679             return err;
1680         }
1681         err = initialize_operating_mode_with_manual_reference(channel, ref);
1682     } else {
1683         err = initialize_operating_mode_with_pll_mode(channel, mode);
1684     }
1685 
1686     if (channel->mode == PTP_PLL_MODE_WRITE_PHASE)
1687         channel->configure_write_frequency(channel);
1688 
1689     return err;
1690 }
1691 
1692 /* PTP Hardware Clock interface */
1693 
1694 /*
1695  * Maximum absolute value for write phase offset in picoseconds
1696  *
1697  * @channel:  channel
1698  * @delta_ns: delta in nanoseconds
1699  *
1700  * Destination signed register is 32-bit register in resolution of 50ps
1701  *
1702  * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
1703  */
1704 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1705 {
1706     struct idtcm *idtcm = channel->idtcm;
1707     int err;
1708     u8 i;
1709     u8 buf[4] = {0};
1710     s32 phase_50ps;
1711     s64 offset_ps;
1712 
1713     if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
1714         err = channel->configure_write_phase(channel);
1715         if (err)
1716             return err;
1717     }
1718 
1719     offset_ps = (s64)delta_ns * 1000;
1720 
1721     /*
1722      * Check for 32-bit signed max * 50:
1723      *
1724      * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
1725      */
1726     if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1727         offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1728     else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1729         offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1730 
1731     phase_50ps = div_s64(offset_ps, 50);
1732 
1733     for (i = 0; i < 4; i++) {
1734         buf[i] = phase_50ps & 0xff;
1735         phase_50ps >>= 8;
1736     }
1737 
1738     err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1739               buf, sizeof(buf));
1740 
1741     return err;
1742 }
1743 
1744 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1745 {
1746     struct idtcm *idtcm = channel->idtcm;
1747     u8 i;
1748     int err;
1749     u8 buf[6] = {0};
1750     s64 fcw;
1751 
1752     if (channel->mode  != PTP_PLL_MODE_WRITE_FREQUENCY) {
1753         err = channel->configure_write_frequency(channel);
1754         if (err)
1755             return err;
1756     }
1757 
1758     /*
1759      * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1760      *
1761      * adjfreq:
1762      *       ppb * 10^9
1763      * FCW = ----------
1764      *          111
1765      *
1766      * adjfine:
1767      *       ppm_16 * 5^12
1768      * FCW = -------------
1769      *         111 * 2^4
1770      */
1771 
1772     /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
1773     fcw = scaled_ppm * 244140625ULL;
1774 
1775     fcw = div_s64(fcw, 1776);
1776 
1777     for (i = 0; i < 6; i++) {
1778         buf[i] = fcw & 0xff;
1779         fcw >>= 8;
1780     }
1781 
1782     err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1783               buf, sizeof(buf));
1784 
1785     return err;
1786 }
1787 
1788 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1789 {
1790     struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1791     struct idtcm *idtcm = channel->idtcm;
1792     int err;
1793 
1794     mutex_lock(idtcm->lock);
1795     err = _idtcm_gettime_immediate(channel, ts);
1796     mutex_unlock(idtcm->lock);
1797 
1798     if (err)
1799         dev_err(idtcm->dev, "Failed at line %d in %s!",
1800             __LINE__, __func__);
1801 
1802     return err;
1803 }
1804 
1805 static int idtcm_settime_deprecated(struct ptp_clock_info *ptp,
1806                     const struct timespec64 *ts)
1807 {
1808     struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1809     struct idtcm *idtcm = channel->idtcm;
1810     int err;
1811 
1812     mutex_lock(idtcm->lock);
1813     err = _idtcm_settime_deprecated(channel, ts);
1814     mutex_unlock(idtcm->lock);
1815 
1816     if (err)
1817         dev_err(idtcm->dev,
1818             "Failed at line %d in %s!", __LINE__, __func__);
1819 
1820     return err;
1821 }
1822 
1823 static int idtcm_settime(struct ptp_clock_info *ptp,
1824              const struct timespec64 *ts)
1825 {
1826     struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1827     struct idtcm *idtcm = channel->idtcm;
1828     int err;
1829 
1830     mutex_lock(idtcm->lock);
1831     err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1832     mutex_unlock(idtcm->lock);
1833 
1834     if (err)
1835         dev_err(idtcm->dev,
1836             "Failed at line %d in %s!", __LINE__, __func__);
1837 
1838     return err;
1839 }
1840 
1841 static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta)
1842 {
1843     struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1844     struct idtcm *idtcm = channel->idtcm;
1845     int err;
1846 
1847     mutex_lock(idtcm->lock);
1848     err = _idtcm_adjtime_deprecated(channel, delta);
1849     mutex_unlock(idtcm->lock);
1850 
1851     if (err)
1852         dev_err(idtcm->dev,
1853             "Failed at line %d in %s!", __LINE__, __func__);
1854 
1855     return err;
1856 }
1857 
1858 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1859 {
1860     struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1861     struct idtcm *idtcm = channel->idtcm;
1862     struct timespec64 ts;
1863     enum scsr_tod_write_type_sel type;
1864     int err;
1865 
1866     if (channel->phase_pull_in == true)
1867         return -EBUSY;
1868 
1869     mutex_lock(idtcm->lock);
1870 
1871     if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
1872         err = channel->do_phase_pull_in(channel, delta, 0);
1873     } else {
1874         if (delta >= 0) {
1875             ts = ns_to_timespec64(delta);
1876             type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1877         } else {
1878             ts = ns_to_timespec64(-delta);
1879             type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1880         }
1881         err = _idtcm_settime(channel, &ts, type);
1882     }
1883 
1884     mutex_unlock(idtcm->lock);
1885 
1886     if (err)
1887         dev_err(idtcm->dev,
1888             "Failed at line %d in %s!", __LINE__, __func__);
1889 
1890     return err;
1891 }
1892 
1893 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1894 {
1895     struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1896     struct idtcm *idtcm = channel->idtcm;
1897     int err;
1898 
1899     mutex_lock(idtcm->lock);
1900     err = _idtcm_adjphase(channel, delta);
1901     mutex_unlock(idtcm->lock);
1902 
1903     if (err)
1904         dev_err(idtcm->dev,
1905             "Failed at line %d in %s!", __LINE__, __func__);
1906 
1907     return err;
1908 }
1909 
1910 static int idtcm_adjfine(struct ptp_clock_info *ptp,  long scaled_ppm)
1911 {
1912     struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1913     struct idtcm *idtcm = channel->idtcm;
1914     int err;
1915 
1916     if (channel->phase_pull_in == true)
1917         return 0;
1918 
1919     if (scaled_ppm == channel->current_freq_scaled_ppm)
1920         return 0;
1921 
1922     mutex_lock(idtcm->lock);
1923     err = _idtcm_adjfine(channel, scaled_ppm);
1924     mutex_unlock(idtcm->lock);
1925 
1926     if (err)
1927         dev_err(idtcm->dev,
1928             "Failed at line %d in %s!", __LINE__, __func__);
1929     else
1930         channel->current_freq_scaled_ppm = scaled_ppm;
1931 
1932     return err;
1933 }
1934 
1935 static int idtcm_enable(struct ptp_clock_info *ptp,
1936             struct ptp_clock_request *rq, int on)
1937 {
1938     struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1939     struct idtcm *idtcm = channel->idtcm;
1940     int err = -EOPNOTSUPP;
1941 
1942     mutex_lock(idtcm->lock);
1943 
1944     switch (rq->type) {
1945     case PTP_CLK_REQ_PEROUT:
1946         if (!on)
1947             err = idtcm_perout_enable(channel, &rq->perout, false);
1948         /* Only accept a 1-PPS aligned to the second. */
1949         else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1950              rq->perout.period.nsec)
1951             err = -ERANGE;
1952         else
1953             err = idtcm_perout_enable(channel, &rq->perout, true);
1954         break;
1955     case PTP_CLK_REQ_EXTTS:
1956         err = idtcm_extts_enable(channel, rq, on);
1957         break;
1958     default:
1959         break;
1960     }
1961 
1962     mutex_unlock(idtcm->lock);
1963 
1964     if (err)
1965         dev_err(channel->idtcm->dev,
1966             "Failed in %s with err %d!", __func__, err);
1967 
1968     return err;
1969 }
1970 
1971 static int idtcm_enable_tod(struct idtcm_channel *channel)
1972 {
1973     struct idtcm *idtcm = channel->idtcm;
1974     struct timespec64 ts = {0, 0};
1975     u16 tod_cfg = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_CFG);
1976     u8 cfg;
1977     int err;
1978 
1979     /*
1980      * Start the TOD clock ticking.
1981      */
1982     err = idtcm_read(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
1983     if (err)
1984         return err;
1985 
1986     cfg |= TOD_ENABLE;
1987 
1988     err = idtcm_write(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
1989     if (err)
1990         return err;
1991 
1992     if (idtcm->fw_ver < V487)
1993         return _idtcm_settime_deprecated(channel, &ts);
1994     else
1995         return _idtcm_settime(channel, &ts,
1996                       SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1997 }
1998 
1999 static void idtcm_set_version_info(struct idtcm *idtcm)
2000 {
2001     u8 major;
2002     u8 minor;
2003     u8 hotfix;
2004     u16 product_id;
2005     u8 hw_rev_id;
2006     u8 config_select;
2007 
2008     idtcm_read_major_release(idtcm, &major);
2009     idtcm_read_minor_release(idtcm, &minor);
2010     idtcm_read_hotfix_release(idtcm, &hotfix);
2011 
2012     idtcm_read_product_id(idtcm, &product_id);
2013     idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
2014 
2015     idtcm_read_otp_scsr_config_select(idtcm, &config_select);
2016 
2017     snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
2018          major, minor, hotfix);
2019 
2020     idtcm->fw_ver = idtcm_fw_version(idtcm->version);
2021 
2022     dev_info(idtcm->dev,
2023          "%d.%d.%d, Id: 0x%04x  HW Rev: %d  OTP Config Select: %d",
2024          major, minor, hotfix,
2025          product_id, hw_rev_id, config_select);
2026 }
2027 
2028 static int idtcm_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
2029                 enum ptp_pin_function func, unsigned int chan)
2030 {
2031     switch (func) {
2032     case PTP_PF_NONE:
2033     case PTP_PF_EXTTS:
2034         break;
2035     case PTP_PF_PEROUT:
2036     case PTP_PF_PHYSYNC:
2037         return -1;
2038     }
2039     return 0;
2040 }
2041 
2042 static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK];
2043 
2044 static const struct ptp_clock_info idtcm_caps = {
2045     .owner      = THIS_MODULE,
2046     .max_adj    = 244000,
2047     .n_per_out  = 12,
2048     .n_ext_ts   = MAX_TOD,
2049     .n_pins     = MAX_REF_CLK,
2050     .adjphase   = &idtcm_adjphase,
2051     .adjfine    = &idtcm_adjfine,
2052     .adjtime    = &idtcm_adjtime,
2053     .gettime64  = &idtcm_gettime,
2054     .settime64  = &idtcm_settime,
2055     .enable     = &idtcm_enable,
2056     .verify     = &idtcm_verify_pin,
2057     .do_aux_work    = &idtcm_work_handler,
2058 };
2059 
2060 static const struct ptp_clock_info idtcm_caps_deprecated = {
2061     .owner      = THIS_MODULE,
2062     .max_adj    = 244000,
2063     .n_per_out  = 12,
2064     .n_ext_ts   = MAX_TOD,
2065     .n_pins     = MAX_REF_CLK,
2066     .adjphase   = &idtcm_adjphase,
2067     .adjfine    = &idtcm_adjfine,
2068     .adjtime    = &idtcm_adjtime_deprecated,
2069     .gettime64  = &idtcm_gettime,
2070     .settime64  = &idtcm_settime_deprecated,
2071     .enable     = &idtcm_enable,
2072     .verify     = &idtcm_verify_pin,
2073     .do_aux_work    = &idtcm_work_handler,
2074 };
2075 
2076 static int configure_channel_pll(struct idtcm_channel *channel)
2077 {
2078     struct idtcm *idtcm = channel->idtcm;
2079     int err = 0;
2080 
2081     switch (channel->pll) {
2082     case 0:
2083         channel->dpll_freq = DPLL_FREQ_0;
2084         channel->dpll_n = DPLL_0;
2085         channel->hw_dpll_n = HW_DPLL_0;
2086         channel->dpll_phase = DPLL_PHASE_0;
2087         channel->dpll_ctrl_n = DPLL_CTRL_0;
2088         channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
2089         break;
2090     case 1:
2091         channel->dpll_freq = DPLL_FREQ_1;
2092         channel->dpll_n = DPLL_1;
2093         channel->hw_dpll_n = HW_DPLL_1;
2094         channel->dpll_phase = DPLL_PHASE_1;
2095         channel->dpll_ctrl_n = DPLL_CTRL_1;
2096         channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
2097         break;
2098     case 2:
2099         channel->dpll_freq = DPLL_FREQ_2;
2100         channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_2);
2101         channel->hw_dpll_n = HW_DPLL_2;
2102         channel->dpll_phase = DPLL_PHASE_2;
2103         channel->dpll_ctrl_n = DPLL_CTRL_2;
2104         channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
2105         break;
2106     case 3:
2107         channel->dpll_freq = DPLL_FREQ_3;
2108         channel->dpll_n = DPLL_3;
2109         channel->hw_dpll_n = HW_DPLL_3;
2110         channel->dpll_phase = DPLL_PHASE_3;
2111         channel->dpll_ctrl_n = DPLL_CTRL_3;
2112         channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
2113         break;
2114     case 4:
2115         channel->dpll_freq = DPLL_FREQ_4;
2116         channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_4);
2117         channel->hw_dpll_n = HW_DPLL_4;
2118         channel->dpll_phase = DPLL_PHASE_4;
2119         channel->dpll_ctrl_n = DPLL_CTRL_4;
2120         channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
2121         break;
2122     case 5:
2123         channel->dpll_freq = DPLL_FREQ_5;
2124         channel->dpll_n = DPLL_5;
2125         channel->hw_dpll_n = HW_DPLL_5;
2126         channel->dpll_phase = DPLL_PHASE_5;
2127         channel->dpll_ctrl_n = DPLL_CTRL_5;
2128         channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
2129         break;
2130     case 6:
2131         channel->dpll_freq = DPLL_FREQ_6;
2132         channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_6);
2133         channel->hw_dpll_n = HW_DPLL_6;
2134         channel->dpll_phase = DPLL_PHASE_6;
2135         channel->dpll_ctrl_n = DPLL_CTRL_6;
2136         channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
2137         break;
2138     case 7:
2139         channel->dpll_freq = DPLL_FREQ_7;
2140         channel->dpll_n = DPLL_7;
2141         channel->hw_dpll_n = HW_DPLL_7;
2142         channel->dpll_phase = DPLL_PHASE_7;
2143         channel->dpll_ctrl_n = DPLL_CTRL_7;
2144         channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
2145         break;
2146     default:
2147         err = -EINVAL;
2148     }
2149 
2150     return err;
2151 }
2152 
2153 /*
2154  * Compensate for the PTP DCO input-to-output delay.
2155  * This delay is 18 FOD cycles.
2156  */
2157 static u32 idtcm_get_dco_delay(struct idtcm_channel *channel)
2158 {
2159     struct idtcm *idtcm = channel->idtcm;
2160     u8 mbuf[8] = {0};
2161     u8 nbuf[2] = {0};
2162     u32 fodFreq;
2163     int err;
2164     u64 m;
2165     u16 n;
2166 
2167     err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2168              DPLL_CTRL_DPLL_FOD_FREQ, mbuf, 6);
2169     if (err)
2170         return 0;
2171 
2172     err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2173              DPLL_CTRL_DPLL_FOD_FREQ + 6, nbuf, 2);
2174     if (err)
2175         return 0;
2176 
2177     m = get_unaligned_le64(mbuf);
2178     n = get_unaligned_le16(nbuf);
2179 
2180     if (n == 0)
2181         n = 1;
2182 
2183     fodFreq = (u32)div_u64(m, n);
2184 
2185     if (fodFreq >= 500000000)
2186         return (u32)div_u64(18 * (u64)NSEC_PER_SEC, fodFreq);
2187 
2188     return 0;
2189 }
2190 
2191 static int configure_channel_tod(struct idtcm_channel *channel, u32 index)
2192 {
2193     enum fw_version fw_ver = channel->idtcm->fw_ver;
2194 
2195     /* Set tod addresses */
2196     switch (index) {
2197     case 0:
2198         channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_0);
2199         channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_0);
2200         channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_0);
2201         channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_0);
2202         channel->sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
2203         break;
2204     case 1:
2205         channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_1);
2206         channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_1);
2207         channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_1);
2208         channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_1);
2209         channel->sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
2210         break;
2211     case 2:
2212         channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_2);
2213         channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_2);
2214         channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_2);
2215         channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_2);
2216         channel->sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
2217         break;
2218     case 3:
2219         channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_3);
2220         channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_3);
2221         channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_3);
2222         channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_3);
2223         channel->sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
2224         break;
2225     default:
2226         return -EINVAL;
2227     }
2228 
2229     return 0;
2230 }
2231 
2232 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
2233 {
2234     struct idtcm_channel *channel;
2235     int err;
2236     int i;
2237 
2238     if (!(index < MAX_TOD))
2239         return -EINVAL;
2240 
2241     channel = &idtcm->channel[index];
2242 
2243     channel->idtcm = idtcm;
2244     channel->current_freq_scaled_ppm = 0;
2245 
2246     /* Set pll addresses */
2247     err = configure_channel_pll(channel);
2248     if (err)
2249         return err;
2250 
2251     /* Set tod addresses */
2252     err = configure_channel_tod(channel, index);
2253     if (err)
2254         return err;
2255 
2256     if (idtcm->fw_ver < V487)
2257         channel->caps = idtcm_caps_deprecated;
2258     else
2259         channel->caps = idtcm_caps;
2260 
2261     snprintf(channel->caps.name, sizeof(channel->caps.name),
2262          "IDT CM TOD%u", index);
2263 
2264     channel->caps.pin_config = pin_config[index];
2265 
2266     for (i = 0; i < channel->caps.n_pins; ++i) {
2267         struct ptp_pin_desc *ppd = &channel->caps.pin_config[i];
2268 
2269         snprintf(ppd->name, sizeof(ppd->name), "input_ref%d", i);
2270         ppd->index = i;
2271         ppd->func = PTP_PF_NONE;
2272         ppd->chan = index;
2273     }
2274 
2275     err = initialize_dco_operating_mode(channel);
2276     if (err)
2277         return err;
2278 
2279     err = idtcm_enable_tod(channel);
2280     if (err) {
2281         dev_err(idtcm->dev,
2282             "Failed at line %d in %s!", __LINE__, __func__);
2283         return err;
2284     }
2285 
2286     channel->dco_delay = idtcm_get_dco_delay(channel);
2287 
2288     channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2289 
2290     if (IS_ERR(channel->ptp_clock)) {
2291         err = PTR_ERR(channel->ptp_clock);
2292         channel->ptp_clock = NULL;
2293         return err;
2294     }
2295 
2296     if (!channel->ptp_clock)
2297         return -ENOTSUPP;
2298 
2299     dev_info(idtcm->dev, "PLL%d registered as ptp%d",
2300          index, channel->ptp_clock->index);
2301 
2302     return 0;
2303 }
2304 
2305 static int idtcm_enable_extts_channel(struct idtcm *idtcm, u32 index)
2306 {
2307     struct idtcm_channel *channel;
2308     int err;
2309 
2310     if (!(index < MAX_TOD))
2311         return -EINVAL;
2312 
2313     channel = &idtcm->channel[index];
2314     channel->idtcm = idtcm;
2315 
2316     /* Set tod addresses */
2317     err = configure_channel_tod(channel, index);
2318     if (err)
2319         return err;
2320 
2321     channel->idtcm = idtcm;
2322 
2323     return 0;
2324 }
2325 
2326 static void idtcm_extts_check(struct work_struct *work)
2327 {
2328     struct idtcm *idtcm = container_of(work, struct idtcm, extts_work.work);
2329     struct idtcm_channel *channel;
2330     u8 mask;
2331     int err;
2332     int i;
2333 
2334     if (idtcm->extts_mask == 0)
2335         return;
2336 
2337     mutex_lock(idtcm->lock);
2338 
2339     for (i = 0; i < MAX_TOD; i++) {
2340         mask = 1 << i;
2341 
2342         if ((idtcm->extts_mask & mask) == 0)
2343             continue;
2344 
2345         err = idtcm_extts_check_channel(idtcm, i);
2346 
2347         if (err == 0) {
2348             /* trigger clears itself, so clear the mask */
2349             if (idtcm->extts_single_shot) {
2350                 idtcm->extts_mask &= ~mask;
2351             } else {
2352                 /* Re-arm */
2353                 channel = &idtcm->channel[i];
2354                 arm_tod_read_trig_sel_refclk(channel, channel->refn);
2355             }
2356         }
2357     }
2358 
2359     if (idtcm->extts_mask)
2360         schedule_delayed_work(&idtcm->extts_work,
2361                       msecs_to_jiffies(EXTTS_PERIOD_MS));
2362 
2363     mutex_unlock(idtcm->lock);
2364 }
2365 
2366 static void ptp_clock_unregister_all(struct idtcm *idtcm)
2367 {
2368     u8 i;
2369     struct idtcm_channel *channel;
2370 
2371     for (i = 0; i < MAX_TOD; i++) {
2372         channel = &idtcm->channel[i];
2373         if (channel->ptp_clock)
2374             ptp_clock_unregister(channel->ptp_clock);
2375     }
2376 }
2377 
2378 static void set_default_masks(struct idtcm *idtcm)
2379 {
2380     idtcm->tod_mask = DEFAULT_TOD_MASK;
2381     idtcm->extts_mask = 0;
2382 
2383     idtcm->channel[0].tod = 0;
2384     idtcm->channel[1].tod = 1;
2385     idtcm->channel[2].tod = 2;
2386     idtcm->channel[3].tod = 3;
2387 
2388     idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2389     idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2390     idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2391     idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2392 
2393     idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2394     idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2395     idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2396     idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2397 }
2398 
2399 static int idtcm_probe(struct platform_device *pdev)
2400 {
2401     struct rsmu_ddata *ddata = dev_get_drvdata(pdev->dev.parent);
2402     struct idtcm *idtcm;
2403     int err;
2404     u8 i;
2405 
2406     idtcm = devm_kzalloc(&pdev->dev, sizeof(struct idtcm), GFP_KERNEL);
2407 
2408     if (!idtcm)
2409         return -ENOMEM;
2410 
2411     idtcm->dev = &pdev->dev;
2412     idtcm->mfd = pdev->dev.parent;
2413     idtcm->lock = &ddata->lock;
2414     idtcm->regmap = ddata->regmap;
2415     idtcm->calculate_overhead_flag = 0;
2416 
2417     INIT_DELAYED_WORK(&idtcm->extts_work, idtcm_extts_check);
2418 
2419     set_default_masks(idtcm);
2420 
2421     mutex_lock(idtcm->lock);
2422 
2423     idtcm_set_version_info(idtcm);
2424 
2425     err = idtcm_load_firmware(idtcm, &pdev->dev);
2426 
2427     if (err)
2428         dev_warn(idtcm->dev, "loading firmware failed with %d", err);
2429 
2430     wait_for_chip_ready(idtcm);
2431 
2432     if (idtcm->tod_mask) {
2433         for (i = 0; i < MAX_TOD; i++) {
2434             if (idtcm->tod_mask & (1 << i))
2435                 err = idtcm_enable_channel(idtcm, i);
2436             else
2437                 err = idtcm_enable_extts_channel(idtcm, i);
2438             if (err) {
2439                 dev_err(idtcm->dev,
2440                     "idtcm_enable_channel %d failed!", i);
2441                 break;
2442             }
2443         }
2444     } else {
2445         dev_err(idtcm->dev,
2446             "no PLLs flagged as PHCs, nothing to do");
2447         err = -ENODEV;
2448     }
2449 
2450     mutex_unlock(idtcm->lock);
2451 
2452     if (err) {
2453         ptp_clock_unregister_all(idtcm);
2454         return err;
2455     }
2456 
2457     platform_set_drvdata(pdev, idtcm);
2458 
2459     return 0;
2460 }
2461 
2462 static int idtcm_remove(struct platform_device *pdev)
2463 {
2464     struct idtcm *idtcm = platform_get_drvdata(pdev);
2465 
2466     idtcm->extts_mask = 0;
2467     ptp_clock_unregister_all(idtcm);
2468     cancel_delayed_work_sync(&idtcm->extts_work);
2469 
2470     return 0;
2471 }
2472 
2473 static struct platform_driver idtcm_driver = {
2474     .driver = {
2475         .name = "8a3400x-phc",
2476     },
2477     .probe = idtcm_probe,
2478     .remove = idtcm_remove,
2479 };
2480 
2481 module_platform_driver(idtcm_driver);
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