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0045 #include <linux/device.h>
0046 #include <linux/module.h>
0047 #include <linux/mutex.h>
0048 #include <linux/param.h>
0049 #include <linux/jiffies.h>
0050 #include <linux/workqueue.h>
0051 #include <linux/delay.h>
0052 #include <linux/platform_device.h>
0053 #include <linux/power_supply.h>
0054 #include <linux/slab.h>
0055 #include <linux/of.h>
0056
0057 #include <linux/power/bq27xxx_battery.h>
0058
0059 #define BQ27XXX_MANUFACTURER "Texas Instruments"
0060
0061
0062 #define BQ27XXX_FLAG_DSC BIT(0)
0063 #define BQ27XXX_FLAG_SOCF BIT(1)
0064 #define BQ27XXX_FLAG_SOC1 BIT(2)
0065 #define BQ27XXX_FLAG_CFGUP BIT(4)
0066 #define BQ27XXX_FLAG_FC BIT(9)
0067 #define BQ27XXX_FLAG_OTD BIT(14)
0068 #define BQ27XXX_FLAG_OTC BIT(15)
0069 #define BQ27XXX_FLAG_UT BIT(14)
0070 #define BQ27XXX_FLAG_OT BIT(15)
0071
0072
0073 #define BQ27000_FLAG_EDVF BIT(0)
0074 #define BQ27000_FLAG_EDV1 BIT(1)
0075 #define BQ27000_FLAG_CI BIT(4)
0076 #define BQ27000_FLAG_FC BIT(5)
0077 #define BQ27000_FLAG_CHGS BIT(7)
0078
0079
0080 #define BQ27Z561_FLAG_FDC BIT(4)
0081 #define BQ27Z561_FLAG_FC BIT(5)
0082 #define BQ27Z561_FLAG_DIS_CH BIT(6)
0083
0084
0085 #define BQ27XXX_SEALED 0x20
0086 #define BQ27XXX_SET_CFGUPDATE 0x13
0087 #define BQ27XXX_SOFT_RESET 0x42
0088 #define BQ27XXX_RESET 0x41
0089
0090 #define BQ27XXX_RS (20)
0091 #define BQ27XXX_POWER_CONSTANT (29200)
0092 #define BQ27XXX_CURRENT_CONSTANT (3570)
0093
0094 #define INVALID_REG_ADDR 0xff
0095
0096
0097
0098
0099
0100
0101
0102 enum bq27xxx_reg_index {
0103 BQ27XXX_REG_CTRL = 0,
0104 BQ27XXX_REG_TEMP,
0105 BQ27XXX_REG_INT_TEMP,
0106 BQ27XXX_REG_VOLT,
0107 BQ27XXX_REG_AI,
0108 BQ27XXX_REG_FLAGS,
0109 BQ27XXX_REG_TTE,
0110 BQ27XXX_REG_TTF,
0111 BQ27XXX_REG_TTES,
0112 BQ27XXX_REG_TTECP,
0113 BQ27XXX_REG_NAC,
0114 BQ27XXX_REG_RC,
0115 BQ27XXX_REG_FCC,
0116 BQ27XXX_REG_CYCT,
0117 BQ27XXX_REG_AE,
0118 BQ27XXX_REG_SOC,
0119 BQ27XXX_REG_DCAP,
0120 BQ27XXX_REG_AP,
0121 BQ27XXX_DM_CTRL,
0122 BQ27XXX_DM_CLASS,
0123 BQ27XXX_DM_BLOCK,
0124 BQ27XXX_DM_DATA,
0125 BQ27XXX_DM_CKSUM,
0126 BQ27XXX_REG_MAX,
0127 };
0128
0129 #define BQ27XXX_DM_REG_ROWS \
0130 [BQ27XXX_DM_CTRL] = 0x61, \
0131 [BQ27XXX_DM_CLASS] = 0x3e, \
0132 [BQ27XXX_DM_BLOCK] = 0x3f, \
0133 [BQ27XXX_DM_DATA] = 0x40, \
0134 [BQ27XXX_DM_CKSUM] = 0x60
0135
0136
0137 static u8
0138 bq27000_regs[BQ27XXX_REG_MAX] = {
0139 [BQ27XXX_REG_CTRL] = 0x00,
0140 [BQ27XXX_REG_TEMP] = 0x06,
0141 [BQ27XXX_REG_INT_TEMP] = INVALID_REG_ADDR,
0142 [BQ27XXX_REG_VOLT] = 0x08,
0143 [BQ27XXX_REG_AI] = 0x14,
0144 [BQ27XXX_REG_FLAGS] = 0x0a,
0145 [BQ27XXX_REG_TTE] = 0x16,
0146 [BQ27XXX_REG_TTF] = 0x18,
0147 [BQ27XXX_REG_TTES] = 0x1c,
0148 [BQ27XXX_REG_TTECP] = 0x26,
0149 [BQ27XXX_REG_NAC] = 0x0c,
0150 [BQ27XXX_REG_RC] = INVALID_REG_ADDR,
0151 [BQ27XXX_REG_FCC] = 0x12,
0152 [BQ27XXX_REG_CYCT] = 0x2a,
0153 [BQ27XXX_REG_AE] = 0x22,
0154 [BQ27XXX_REG_SOC] = 0x0b,
0155 [BQ27XXX_REG_DCAP] = 0x76,
0156 [BQ27XXX_REG_AP] = 0x24,
0157 [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
0158 [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
0159 [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
0160 [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
0161 [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
0162 },
0163 bq27010_regs[BQ27XXX_REG_MAX] = {
0164 [BQ27XXX_REG_CTRL] = 0x00,
0165 [BQ27XXX_REG_TEMP] = 0x06,
0166 [BQ27XXX_REG_INT_TEMP] = INVALID_REG_ADDR,
0167 [BQ27XXX_REG_VOLT] = 0x08,
0168 [BQ27XXX_REG_AI] = 0x14,
0169 [BQ27XXX_REG_FLAGS] = 0x0a,
0170 [BQ27XXX_REG_TTE] = 0x16,
0171 [BQ27XXX_REG_TTF] = 0x18,
0172 [BQ27XXX_REG_TTES] = 0x1c,
0173 [BQ27XXX_REG_TTECP] = 0x26,
0174 [BQ27XXX_REG_NAC] = 0x0c,
0175 [BQ27XXX_REG_RC] = INVALID_REG_ADDR,
0176 [BQ27XXX_REG_FCC] = 0x12,
0177 [BQ27XXX_REG_CYCT] = 0x2a,
0178 [BQ27XXX_REG_AE] = INVALID_REG_ADDR,
0179 [BQ27XXX_REG_SOC] = 0x0b,
0180 [BQ27XXX_REG_DCAP] = 0x76,
0181 [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
0182 [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
0183 [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
0184 [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
0185 [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
0186 [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
0187 },
0188 bq2750x_regs[BQ27XXX_REG_MAX] = {
0189 [BQ27XXX_REG_CTRL] = 0x00,
0190 [BQ27XXX_REG_TEMP] = 0x06,
0191 [BQ27XXX_REG_INT_TEMP] = 0x28,
0192 [BQ27XXX_REG_VOLT] = 0x08,
0193 [BQ27XXX_REG_AI] = 0x14,
0194 [BQ27XXX_REG_FLAGS] = 0x0a,
0195 [BQ27XXX_REG_TTE] = 0x16,
0196 [BQ27XXX_REG_TTF] = INVALID_REG_ADDR,
0197 [BQ27XXX_REG_TTES] = 0x1a,
0198 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0199 [BQ27XXX_REG_NAC] = 0x0c,
0200 [BQ27XXX_REG_RC] = 0x10,
0201 [BQ27XXX_REG_FCC] = 0x12,
0202 [BQ27XXX_REG_CYCT] = 0x2a,
0203 [BQ27XXX_REG_AE] = INVALID_REG_ADDR,
0204 [BQ27XXX_REG_SOC] = 0x2c,
0205 [BQ27XXX_REG_DCAP] = 0x3c,
0206 [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
0207 BQ27XXX_DM_REG_ROWS,
0208 },
0209 #define bq2751x_regs bq27510g3_regs
0210 #define bq2752x_regs bq27510g3_regs
0211 bq27500_regs[BQ27XXX_REG_MAX] = {
0212 [BQ27XXX_REG_CTRL] = 0x00,
0213 [BQ27XXX_REG_TEMP] = 0x06,
0214 [BQ27XXX_REG_INT_TEMP] = INVALID_REG_ADDR,
0215 [BQ27XXX_REG_VOLT] = 0x08,
0216 [BQ27XXX_REG_AI] = 0x14,
0217 [BQ27XXX_REG_FLAGS] = 0x0a,
0218 [BQ27XXX_REG_TTE] = 0x16,
0219 [BQ27XXX_REG_TTF] = 0x18,
0220 [BQ27XXX_REG_TTES] = 0x1c,
0221 [BQ27XXX_REG_TTECP] = 0x26,
0222 [BQ27XXX_REG_NAC] = 0x0c,
0223 [BQ27XXX_REG_RC] = 0x10,
0224 [BQ27XXX_REG_FCC] = 0x12,
0225 [BQ27XXX_REG_CYCT] = 0x2a,
0226 [BQ27XXX_REG_AE] = 0x22,
0227 [BQ27XXX_REG_SOC] = 0x2c,
0228 [BQ27XXX_REG_DCAP] = 0x3c,
0229 [BQ27XXX_REG_AP] = 0x24,
0230 BQ27XXX_DM_REG_ROWS,
0231 },
0232 #define bq27510g1_regs bq27500_regs
0233 #define bq27510g2_regs bq27500_regs
0234 bq27510g3_regs[BQ27XXX_REG_MAX] = {
0235 [BQ27XXX_REG_CTRL] = 0x00,
0236 [BQ27XXX_REG_TEMP] = 0x06,
0237 [BQ27XXX_REG_INT_TEMP] = 0x28,
0238 [BQ27XXX_REG_VOLT] = 0x08,
0239 [BQ27XXX_REG_AI] = 0x14,
0240 [BQ27XXX_REG_FLAGS] = 0x0a,
0241 [BQ27XXX_REG_TTE] = 0x16,
0242 [BQ27XXX_REG_TTF] = INVALID_REG_ADDR,
0243 [BQ27XXX_REG_TTES] = 0x1a,
0244 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0245 [BQ27XXX_REG_NAC] = 0x0c,
0246 [BQ27XXX_REG_RC] = 0x10,
0247 [BQ27XXX_REG_FCC] = 0x12,
0248 [BQ27XXX_REG_CYCT] = 0x1e,
0249 [BQ27XXX_REG_AE] = INVALID_REG_ADDR,
0250 [BQ27XXX_REG_SOC] = 0x20,
0251 [BQ27XXX_REG_DCAP] = 0x2e,
0252 [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
0253 BQ27XXX_DM_REG_ROWS,
0254 },
0255 bq27520g1_regs[BQ27XXX_REG_MAX] = {
0256 [BQ27XXX_REG_CTRL] = 0x00,
0257 [BQ27XXX_REG_TEMP] = 0x06,
0258 [BQ27XXX_REG_INT_TEMP] = INVALID_REG_ADDR,
0259 [BQ27XXX_REG_VOLT] = 0x08,
0260 [BQ27XXX_REG_AI] = 0x14,
0261 [BQ27XXX_REG_FLAGS] = 0x0a,
0262 [BQ27XXX_REG_TTE] = 0x16,
0263 [BQ27XXX_REG_TTF] = 0x18,
0264 [BQ27XXX_REG_TTES] = 0x1c,
0265 [BQ27XXX_REG_TTECP] = 0x26,
0266 [BQ27XXX_REG_NAC] = 0x0c,
0267 [BQ27XXX_REG_RC] = 0x10,
0268 [BQ27XXX_REG_FCC] = 0x12,
0269 [BQ27XXX_REG_CYCT] = INVALID_REG_ADDR,
0270 [BQ27XXX_REG_AE] = 0x22,
0271 [BQ27XXX_REG_SOC] = 0x2c,
0272 [BQ27XXX_REG_DCAP] = 0x3c,
0273 [BQ27XXX_REG_AP] = 0x24,
0274 BQ27XXX_DM_REG_ROWS,
0275 },
0276 bq27520g2_regs[BQ27XXX_REG_MAX] = {
0277 [BQ27XXX_REG_CTRL] = 0x00,
0278 [BQ27XXX_REG_TEMP] = 0x06,
0279 [BQ27XXX_REG_INT_TEMP] = 0x36,
0280 [BQ27XXX_REG_VOLT] = 0x08,
0281 [BQ27XXX_REG_AI] = 0x14,
0282 [BQ27XXX_REG_FLAGS] = 0x0a,
0283 [BQ27XXX_REG_TTE] = 0x16,
0284 [BQ27XXX_REG_TTF] = 0x18,
0285 [BQ27XXX_REG_TTES] = 0x1c,
0286 [BQ27XXX_REG_TTECP] = 0x26,
0287 [BQ27XXX_REG_NAC] = 0x0c,
0288 [BQ27XXX_REG_RC] = 0x10,
0289 [BQ27XXX_REG_FCC] = 0x12,
0290 [BQ27XXX_REG_CYCT] = 0x2a,
0291 [BQ27XXX_REG_AE] = 0x22,
0292 [BQ27XXX_REG_SOC] = 0x2c,
0293 [BQ27XXX_REG_DCAP] = 0x3c,
0294 [BQ27XXX_REG_AP] = 0x24,
0295 BQ27XXX_DM_REG_ROWS,
0296 },
0297 bq27520g3_regs[BQ27XXX_REG_MAX] = {
0298 [BQ27XXX_REG_CTRL] = 0x00,
0299 [BQ27XXX_REG_TEMP] = 0x06,
0300 [BQ27XXX_REG_INT_TEMP] = 0x36,
0301 [BQ27XXX_REG_VOLT] = 0x08,
0302 [BQ27XXX_REG_AI] = 0x14,
0303 [BQ27XXX_REG_FLAGS] = 0x0a,
0304 [BQ27XXX_REG_TTE] = 0x16,
0305 [BQ27XXX_REG_TTF] = INVALID_REG_ADDR,
0306 [BQ27XXX_REG_TTES] = 0x1c,
0307 [BQ27XXX_REG_TTECP] = 0x26,
0308 [BQ27XXX_REG_NAC] = 0x0c,
0309 [BQ27XXX_REG_RC] = 0x10,
0310 [BQ27XXX_REG_FCC] = 0x12,
0311 [BQ27XXX_REG_CYCT] = 0x2a,
0312 [BQ27XXX_REG_AE] = 0x22,
0313 [BQ27XXX_REG_SOC] = 0x2c,
0314 [BQ27XXX_REG_DCAP] = 0x3c,
0315 [BQ27XXX_REG_AP] = 0x24,
0316 BQ27XXX_DM_REG_ROWS,
0317 },
0318 bq27520g4_regs[BQ27XXX_REG_MAX] = {
0319 [BQ27XXX_REG_CTRL] = 0x00,
0320 [BQ27XXX_REG_TEMP] = 0x06,
0321 [BQ27XXX_REG_INT_TEMP] = 0x28,
0322 [BQ27XXX_REG_VOLT] = 0x08,
0323 [BQ27XXX_REG_AI] = 0x14,
0324 [BQ27XXX_REG_FLAGS] = 0x0a,
0325 [BQ27XXX_REG_TTE] = 0x16,
0326 [BQ27XXX_REG_TTF] = INVALID_REG_ADDR,
0327 [BQ27XXX_REG_TTES] = 0x1c,
0328 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0329 [BQ27XXX_REG_NAC] = 0x0c,
0330 [BQ27XXX_REG_RC] = 0x10,
0331 [BQ27XXX_REG_FCC] = 0x12,
0332 [BQ27XXX_REG_CYCT] = 0x1e,
0333 [BQ27XXX_REG_AE] = INVALID_REG_ADDR,
0334 [BQ27XXX_REG_SOC] = 0x20,
0335 [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
0336 [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
0337 BQ27XXX_DM_REG_ROWS,
0338 },
0339 bq27521_regs[BQ27XXX_REG_MAX] = {
0340 [BQ27XXX_REG_CTRL] = 0x02,
0341 [BQ27XXX_REG_TEMP] = 0x0a,
0342 [BQ27XXX_REG_INT_TEMP] = INVALID_REG_ADDR,
0343 [BQ27XXX_REG_VOLT] = 0x0c,
0344 [BQ27XXX_REG_AI] = 0x0e,
0345 [BQ27XXX_REG_FLAGS] = 0x08,
0346 [BQ27XXX_REG_TTE] = INVALID_REG_ADDR,
0347 [BQ27XXX_REG_TTF] = INVALID_REG_ADDR,
0348 [BQ27XXX_REG_TTES] = INVALID_REG_ADDR,
0349 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0350 [BQ27XXX_REG_NAC] = INVALID_REG_ADDR,
0351 [BQ27XXX_REG_RC] = INVALID_REG_ADDR,
0352 [BQ27XXX_REG_FCC] = INVALID_REG_ADDR,
0353 [BQ27XXX_REG_CYCT] = INVALID_REG_ADDR,
0354 [BQ27XXX_REG_AE] = INVALID_REG_ADDR,
0355 [BQ27XXX_REG_SOC] = INVALID_REG_ADDR,
0356 [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
0357 [BQ27XXX_REG_AP] = INVALID_REG_ADDR,
0358 [BQ27XXX_DM_CTRL] = INVALID_REG_ADDR,
0359 [BQ27XXX_DM_CLASS] = INVALID_REG_ADDR,
0360 [BQ27XXX_DM_BLOCK] = INVALID_REG_ADDR,
0361 [BQ27XXX_DM_DATA] = INVALID_REG_ADDR,
0362 [BQ27XXX_DM_CKSUM] = INVALID_REG_ADDR,
0363 },
0364 bq27530_regs[BQ27XXX_REG_MAX] = {
0365 [BQ27XXX_REG_CTRL] = 0x00,
0366 [BQ27XXX_REG_TEMP] = 0x06,
0367 [BQ27XXX_REG_INT_TEMP] = 0x32,
0368 [BQ27XXX_REG_VOLT] = 0x08,
0369 [BQ27XXX_REG_AI] = 0x14,
0370 [BQ27XXX_REG_FLAGS] = 0x0a,
0371 [BQ27XXX_REG_TTE] = 0x16,
0372 [BQ27XXX_REG_TTF] = INVALID_REG_ADDR,
0373 [BQ27XXX_REG_TTES] = INVALID_REG_ADDR,
0374 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0375 [BQ27XXX_REG_NAC] = 0x0c,
0376 [BQ27XXX_REG_RC] = 0x10,
0377 [BQ27XXX_REG_FCC] = 0x12,
0378 [BQ27XXX_REG_CYCT] = 0x2a,
0379 [BQ27XXX_REG_AE] = INVALID_REG_ADDR,
0380 [BQ27XXX_REG_SOC] = 0x2c,
0381 [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
0382 [BQ27XXX_REG_AP] = 0x24,
0383 BQ27XXX_DM_REG_ROWS,
0384 },
0385 #define bq27531_regs bq27530_regs
0386 bq27541_regs[BQ27XXX_REG_MAX] = {
0387 [BQ27XXX_REG_CTRL] = 0x00,
0388 [BQ27XXX_REG_TEMP] = 0x06,
0389 [BQ27XXX_REG_INT_TEMP] = 0x28,
0390 [BQ27XXX_REG_VOLT] = 0x08,
0391 [BQ27XXX_REG_AI] = 0x14,
0392 [BQ27XXX_REG_FLAGS] = 0x0a,
0393 [BQ27XXX_REG_TTE] = 0x16,
0394 [BQ27XXX_REG_TTF] = INVALID_REG_ADDR,
0395 [BQ27XXX_REG_TTES] = INVALID_REG_ADDR,
0396 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0397 [BQ27XXX_REG_NAC] = 0x0c,
0398 [BQ27XXX_REG_RC] = 0x10,
0399 [BQ27XXX_REG_FCC] = 0x12,
0400 [BQ27XXX_REG_CYCT] = 0x2a,
0401 [BQ27XXX_REG_AE] = INVALID_REG_ADDR,
0402 [BQ27XXX_REG_SOC] = 0x2c,
0403 [BQ27XXX_REG_DCAP] = 0x3c,
0404 [BQ27XXX_REG_AP] = 0x24,
0405 BQ27XXX_DM_REG_ROWS,
0406 },
0407 #define bq27542_regs bq27541_regs
0408 #define bq27546_regs bq27541_regs
0409 #define bq27742_regs bq27541_regs
0410 bq27545_regs[BQ27XXX_REG_MAX] = {
0411 [BQ27XXX_REG_CTRL] = 0x00,
0412 [BQ27XXX_REG_TEMP] = 0x06,
0413 [BQ27XXX_REG_INT_TEMP] = 0x28,
0414 [BQ27XXX_REG_VOLT] = 0x08,
0415 [BQ27XXX_REG_AI] = 0x14,
0416 [BQ27XXX_REG_FLAGS] = 0x0a,
0417 [BQ27XXX_REG_TTE] = 0x16,
0418 [BQ27XXX_REG_TTF] = INVALID_REG_ADDR,
0419 [BQ27XXX_REG_TTES] = INVALID_REG_ADDR,
0420 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0421 [BQ27XXX_REG_NAC] = 0x0c,
0422 [BQ27XXX_REG_RC] = 0x10,
0423 [BQ27XXX_REG_FCC] = 0x12,
0424 [BQ27XXX_REG_CYCT] = 0x2a,
0425 [BQ27XXX_REG_AE] = INVALID_REG_ADDR,
0426 [BQ27XXX_REG_SOC] = 0x2c,
0427 [BQ27XXX_REG_DCAP] = INVALID_REG_ADDR,
0428 [BQ27XXX_REG_AP] = 0x24,
0429 BQ27XXX_DM_REG_ROWS,
0430 },
0431 bq27421_regs[BQ27XXX_REG_MAX] = {
0432 [BQ27XXX_REG_CTRL] = 0x00,
0433 [BQ27XXX_REG_TEMP] = 0x02,
0434 [BQ27XXX_REG_INT_TEMP] = 0x1e,
0435 [BQ27XXX_REG_VOLT] = 0x04,
0436 [BQ27XXX_REG_AI] = 0x10,
0437 [BQ27XXX_REG_FLAGS] = 0x06,
0438 [BQ27XXX_REG_TTE] = INVALID_REG_ADDR,
0439 [BQ27XXX_REG_TTF] = INVALID_REG_ADDR,
0440 [BQ27XXX_REG_TTES] = INVALID_REG_ADDR,
0441 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0442 [BQ27XXX_REG_NAC] = 0x08,
0443 [BQ27XXX_REG_RC] = 0x0c,
0444 [BQ27XXX_REG_FCC] = 0x0e,
0445 [BQ27XXX_REG_CYCT] = INVALID_REG_ADDR,
0446 [BQ27XXX_REG_AE] = INVALID_REG_ADDR,
0447 [BQ27XXX_REG_SOC] = 0x1c,
0448 [BQ27XXX_REG_DCAP] = 0x3c,
0449 [BQ27XXX_REG_AP] = 0x18,
0450 BQ27XXX_DM_REG_ROWS,
0451 },
0452 #define bq27411_regs bq27421_regs
0453 #define bq27425_regs bq27421_regs
0454 #define bq27426_regs bq27421_regs
0455 #define bq27441_regs bq27421_regs
0456 #define bq27621_regs bq27421_regs
0457 bq27z561_regs[BQ27XXX_REG_MAX] = {
0458 [BQ27XXX_REG_CTRL] = 0x00,
0459 [BQ27XXX_REG_TEMP] = 0x06,
0460 [BQ27XXX_REG_INT_TEMP] = INVALID_REG_ADDR,
0461 [BQ27XXX_REG_VOLT] = 0x08,
0462 [BQ27XXX_REG_AI] = 0x14,
0463 [BQ27XXX_REG_FLAGS] = 0x0a,
0464 [BQ27XXX_REG_TTE] = 0x16,
0465 [BQ27XXX_REG_TTF] = 0x18,
0466 [BQ27XXX_REG_TTES] = INVALID_REG_ADDR,
0467 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0468 [BQ27XXX_REG_NAC] = INVALID_REG_ADDR,
0469 [BQ27XXX_REG_RC] = 0x10,
0470 [BQ27XXX_REG_FCC] = 0x12,
0471 [BQ27XXX_REG_CYCT] = 0x2a,
0472 [BQ27XXX_REG_AE] = 0x22,
0473 [BQ27XXX_REG_SOC] = 0x2c,
0474 [BQ27XXX_REG_DCAP] = 0x3c,
0475 [BQ27XXX_REG_AP] = 0x22,
0476 BQ27XXX_DM_REG_ROWS,
0477 },
0478 bq28z610_regs[BQ27XXX_REG_MAX] = {
0479 [BQ27XXX_REG_CTRL] = 0x00,
0480 [BQ27XXX_REG_TEMP] = 0x06,
0481 [BQ27XXX_REG_INT_TEMP] = INVALID_REG_ADDR,
0482 [BQ27XXX_REG_VOLT] = 0x08,
0483 [BQ27XXX_REG_AI] = 0x14,
0484 [BQ27XXX_REG_FLAGS] = 0x0a,
0485 [BQ27XXX_REG_TTE] = 0x16,
0486 [BQ27XXX_REG_TTF] = 0x18,
0487 [BQ27XXX_REG_TTES] = INVALID_REG_ADDR,
0488 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0489 [BQ27XXX_REG_NAC] = INVALID_REG_ADDR,
0490 [BQ27XXX_REG_RC] = 0x10,
0491 [BQ27XXX_REG_FCC] = 0x12,
0492 [BQ27XXX_REG_CYCT] = 0x2a,
0493 [BQ27XXX_REG_AE] = 0x22,
0494 [BQ27XXX_REG_SOC] = 0x2c,
0495 [BQ27XXX_REG_DCAP] = 0x3c,
0496 [BQ27XXX_REG_AP] = 0x22,
0497 BQ27XXX_DM_REG_ROWS,
0498 },
0499 bq34z100_regs[BQ27XXX_REG_MAX] = {
0500 [BQ27XXX_REG_CTRL] = 0x00,
0501 [BQ27XXX_REG_TEMP] = 0x0c,
0502 [BQ27XXX_REG_INT_TEMP] = 0x2a,
0503 [BQ27XXX_REG_VOLT] = 0x08,
0504 [BQ27XXX_REG_AI] = 0x0a,
0505 [BQ27XXX_REG_FLAGS] = 0x0e,
0506 [BQ27XXX_REG_TTE] = 0x18,
0507 [BQ27XXX_REG_TTF] = 0x1a,
0508 [BQ27XXX_REG_TTES] = 0x1e,
0509 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0510 [BQ27XXX_REG_NAC] = INVALID_REG_ADDR,
0511 [BQ27XXX_REG_RC] = 0x04,
0512 [BQ27XXX_REG_FCC] = 0x06,
0513 [BQ27XXX_REG_CYCT] = 0x2c,
0514 [BQ27XXX_REG_AE] = 0x24,
0515 [BQ27XXX_REG_SOC] = 0x02,
0516 [BQ27XXX_REG_DCAP] = 0x3c,
0517 [BQ27XXX_REG_AP] = 0x22,
0518 BQ27XXX_DM_REG_ROWS,
0519 },
0520 bq78z100_regs[BQ27XXX_REG_MAX] = {
0521 [BQ27XXX_REG_CTRL] = 0x00,
0522 [BQ27XXX_REG_TEMP] = 0x06,
0523 [BQ27XXX_REG_INT_TEMP] = 0x28,
0524 [BQ27XXX_REG_VOLT] = 0x08,
0525 [BQ27XXX_REG_AI] = 0x14,
0526 [BQ27XXX_REG_FLAGS] = 0x0a,
0527 [BQ27XXX_REG_TTE] = 0x16,
0528 [BQ27XXX_REG_TTF] = 0x18,
0529 [BQ27XXX_REG_TTES] = 0x1c,
0530 [BQ27XXX_REG_TTECP] = INVALID_REG_ADDR,
0531 [BQ27XXX_REG_NAC] = INVALID_REG_ADDR,
0532 [BQ27XXX_REG_RC] = 0x10,
0533 [BQ27XXX_REG_FCC] = 0x12,
0534 [BQ27XXX_REG_CYCT] = 0x2a,
0535 [BQ27XXX_REG_AE] = INVALID_REG_ADDR,
0536 [BQ27XXX_REG_SOC] = 0x2c,
0537 [BQ27XXX_REG_DCAP] = 0x3c,
0538 [BQ27XXX_REG_AP] = 0x22,
0539 BQ27XXX_DM_REG_ROWS,
0540 };
0541
0542 static enum power_supply_property bq27000_props[] = {
0543 POWER_SUPPLY_PROP_STATUS,
0544 POWER_SUPPLY_PROP_PRESENT,
0545 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0546 POWER_SUPPLY_PROP_CURRENT_NOW,
0547 POWER_SUPPLY_PROP_CAPACITY,
0548 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0549 POWER_SUPPLY_PROP_TEMP,
0550 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0551 POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
0552 POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
0553 POWER_SUPPLY_PROP_TECHNOLOGY,
0554 POWER_SUPPLY_PROP_CHARGE_FULL,
0555 POWER_SUPPLY_PROP_CHARGE_NOW,
0556 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0557 POWER_SUPPLY_PROP_CYCLE_COUNT,
0558 POWER_SUPPLY_PROP_ENERGY_NOW,
0559 POWER_SUPPLY_PROP_POWER_AVG,
0560 POWER_SUPPLY_PROP_HEALTH,
0561 POWER_SUPPLY_PROP_MANUFACTURER,
0562 };
0563
0564 static enum power_supply_property bq27010_props[] = {
0565 POWER_SUPPLY_PROP_STATUS,
0566 POWER_SUPPLY_PROP_PRESENT,
0567 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0568 POWER_SUPPLY_PROP_CURRENT_NOW,
0569 POWER_SUPPLY_PROP_CAPACITY,
0570 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0571 POWER_SUPPLY_PROP_TEMP,
0572 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0573 POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
0574 POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
0575 POWER_SUPPLY_PROP_TECHNOLOGY,
0576 POWER_SUPPLY_PROP_CHARGE_FULL,
0577 POWER_SUPPLY_PROP_CHARGE_NOW,
0578 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0579 POWER_SUPPLY_PROP_CYCLE_COUNT,
0580 POWER_SUPPLY_PROP_HEALTH,
0581 POWER_SUPPLY_PROP_MANUFACTURER,
0582 };
0583
0584 #define bq2750x_props bq27510g3_props
0585 #define bq2751x_props bq27510g3_props
0586 #define bq2752x_props bq27510g3_props
0587
0588 static enum power_supply_property bq27500_props[] = {
0589 POWER_SUPPLY_PROP_STATUS,
0590 POWER_SUPPLY_PROP_PRESENT,
0591 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0592 POWER_SUPPLY_PROP_CURRENT_NOW,
0593 POWER_SUPPLY_PROP_CAPACITY,
0594 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0595 POWER_SUPPLY_PROP_TEMP,
0596 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0597 POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
0598 POWER_SUPPLY_PROP_TECHNOLOGY,
0599 POWER_SUPPLY_PROP_CHARGE_FULL,
0600 POWER_SUPPLY_PROP_CHARGE_NOW,
0601 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0602 POWER_SUPPLY_PROP_CYCLE_COUNT,
0603 POWER_SUPPLY_PROP_ENERGY_NOW,
0604 POWER_SUPPLY_PROP_POWER_AVG,
0605 POWER_SUPPLY_PROP_HEALTH,
0606 POWER_SUPPLY_PROP_MANUFACTURER,
0607 };
0608 #define bq27510g1_props bq27500_props
0609 #define bq27510g2_props bq27500_props
0610
0611 static enum power_supply_property bq27510g3_props[] = {
0612 POWER_SUPPLY_PROP_STATUS,
0613 POWER_SUPPLY_PROP_PRESENT,
0614 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0615 POWER_SUPPLY_PROP_CURRENT_NOW,
0616 POWER_SUPPLY_PROP_CAPACITY,
0617 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0618 POWER_SUPPLY_PROP_TEMP,
0619 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0620 POWER_SUPPLY_PROP_TECHNOLOGY,
0621 POWER_SUPPLY_PROP_CHARGE_FULL,
0622 POWER_SUPPLY_PROP_CHARGE_NOW,
0623 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0624 POWER_SUPPLY_PROP_CYCLE_COUNT,
0625 POWER_SUPPLY_PROP_HEALTH,
0626 POWER_SUPPLY_PROP_MANUFACTURER,
0627 };
0628
0629 static enum power_supply_property bq27520g1_props[] = {
0630 POWER_SUPPLY_PROP_STATUS,
0631 POWER_SUPPLY_PROP_PRESENT,
0632 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0633 POWER_SUPPLY_PROP_CURRENT_NOW,
0634 POWER_SUPPLY_PROP_CAPACITY,
0635 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0636 POWER_SUPPLY_PROP_TEMP,
0637 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0638 POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
0639 POWER_SUPPLY_PROP_TECHNOLOGY,
0640 POWER_SUPPLY_PROP_CHARGE_FULL,
0641 POWER_SUPPLY_PROP_CHARGE_NOW,
0642 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0643 POWER_SUPPLY_PROP_ENERGY_NOW,
0644 POWER_SUPPLY_PROP_POWER_AVG,
0645 POWER_SUPPLY_PROP_HEALTH,
0646 POWER_SUPPLY_PROP_MANUFACTURER,
0647 };
0648
0649 #define bq27520g2_props bq27500_props
0650
0651 static enum power_supply_property bq27520g3_props[] = {
0652 POWER_SUPPLY_PROP_STATUS,
0653 POWER_SUPPLY_PROP_PRESENT,
0654 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0655 POWER_SUPPLY_PROP_CURRENT_NOW,
0656 POWER_SUPPLY_PROP_CAPACITY,
0657 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0658 POWER_SUPPLY_PROP_TEMP,
0659 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0660 POWER_SUPPLY_PROP_TECHNOLOGY,
0661 POWER_SUPPLY_PROP_CHARGE_FULL,
0662 POWER_SUPPLY_PROP_CHARGE_NOW,
0663 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0664 POWER_SUPPLY_PROP_CYCLE_COUNT,
0665 POWER_SUPPLY_PROP_ENERGY_NOW,
0666 POWER_SUPPLY_PROP_POWER_AVG,
0667 POWER_SUPPLY_PROP_HEALTH,
0668 POWER_SUPPLY_PROP_MANUFACTURER,
0669 };
0670
0671 static enum power_supply_property bq27520g4_props[] = {
0672 POWER_SUPPLY_PROP_STATUS,
0673 POWER_SUPPLY_PROP_PRESENT,
0674 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0675 POWER_SUPPLY_PROP_CURRENT_NOW,
0676 POWER_SUPPLY_PROP_CAPACITY,
0677 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0678 POWER_SUPPLY_PROP_TEMP,
0679 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0680 POWER_SUPPLY_PROP_TECHNOLOGY,
0681 POWER_SUPPLY_PROP_CHARGE_FULL,
0682 POWER_SUPPLY_PROP_CHARGE_NOW,
0683 POWER_SUPPLY_PROP_CYCLE_COUNT,
0684 POWER_SUPPLY_PROP_HEALTH,
0685 POWER_SUPPLY_PROP_MANUFACTURER,
0686 };
0687
0688 static enum power_supply_property bq27521_props[] = {
0689 POWER_SUPPLY_PROP_STATUS,
0690 POWER_SUPPLY_PROP_PRESENT,
0691 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0692 POWER_SUPPLY_PROP_CURRENT_NOW,
0693 POWER_SUPPLY_PROP_TEMP,
0694 POWER_SUPPLY_PROP_TECHNOLOGY,
0695 };
0696
0697 static enum power_supply_property bq27530_props[] = {
0698 POWER_SUPPLY_PROP_STATUS,
0699 POWER_SUPPLY_PROP_PRESENT,
0700 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0701 POWER_SUPPLY_PROP_CURRENT_NOW,
0702 POWER_SUPPLY_PROP_CAPACITY,
0703 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0704 POWER_SUPPLY_PROP_TEMP,
0705 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0706 POWER_SUPPLY_PROP_TECHNOLOGY,
0707 POWER_SUPPLY_PROP_CHARGE_FULL,
0708 POWER_SUPPLY_PROP_CHARGE_NOW,
0709 POWER_SUPPLY_PROP_POWER_AVG,
0710 POWER_SUPPLY_PROP_HEALTH,
0711 POWER_SUPPLY_PROP_CYCLE_COUNT,
0712 POWER_SUPPLY_PROP_MANUFACTURER,
0713 };
0714 #define bq27531_props bq27530_props
0715
0716 static enum power_supply_property bq27541_props[] = {
0717 POWER_SUPPLY_PROP_STATUS,
0718 POWER_SUPPLY_PROP_PRESENT,
0719 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0720 POWER_SUPPLY_PROP_CURRENT_NOW,
0721 POWER_SUPPLY_PROP_CAPACITY,
0722 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0723 POWER_SUPPLY_PROP_TEMP,
0724 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0725 POWER_SUPPLY_PROP_TECHNOLOGY,
0726 POWER_SUPPLY_PROP_CHARGE_FULL,
0727 POWER_SUPPLY_PROP_CHARGE_NOW,
0728 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0729 POWER_SUPPLY_PROP_CYCLE_COUNT,
0730 POWER_SUPPLY_PROP_POWER_AVG,
0731 POWER_SUPPLY_PROP_HEALTH,
0732 POWER_SUPPLY_PROP_MANUFACTURER,
0733 };
0734 #define bq27542_props bq27541_props
0735 #define bq27546_props bq27541_props
0736 #define bq27742_props bq27541_props
0737
0738 static enum power_supply_property bq27545_props[] = {
0739 POWER_SUPPLY_PROP_STATUS,
0740 POWER_SUPPLY_PROP_PRESENT,
0741 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0742 POWER_SUPPLY_PROP_CURRENT_NOW,
0743 POWER_SUPPLY_PROP_CAPACITY,
0744 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0745 POWER_SUPPLY_PROP_TEMP,
0746 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0747 POWER_SUPPLY_PROP_TECHNOLOGY,
0748 POWER_SUPPLY_PROP_CHARGE_FULL,
0749 POWER_SUPPLY_PROP_CHARGE_NOW,
0750 POWER_SUPPLY_PROP_HEALTH,
0751 POWER_SUPPLY_PROP_CYCLE_COUNT,
0752 POWER_SUPPLY_PROP_POWER_AVG,
0753 POWER_SUPPLY_PROP_MANUFACTURER,
0754 };
0755
0756 static enum power_supply_property bq27421_props[] = {
0757 POWER_SUPPLY_PROP_STATUS,
0758 POWER_SUPPLY_PROP_PRESENT,
0759 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0760 POWER_SUPPLY_PROP_CURRENT_NOW,
0761 POWER_SUPPLY_PROP_CAPACITY,
0762 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0763 POWER_SUPPLY_PROP_TEMP,
0764 POWER_SUPPLY_PROP_TECHNOLOGY,
0765 POWER_SUPPLY_PROP_CHARGE_FULL,
0766 POWER_SUPPLY_PROP_CHARGE_NOW,
0767 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0768 POWER_SUPPLY_PROP_MANUFACTURER,
0769 };
0770 #define bq27411_props bq27421_props
0771 #define bq27425_props bq27421_props
0772 #define bq27426_props bq27421_props
0773 #define bq27441_props bq27421_props
0774 #define bq27621_props bq27421_props
0775
0776 static enum power_supply_property bq27z561_props[] = {
0777 POWER_SUPPLY_PROP_STATUS,
0778 POWER_SUPPLY_PROP_PRESENT,
0779 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0780 POWER_SUPPLY_PROP_CURRENT_NOW,
0781 POWER_SUPPLY_PROP_CAPACITY,
0782 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0783 POWER_SUPPLY_PROP_TEMP,
0784 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0785 POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
0786 POWER_SUPPLY_PROP_TECHNOLOGY,
0787 POWER_SUPPLY_PROP_CHARGE_FULL,
0788 POWER_SUPPLY_PROP_CHARGE_NOW,
0789 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0790 POWER_SUPPLY_PROP_CYCLE_COUNT,
0791 POWER_SUPPLY_PROP_POWER_AVG,
0792 POWER_SUPPLY_PROP_HEALTH,
0793 POWER_SUPPLY_PROP_MANUFACTURER,
0794 };
0795
0796 static enum power_supply_property bq28z610_props[] = {
0797 POWER_SUPPLY_PROP_STATUS,
0798 POWER_SUPPLY_PROP_PRESENT,
0799 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0800 POWER_SUPPLY_PROP_CURRENT_NOW,
0801 POWER_SUPPLY_PROP_CAPACITY,
0802 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0803 POWER_SUPPLY_PROP_TEMP,
0804 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0805 POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
0806 POWER_SUPPLY_PROP_TECHNOLOGY,
0807 POWER_SUPPLY_PROP_CHARGE_FULL,
0808 POWER_SUPPLY_PROP_CHARGE_NOW,
0809 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0810 POWER_SUPPLY_PROP_CYCLE_COUNT,
0811 POWER_SUPPLY_PROP_POWER_AVG,
0812 POWER_SUPPLY_PROP_HEALTH,
0813 POWER_SUPPLY_PROP_MANUFACTURER,
0814 };
0815
0816 static enum power_supply_property bq34z100_props[] = {
0817 POWER_SUPPLY_PROP_STATUS,
0818 POWER_SUPPLY_PROP_PRESENT,
0819 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0820 POWER_SUPPLY_PROP_CURRENT_NOW,
0821 POWER_SUPPLY_PROP_CAPACITY,
0822 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0823 POWER_SUPPLY_PROP_TEMP,
0824 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0825 POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
0826 POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
0827 POWER_SUPPLY_PROP_TECHNOLOGY,
0828 POWER_SUPPLY_PROP_CHARGE_FULL,
0829 POWER_SUPPLY_PROP_CHARGE_NOW,
0830 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0831 POWER_SUPPLY_PROP_CYCLE_COUNT,
0832 POWER_SUPPLY_PROP_ENERGY_NOW,
0833 POWER_SUPPLY_PROP_POWER_AVG,
0834 POWER_SUPPLY_PROP_HEALTH,
0835 POWER_SUPPLY_PROP_MANUFACTURER,
0836 };
0837
0838 static enum power_supply_property bq78z100_props[] = {
0839 POWER_SUPPLY_PROP_STATUS,
0840 POWER_SUPPLY_PROP_PRESENT,
0841 POWER_SUPPLY_PROP_VOLTAGE_NOW,
0842 POWER_SUPPLY_PROP_CURRENT_NOW,
0843 POWER_SUPPLY_PROP_CAPACITY,
0844 POWER_SUPPLY_PROP_CAPACITY_LEVEL,
0845 POWER_SUPPLY_PROP_TEMP,
0846 POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
0847 POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
0848 POWER_SUPPLY_PROP_TECHNOLOGY,
0849 POWER_SUPPLY_PROP_CHARGE_FULL,
0850 POWER_SUPPLY_PROP_CHARGE_NOW,
0851 POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
0852 POWER_SUPPLY_PROP_CYCLE_COUNT,
0853 POWER_SUPPLY_PROP_POWER_AVG,
0854 POWER_SUPPLY_PROP_HEALTH,
0855 POWER_SUPPLY_PROP_MANUFACTURER,
0856 };
0857
0858 struct bq27xxx_dm_reg {
0859 u8 subclass_id;
0860 u8 offset;
0861 u8 bytes;
0862 u16 min, max;
0863 };
0864
0865 enum bq27xxx_dm_reg_id {
0866 BQ27XXX_DM_DESIGN_CAPACITY = 0,
0867 BQ27XXX_DM_DESIGN_ENERGY,
0868 BQ27XXX_DM_TERMINATE_VOLTAGE,
0869 };
0870
0871 #define bq27000_dm_regs 0
0872 #define bq27010_dm_regs 0
0873 #define bq2750x_dm_regs 0
0874 #define bq2751x_dm_regs 0
0875 #define bq2752x_dm_regs 0
0876
0877 #if 0
0878 static struct bq27xxx_dm_reg bq27500_dm_regs[] = {
0879 [BQ27XXX_DM_DESIGN_CAPACITY] = { 48, 10, 2, 0, 65535 },
0880 [BQ27XXX_DM_DESIGN_ENERGY] = { },
0881 [BQ27XXX_DM_TERMINATE_VOLTAGE] = { 80, 48, 2, 1000, 32767 },
0882 };
0883 #else
0884 #define bq27500_dm_regs 0
0885 #endif
0886
0887
0888 #define bq27510g1_dm_regs 0
0889 #define bq27510g2_dm_regs 0
0890 #define bq27510g3_dm_regs 0
0891 #define bq27520g1_dm_regs 0
0892 #define bq27520g2_dm_regs 0
0893 #define bq27520g3_dm_regs 0
0894 #define bq27520g4_dm_regs 0
0895 #define bq27521_dm_regs 0
0896 #define bq27530_dm_regs 0
0897 #define bq27531_dm_regs 0
0898 #define bq27541_dm_regs 0
0899 #define bq27542_dm_regs 0
0900 #define bq27546_dm_regs 0
0901 #define bq27742_dm_regs 0
0902
0903 #if 0
0904 static struct bq27xxx_dm_reg bq27545_dm_regs[] = {
0905 [BQ27XXX_DM_DESIGN_CAPACITY] = { 48, 23, 2, 0, 32767 },
0906 [BQ27XXX_DM_DESIGN_ENERGY] = { 48, 25, 2, 0, 32767 },
0907 [BQ27XXX_DM_TERMINATE_VOLTAGE] = { 80, 67, 2, 2800, 3700 },
0908 };
0909 #else
0910 #define bq27545_dm_regs 0
0911 #endif
0912
0913 static struct bq27xxx_dm_reg bq27411_dm_regs[] = {
0914 [BQ27XXX_DM_DESIGN_CAPACITY] = { 82, 10, 2, 0, 32767 },
0915 [BQ27XXX_DM_DESIGN_ENERGY] = { 82, 12, 2, 0, 32767 },
0916 [BQ27XXX_DM_TERMINATE_VOLTAGE] = { 82, 16, 2, 2800, 3700 },
0917 };
0918
0919 static struct bq27xxx_dm_reg bq27421_dm_regs[] = {
0920 [BQ27XXX_DM_DESIGN_CAPACITY] = { 82, 10, 2, 0, 8000 },
0921 [BQ27XXX_DM_DESIGN_ENERGY] = { 82, 12, 2, 0, 32767 },
0922 [BQ27XXX_DM_TERMINATE_VOLTAGE] = { 82, 16, 2, 2500, 3700 },
0923 };
0924
0925 static struct bq27xxx_dm_reg bq27425_dm_regs[] = {
0926 [BQ27XXX_DM_DESIGN_CAPACITY] = { 82, 12, 2, 0, 32767 },
0927 [BQ27XXX_DM_DESIGN_ENERGY] = { 82, 14, 2, 0, 32767 },
0928 [BQ27XXX_DM_TERMINATE_VOLTAGE] = { 82, 18, 2, 2800, 3700 },
0929 };
0930
0931 static struct bq27xxx_dm_reg bq27426_dm_regs[] = {
0932 [BQ27XXX_DM_DESIGN_CAPACITY] = { 82, 6, 2, 0, 8000 },
0933 [BQ27XXX_DM_DESIGN_ENERGY] = { 82, 8, 2, 0, 32767 },
0934 [BQ27XXX_DM_TERMINATE_VOLTAGE] = { 82, 10, 2, 2500, 3700 },
0935 };
0936
0937 #if 0
0938 #define bq27441_dm_regs bq27421_dm_regs
0939 #else
0940 #define bq27441_dm_regs 0
0941 #endif
0942
0943 #if 0
0944 static struct bq27xxx_dm_reg bq27621_dm_regs[] = {
0945 [BQ27XXX_DM_DESIGN_CAPACITY] = { 82, 3, 2, 0, 8000 },
0946 [BQ27XXX_DM_DESIGN_ENERGY] = { 82, 5, 2, 0, 32767 },
0947 [BQ27XXX_DM_TERMINATE_VOLTAGE] = { 82, 9, 2, 2500, 3700 },
0948 };
0949 #else
0950 #define bq27621_dm_regs 0
0951 #endif
0952
0953 #define bq27z561_dm_regs 0
0954 #define bq28z610_dm_regs 0
0955 #define bq34z100_dm_regs 0
0956 #define bq78z100_dm_regs 0
0957
0958 #define BQ27XXX_O_ZERO BIT(0)
0959 #define BQ27XXX_O_OTDC BIT(1)
0960 #define BQ27XXX_O_UTOT BIT(2)
0961 #define BQ27XXX_O_CFGUP BIT(3)
0962 #define BQ27XXX_O_RAM BIT(4)
0963 #define BQ27Z561_O_BITS BIT(5)
0964 #define BQ27XXX_O_SOC_SI BIT(6)
0965 #define BQ27XXX_O_HAS_CI BIT(7)
0966 #define BQ27XXX_O_MUL_CHEM BIT(8)
0967
0968 #define BQ27XXX_DATA(ref, key, opt) { \
0969 .opts = (opt), \
0970 .unseal_key = key, \
0971 .regs = ref##_regs, \
0972 .dm_regs = ref##_dm_regs, \
0973 .props = ref##_props, \
0974 .props_size = ARRAY_SIZE(ref##_props) }
0975
0976 static struct {
0977 u32 opts;
0978 u32 unseal_key;
0979 u8 *regs;
0980 struct bq27xxx_dm_reg *dm_regs;
0981 enum power_supply_property *props;
0982 size_t props_size;
0983 } bq27xxx_chip_data[] = {
0984 [BQ27000] = BQ27XXX_DATA(bq27000, 0 , BQ27XXX_O_ZERO | BQ27XXX_O_SOC_SI | BQ27XXX_O_HAS_CI),
0985 [BQ27010] = BQ27XXX_DATA(bq27010, 0 , BQ27XXX_O_ZERO | BQ27XXX_O_SOC_SI | BQ27XXX_O_HAS_CI),
0986 [BQ2750X] = BQ27XXX_DATA(bq2750x, 0 , BQ27XXX_O_OTDC),
0987 [BQ2751X] = BQ27XXX_DATA(bq2751x, 0 , BQ27XXX_O_OTDC),
0988 [BQ2752X] = BQ27XXX_DATA(bq2752x, 0 , BQ27XXX_O_OTDC),
0989 [BQ27500] = BQ27XXX_DATA(bq27500, 0x04143672, BQ27XXX_O_OTDC),
0990 [BQ27510G1] = BQ27XXX_DATA(bq27510g1, 0 , BQ27XXX_O_OTDC),
0991 [BQ27510G2] = BQ27XXX_DATA(bq27510g2, 0 , BQ27XXX_O_OTDC),
0992 [BQ27510G3] = BQ27XXX_DATA(bq27510g3, 0 , BQ27XXX_O_OTDC),
0993 [BQ27520G1] = BQ27XXX_DATA(bq27520g1, 0 , BQ27XXX_O_OTDC),
0994 [BQ27520G2] = BQ27XXX_DATA(bq27520g2, 0 , BQ27XXX_O_OTDC),
0995 [BQ27520G3] = BQ27XXX_DATA(bq27520g3, 0 , BQ27XXX_O_OTDC),
0996 [BQ27520G4] = BQ27XXX_DATA(bq27520g4, 0 , BQ27XXX_O_OTDC),
0997 [BQ27521] = BQ27XXX_DATA(bq27521, 0 , 0),
0998 [BQ27530] = BQ27XXX_DATA(bq27530, 0 , BQ27XXX_O_UTOT),
0999 [BQ27531] = BQ27XXX_DATA(bq27531, 0 , BQ27XXX_O_UTOT),
1000 [BQ27541] = BQ27XXX_DATA(bq27541, 0 , BQ27XXX_O_OTDC),
1001 [BQ27542] = BQ27XXX_DATA(bq27542, 0 , BQ27XXX_O_OTDC),
1002 [BQ27546] = BQ27XXX_DATA(bq27546, 0 , BQ27XXX_O_OTDC),
1003 [BQ27742] = BQ27XXX_DATA(bq27742, 0 , BQ27XXX_O_OTDC),
1004 [BQ27545] = BQ27XXX_DATA(bq27545, 0x04143672, BQ27XXX_O_OTDC),
1005 [BQ27411] = BQ27XXX_DATA(bq27411, 0x80008000, BQ27XXX_O_UTOT | BQ27XXX_O_CFGUP | BQ27XXX_O_RAM),
1006 [BQ27421] = BQ27XXX_DATA(bq27421, 0x80008000, BQ27XXX_O_UTOT | BQ27XXX_O_CFGUP | BQ27XXX_O_RAM),
1007 [BQ27425] = BQ27XXX_DATA(bq27425, 0x04143672, BQ27XXX_O_UTOT | BQ27XXX_O_CFGUP),
1008 [BQ27426] = BQ27XXX_DATA(bq27426, 0x80008000, BQ27XXX_O_UTOT | BQ27XXX_O_CFGUP | BQ27XXX_O_RAM),
1009 [BQ27441] = BQ27XXX_DATA(bq27441, 0x80008000, BQ27XXX_O_UTOT | BQ27XXX_O_CFGUP | BQ27XXX_O_RAM),
1010 [BQ27621] = BQ27XXX_DATA(bq27621, 0x80008000, BQ27XXX_O_UTOT | BQ27XXX_O_CFGUP | BQ27XXX_O_RAM),
1011 [BQ27Z561] = BQ27XXX_DATA(bq27z561, 0 , BQ27Z561_O_BITS),
1012 [BQ28Z610] = BQ27XXX_DATA(bq28z610, 0 , BQ27Z561_O_BITS),
1013 [BQ34Z100] = BQ27XXX_DATA(bq34z100, 0 , BQ27XXX_O_OTDC | BQ27XXX_O_SOC_SI | \
1014 BQ27XXX_O_HAS_CI | BQ27XXX_O_MUL_CHEM),
1015 [BQ78Z100] = BQ27XXX_DATA(bq78z100, 0 , BQ27Z561_O_BITS),
1016 };
1017
1018 static DEFINE_MUTEX(bq27xxx_list_lock);
1019 static LIST_HEAD(bq27xxx_battery_devices);
1020
1021 #define BQ27XXX_MSLEEP(i) usleep_range((i)*1000, (i)*1000+500)
1022
1023 #define BQ27XXX_DM_SZ 32
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035 struct bq27xxx_dm_buf {
1036 u8 class;
1037 u8 block;
1038 u8 data[BQ27XXX_DM_SZ];
1039 bool has_data, dirty;
1040 };
1041
1042 #define BQ27XXX_DM_BUF(di, i) { \
1043 .class = (di)->dm_regs[i].subclass_id, \
1044 .block = (di)->dm_regs[i].offset / BQ27XXX_DM_SZ, \
1045 }
1046
1047 static inline u16 *bq27xxx_dm_reg_ptr(struct bq27xxx_dm_buf *buf,
1048 struct bq27xxx_dm_reg *reg)
1049 {
1050 if (buf->class == reg->subclass_id &&
1051 buf->block == reg->offset / BQ27XXX_DM_SZ)
1052 return (u16 *) (buf->data + reg->offset % BQ27XXX_DM_SZ);
1053
1054 return NULL;
1055 }
1056
1057 static const char * const bq27xxx_dm_reg_name[] = {
1058 [BQ27XXX_DM_DESIGN_CAPACITY] = "design-capacity",
1059 [BQ27XXX_DM_DESIGN_ENERGY] = "design-energy",
1060 [BQ27XXX_DM_TERMINATE_VOLTAGE] = "terminate-voltage",
1061 };
1062
1063
1064 static bool bq27xxx_dt_to_nvm = true;
1065 module_param_named(dt_monitored_battery_updates_nvm, bq27xxx_dt_to_nvm, bool, 0444);
1066 MODULE_PARM_DESC(dt_monitored_battery_updates_nvm,
1067 "Devicetree monitored-battery config updates data memory on NVM/flash chips.\n"
1068 "Users must set this =0 when installing a different type of battery!\n"
1069 "Default is =1."
1070 #ifndef CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM
1071 "\nSetting this affects future kernel updates, not the current configuration."
1072 #endif
1073 );
1074
1075 static int poll_interval_param_set(const char *val, const struct kernel_param *kp)
1076 {
1077 struct bq27xxx_device_info *di;
1078 unsigned int prev_val = *(unsigned int *) kp->arg;
1079 int ret;
1080
1081 ret = param_set_uint(val, kp);
1082 if (ret < 0 || prev_val == *(unsigned int *) kp->arg)
1083 return ret;
1084
1085 mutex_lock(&bq27xxx_list_lock);
1086 list_for_each_entry(di, &bq27xxx_battery_devices, list) {
1087 cancel_delayed_work_sync(&di->work);
1088 schedule_delayed_work(&di->work, 0);
1089 }
1090 mutex_unlock(&bq27xxx_list_lock);
1091
1092 return ret;
1093 }
1094
1095 static const struct kernel_param_ops param_ops_poll_interval = {
1096 .get = param_get_uint,
1097 .set = poll_interval_param_set,
1098 };
1099
1100 static unsigned int poll_interval = 360;
1101 module_param_cb(poll_interval, ¶m_ops_poll_interval, &poll_interval, 0644);
1102 MODULE_PARM_DESC(poll_interval,
1103 "battery poll interval in seconds - 0 disables polling");
1104
1105
1106
1107
1108
1109 static inline int bq27xxx_read(struct bq27xxx_device_info *di, int reg_index,
1110 bool single)
1111 {
1112 int ret;
1113
1114 if (!di || di->regs[reg_index] == INVALID_REG_ADDR)
1115 return -EINVAL;
1116
1117 ret = di->bus.read(di, di->regs[reg_index], single);
1118 if (ret < 0)
1119 dev_dbg(di->dev, "failed to read register 0x%02x (index %d)\n",
1120 di->regs[reg_index], reg_index);
1121
1122 return ret;
1123 }
1124
1125 static inline int bq27xxx_write(struct bq27xxx_device_info *di, int reg_index,
1126 u16 value, bool single)
1127 {
1128 int ret;
1129
1130 if (!di || di->regs[reg_index] == INVALID_REG_ADDR)
1131 return -EINVAL;
1132
1133 if (!di->bus.write)
1134 return -EPERM;
1135
1136 ret = di->bus.write(di, di->regs[reg_index], value, single);
1137 if (ret < 0)
1138 dev_dbg(di->dev, "failed to write register 0x%02x (index %d)\n",
1139 di->regs[reg_index], reg_index);
1140
1141 return ret;
1142 }
1143
1144 static inline int bq27xxx_read_block(struct bq27xxx_device_info *di, int reg_index,
1145 u8 *data, int len)
1146 {
1147 int ret;
1148
1149 if (!di || di->regs[reg_index] == INVALID_REG_ADDR)
1150 return -EINVAL;
1151
1152 if (!di->bus.read_bulk)
1153 return -EPERM;
1154
1155 ret = di->bus.read_bulk(di, di->regs[reg_index], data, len);
1156 if (ret < 0)
1157 dev_dbg(di->dev, "failed to read_bulk register 0x%02x (index %d)\n",
1158 di->regs[reg_index], reg_index);
1159
1160 return ret;
1161 }
1162
1163 static inline int bq27xxx_write_block(struct bq27xxx_device_info *di, int reg_index,
1164 u8 *data, int len)
1165 {
1166 int ret;
1167
1168 if (!di || di->regs[reg_index] == INVALID_REG_ADDR)
1169 return -EINVAL;
1170
1171 if (!di->bus.write_bulk)
1172 return -EPERM;
1173
1174 ret = di->bus.write_bulk(di, di->regs[reg_index], data, len);
1175 if (ret < 0)
1176 dev_dbg(di->dev, "failed to write_bulk register 0x%02x (index %d)\n",
1177 di->regs[reg_index], reg_index);
1178
1179 return ret;
1180 }
1181
1182 static int bq27xxx_battery_seal(struct bq27xxx_device_info *di)
1183 {
1184 int ret;
1185
1186 ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, BQ27XXX_SEALED, false);
1187 if (ret < 0) {
1188 dev_err(di->dev, "bus error on seal: %d\n", ret);
1189 return ret;
1190 }
1191
1192 return 0;
1193 }
1194
1195 static int bq27xxx_battery_unseal(struct bq27xxx_device_info *di)
1196 {
1197 int ret;
1198
1199 if (di->unseal_key == 0) {
1200 dev_err(di->dev, "unseal failed due to missing key\n");
1201 return -EINVAL;
1202 }
1203
1204 ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)(di->unseal_key >> 16), false);
1205 if (ret < 0)
1206 goto out;
1207
1208 ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, (u16)di->unseal_key, false);
1209 if (ret < 0)
1210 goto out;
1211
1212 return 0;
1213
1214 out:
1215 dev_err(di->dev, "bus error on unseal: %d\n", ret);
1216 return ret;
1217 }
1218
1219 static u8 bq27xxx_battery_checksum_dm_block(struct bq27xxx_dm_buf *buf)
1220 {
1221 u16 sum = 0;
1222 int i;
1223
1224 for (i = 0; i < BQ27XXX_DM_SZ; i++)
1225 sum += buf->data[i];
1226 sum &= 0xff;
1227
1228 return 0xff - sum;
1229 }
1230
1231 static int bq27xxx_battery_read_dm_block(struct bq27xxx_device_info *di,
1232 struct bq27xxx_dm_buf *buf)
1233 {
1234 int ret;
1235
1236 buf->has_data = false;
1237
1238 ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
1239 if (ret < 0)
1240 goto out;
1241
1242 ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
1243 if (ret < 0)
1244 goto out;
1245
1246 BQ27XXX_MSLEEP(1);
1247
1248 ret = bq27xxx_read_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
1249 if (ret < 0)
1250 goto out;
1251
1252 ret = bq27xxx_read(di, BQ27XXX_DM_CKSUM, true);
1253 if (ret < 0)
1254 goto out;
1255
1256 if ((u8)ret != bq27xxx_battery_checksum_dm_block(buf)) {
1257 ret = -EINVAL;
1258 goto out;
1259 }
1260
1261 buf->has_data = true;
1262 buf->dirty = false;
1263
1264 return 0;
1265
1266 out:
1267 dev_err(di->dev, "bus error reading chip memory: %d\n", ret);
1268 return ret;
1269 }
1270
1271 static void bq27xxx_battery_update_dm_block(struct bq27xxx_device_info *di,
1272 struct bq27xxx_dm_buf *buf,
1273 enum bq27xxx_dm_reg_id reg_id,
1274 unsigned int val)
1275 {
1276 struct bq27xxx_dm_reg *reg = &di->dm_regs[reg_id];
1277 const char *str = bq27xxx_dm_reg_name[reg_id];
1278 u16 *prev = bq27xxx_dm_reg_ptr(buf, reg);
1279
1280 if (prev == NULL) {
1281 dev_warn(di->dev, "buffer does not match %s dm spec\n", str);
1282 return;
1283 }
1284
1285 if (reg->bytes != 2) {
1286 dev_warn(di->dev, "%s dm spec has unsupported byte size\n", str);
1287 return;
1288 }
1289
1290 if (!buf->has_data)
1291 return;
1292
1293 if (be16_to_cpup(prev) == val) {
1294 dev_info(di->dev, "%s has %u\n", str, val);
1295 return;
1296 }
1297
1298 #ifdef CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM
1299 if (!(di->opts & BQ27XXX_O_RAM) && !bq27xxx_dt_to_nvm) {
1300 #else
1301 if (!(di->opts & BQ27XXX_O_RAM)) {
1302 #endif
1303
1304 dev_warn(di->dev, "%s has %u; update to %u disallowed "
1305 #ifdef CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM
1306 "by dt_monitored_battery_updates_nvm=0"
1307 #else
1308 "for flash/NVM data memory"
1309 #endif
1310 "\n", str, be16_to_cpup(prev), val);
1311 return;
1312 }
1313
1314 dev_info(di->dev, "update %s to %u\n", str, val);
1315
1316 *prev = cpu_to_be16(val);
1317 buf->dirty = true;
1318 }
1319
1320 static int bq27xxx_battery_cfgupdate_priv(struct bq27xxx_device_info *di, bool active)
1321 {
1322 const int limit = 100;
1323 u16 cmd = active ? BQ27XXX_SET_CFGUPDATE : BQ27XXX_SOFT_RESET;
1324 int ret, try = limit;
1325
1326 ret = bq27xxx_write(di, BQ27XXX_REG_CTRL, cmd, false);
1327 if (ret < 0)
1328 return ret;
1329
1330 do {
1331 BQ27XXX_MSLEEP(25);
1332 ret = bq27xxx_read(di, BQ27XXX_REG_FLAGS, false);
1333 if (ret < 0)
1334 return ret;
1335 } while (!!(ret & BQ27XXX_FLAG_CFGUP) != active && --try);
1336
1337 if (!try && di->chip != BQ27425) {
1338 dev_err(di->dev, "timed out waiting for cfgupdate flag %d\n", active);
1339 return -EINVAL;
1340 }
1341
1342 if (limit - try > 3)
1343 dev_warn(di->dev, "cfgupdate %d, retries %d\n", active, limit - try);
1344
1345 return 0;
1346 }
1347
1348 static inline int bq27xxx_battery_set_cfgupdate(struct bq27xxx_device_info *di)
1349 {
1350 int ret = bq27xxx_battery_cfgupdate_priv(di, true);
1351 if (ret < 0 && ret != -EINVAL)
1352 dev_err(di->dev, "bus error on set_cfgupdate: %d\n", ret);
1353
1354 return ret;
1355 }
1356
1357 static inline int bq27xxx_battery_soft_reset(struct bq27xxx_device_info *di)
1358 {
1359 int ret = bq27xxx_battery_cfgupdate_priv(di, false);
1360 if (ret < 0 && ret != -EINVAL)
1361 dev_err(di->dev, "bus error on soft_reset: %d\n", ret);
1362
1363 return ret;
1364 }
1365
1366 static int bq27xxx_battery_write_dm_block(struct bq27xxx_device_info *di,
1367 struct bq27xxx_dm_buf *buf)
1368 {
1369 bool cfgup = di->opts & BQ27XXX_O_CFGUP;
1370 int ret;
1371
1372 if (!buf->dirty)
1373 return 0;
1374
1375 if (cfgup) {
1376 ret = bq27xxx_battery_set_cfgupdate(di);
1377 if (ret < 0)
1378 return ret;
1379 }
1380
1381 ret = bq27xxx_write(di, BQ27XXX_DM_CTRL, 0, true);
1382 if (ret < 0)
1383 goto out;
1384
1385 ret = bq27xxx_write(di, BQ27XXX_DM_CLASS, buf->class, true);
1386 if (ret < 0)
1387 goto out;
1388
1389 ret = bq27xxx_write(di, BQ27XXX_DM_BLOCK, buf->block, true);
1390 if (ret < 0)
1391 goto out;
1392
1393 BQ27XXX_MSLEEP(1);
1394
1395 ret = bq27xxx_write_block(di, BQ27XXX_DM_DATA, buf->data, BQ27XXX_DM_SZ);
1396 if (ret < 0)
1397 goto out;
1398
1399 ret = bq27xxx_write(di, BQ27XXX_DM_CKSUM,
1400 bq27xxx_battery_checksum_dm_block(buf), true);
1401 if (ret < 0)
1402 goto out;
1403
1404
1405
1406
1407
1408
1409 if (cfgup) {
1410 BQ27XXX_MSLEEP(1);
1411 ret = bq27xxx_battery_soft_reset(di);
1412 if (ret < 0)
1413 return ret;
1414 } else {
1415 BQ27XXX_MSLEEP(100);
1416 }
1417
1418 buf->dirty = false;
1419
1420 return 0;
1421
1422 out:
1423 if (cfgup)
1424 bq27xxx_battery_soft_reset(di);
1425
1426 dev_err(di->dev, "bus error writing chip memory: %d\n", ret);
1427 return ret;
1428 }
1429
1430 static void bq27xxx_battery_set_config(struct bq27xxx_device_info *di,
1431 struct power_supply_battery_info *info)
1432 {
1433 struct bq27xxx_dm_buf bd = BQ27XXX_DM_BUF(di, BQ27XXX_DM_DESIGN_CAPACITY);
1434 struct bq27xxx_dm_buf bt = BQ27XXX_DM_BUF(di, BQ27XXX_DM_TERMINATE_VOLTAGE);
1435 bool updated;
1436
1437 if (bq27xxx_battery_unseal(di) < 0)
1438 return;
1439
1440 if (info->charge_full_design_uah != -EINVAL &&
1441 info->energy_full_design_uwh != -EINVAL) {
1442 bq27xxx_battery_read_dm_block(di, &bd);
1443
1444 bq27xxx_battery_update_dm_block(di, &bd,
1445 BQ27XXX_DM_DESIGN_CAPACITY,
1446 info->charge_full_design_uah / 1000);
1447 bq27xxx_battery_update_dm_block(di, &bd,
1448 BQ27XXX_DM_DESIGN_ENERGY,
1449 info->energy_full_design_uwh / 1000);
1450 }
1451
1452 if (info->voltage_min_design_uv != -EINVAL) {
1453 bool same = bd.class == bt.class && bd.block == bt.block;
1454 if (!same)
1455 bq27xxx_battery_read_dm_block(di, &bt);
1456 bq27xxx_battery_update_dm_block(di, same ? &bd : &bt,
1457 BQ27XXX_DM_TERMINATE_VOLTAGE,
1458 info->voltage_min_design_uv / 1000);
1459 }
1460
1461 updated = bd.dirty || bt.dirty;
1462
1463 bq27xxx_battery_write_dm_block(di, &bd);
1464 bq27xxx_battery_write_dm_block(di, &bt);
1465
1466 bq27xxx_battery_seal(di);
1467
1468 if (updated && !(di->opts & BQ27XXX_O_CFGUP)) {
1469 bq27xxx_write(di, BQ27XXX_REG_CTRL, BQ27XXX_RESET, false);
1470 BQ27XXX_MSLEEP(300);
1471 }
1472
1473 }
1474
1475 static void bq27xxx_battery_settings(struct bq27xxx_device_info *di)
1476 {
1477 struct power_supply_battery_info *info;
1478 unsigned int min, max;
1479
1480 if (power_supply_get_battery_info(di->bat, &info) < 0)
1481 return;
1482
1483 if (!di->dm_regs) {
1484 dev_warn(di->dev, "data memory update not supported for chip\n");
1485 return;
1486 }
1487
1488 if (info->energy_full_design_uwh != info->charge_full_design_uah) {
1489 if (info->energy_full_design_uwh == -EINVAL)
1490 dev_warn(di->dev, "missing battery:energy-full-design-microwatt-hours\n");
1491 else if (info->charge_full_design_uah == -EINVAL)
1492 dev_warn(di->dev, "missing battery:charge-full-design-microamp-hours\n");
1493 }
1494
1495
1496 max = di->dm_regs[BQ27XXX_DM_DESIGN_ENERGY].max;
1497 if (info->energy_full_design_uwh > max * 1000) {
1498 dev_err(di->dev, "invalid battery:energy-full-design-microwatt-hours %d\n",
1499 info->energy_full_design_uwh);
1500 info->energy_full_design_uwh = -EINVAL;
1501 }
1502
1503
1504 max = di->dm_regs[BQ27XXX_DM_DESIGN_CAPACITY].max;
1505 if (info->charge_full_design_uah > max * 1000) {
1506 dev_err(di->dev, "invalid battery:charge-full-design-microamp-hours %d\n",
1507 info->charge_full_design_uah);
1508 info->charge_full_design_uah = -EINVAL;
1509 }
1510
1511 min = di->dm_regs[BQ27XXX_DM_TERMINATE_VOLTAGE].min;
1512 max = di->dm_regs[BQ27XXX_DM_TERMINATE_VOLTAGE].max;
1513 if ((info->voltage_min_design_uv < min * 1000 ||
1514 info->voltage_min_design_uv > max * 1000) &&
1515 info->voltage_min_design_uv != -EINVAL) {
1516 dev_err(di->dev, "invalid battery:voltage-min-design-microvolt %d\n",
1517 info->voltage_min_design_uv);
1518 info->voltage_min_design_uv = -EINVAL;
1519 }
1520
1521 if ((info->energy_full_design_uwh != -EINVAL &&
1522 info->charge_full_design_uah != -EINVAL) ||
1523 info->voltage_min_design_uv != -EINVAL)
1524 bq27xxx_battery_set_config(di, info);
1525 }
1526
1527
1528
1529
1530
1531 static int bq27xxx_battery_read_soc(struct bq27xxx_device_info *di)
1532 {
1533 int soc;
1534
1535 if (di->opts & BQ27XXX_O_SOC_SI)
1536 soc = bq27xxx_read(di, BQ27XXX_REG_SOC, true);
1537 else
1538 soc = bq27xxx_read(di, BQ27XXX_REG_SOC, false);
1539
1540 if (soc < 0)
1541 dev_dbg(di->dev, "error reading State-of-Charge\n");
1542
1543 return soc;
1544 }
1545
1546
1547
1548
1549
1550 static int bq27xxx_battery_read_charge(struct bq27xxx_device_info *di, u8 reg)
1551 {
1552 int charge;
1553
1554 charge = bq27xxx_read(di, reg, false);
1555 if (charge < 0) {
1556 dev_dbg(di->dev, "error reading charge register %02x: %d\n",
1557 reg, charge);
1558 return charge;
1559 }
1560
1561 if (di->opts & BQ27XXX_O_ZERO)
1562 charge *= BQ27XXX_CURRENT_CONSTANT / BQ27XXX_RS;
1563 else
1564 charge *= 1000;
1565
1566 return charge;
1567 }
1568
1569
1570
1571
1572
1573 static inline int bq27xxx_battery_read_nac(struct bq27xxx_device_info *di)
1574 {
1575 return bq27xxx_battery_read_charge(di, BQ27XXX_REG_NAC);
1576 }
1577
1578
1579
1580
1581
1582 static inline int bq27xxx_battery_read_rc(struct bq27xxx_device_info *di)
1583 {
1584 return bq27xxx_battery_read_charge(di, BQ27XXX_REG_RC);
1585 }
1586
1587
1588
1589
1590
1591 static inline int bq27xxx_battery_read_fcc(struct bq27xxx_device_info *di)
1592 {
1593 return bq27xxx_battery_read_charge(di, BQ27XXX_REG_FCC);
1594 }
1595
1596
1597
1598
1599
1600 static int bq27xxx_battery_read_dcap(struct bq27xxx_device_info *di)
1601 {
1602 int dcap;
1603
1604 if (di->opts & BQ27XXX_O_ZERO)
1605 dcap = bq27xxx_read(di, BQ27XXX_REG_DCAP, true);
1606 else
1607 dcap = bq27xxx_read(di, BQ27XXX_REG_DCAP, false);
1608
1609 if (dcap < 0) {
1610 dev_dbg(di->dev, "error reading initial last measured discharge\n");
1611 return dcap;
1612 }
1613
1614 if (di->opts & BQ27XXX_O_ZERO)
1615 dcap = (dcap << 8) * BQ27XXX_CURRENT_CONSTANT / BQ27XXX_RS;
1616 else
1617 dcap *= 1000;
1618
1619 return dcap;
1620 }
1621
1622
1623
1624
1625
1626 static int bq27xxx_battery_read_energy(struct bq27xxx_device_info *di)
1627 {
1628 int ae;
1629
1630 ae = bq27xxx_read(di, BQ27XXX_REG_AE, false);
1631 if (ae < 0) {
1632 dev_dbg(di->dev, "error reading available energy\n");
1633 return ae;
1634 }
1635
1636 if (di->opts & BQ27XXX_O_ZERO)
1637 ae *= BQ27XXX_POWER_CONSTANT / BQ27XXX_RS;
1638 else
1639 ae *= 1000;
1640
1641 return ae;
1642 }
1643
1644
1645
1646
1647
1648 static int bq27xxx_battery_read_temperature(struct bq27xxx_device_info *di)
1649 {
1650 int temp;
1651
1652 temp = bq27xxx_read(di, BQ27XXX_REG_TEMP, false);
1653 if (temp < 0) {
1654 dev_err(di->dev, "error reading temperature\n");
1655 return temp;
1656 }
1657
1658 if (di->opts & BQ27XXX_O_ZERO)
1659 temp = 5 * temp / 2;
1660
1661 return temp;
1662 }
1663
1664
1665
1666
1667
1668 static int bq27xxx_battery_read_cyct(struct bq27xxx_device_info *di)
1669 {
1670 int cyct;
1671
1672 cyct = bq27xxx_read(di, BQ27XXX_REG_CYCT, false);
1673 if (cyct < 0)
1674 dev_err(di->dev, "error reading cycle count total\n");
1675
1676 return cyct;
1677 }
1678
1679
1680
1681
1682
1683 static int bq27xxx_battery_read_time(struct bq27xxx_device_info *di, u8 reg)
1684 {
1685 int tval;
1686
1687 tval = bq27xxx_read(di, reg, false);
1688 if (tval < 0) {
1689 dev_dbg(di->dev, "error reading time register %02x: %d\n",
1690 reg, tval);
1691 return tval;
1692 }
1693
1694 if (tval == 65535)
1695 return -ENODATA;
1696
1697 return tval * 60;
1698 }
1699
1700
1701
1702
1703 static bool bq27xxx_battery_overtemp(struct bq27xxx_device_info *di, u16 flags)
1704 {
1705 if (di->opts & BQ27XXX_O_OTDC)
1706 return flags & (BQ27XXX_FLAG_OTC | BQ27XXX_FLAG_OTD);
1707 if (di->opts & BQ27XXX_O_UTOT)
1708 return flags & BQ27XXX_FLAG_OT;
1709
1710 return false;
1711 }
1712
1713
1714
1715
1716 static bool bq27xxx_battery_undertemp(struct bq27xxx_device_info *di, u16 flags)
1717 {
1718 if (di->opts & BQ27XXX_O_UTOT)
1719 return flags & BQ27XXX_FLAG_UT;
1720
1721 return false;
1722 }
1723
1724
1725
1726
1727 static bool bq27xxx_battery_dead(struct bq27xxx_device_info *di, u16 flags)
1728 {
1729 if (di->opts & BQ27XXX_O_ZERO)
1730 return flags & (BQ27000_FLAG_EDV1 | BQ27000_FLAG_EDVF);
1731 else if (di->opts & BQ27Z561_O_BITS)
1732 return flags & BQ27Z561_FLAG_FDC;
1733 else
1734 return flags & (BQ27XXX_FLAG_SOC1 | BQ27XXX_FLAG_SOCF);
1735 }
1736
1737
1738
1739
1740 static bool bq27xxx_battery_capacity_inaccurate(struct bq27xxx_device_info *di,
1741 u16 flags)
1742 {
1743 if (di->opts & BQ27XXX_O_HAS_CI)
1744 return (flags & BQ27000_FLAG_CI);
1745 else
1746 return false;
1747 }
1748
1749 static int bq27xxx_battery_read_health(struct bq27xxx_device_info *di)
1750 {
1751
1752 if (unlikely(bq27xxx_battery_overtemp(di, di->cache.flags)))
1753 return POWER_SUPPLY_HEALTH_OVERHEAT;
1754 if (unlikely(bq27xxx_battery_undertemp(di, di->cache.flags)))
1755 return POWER_SUPPLY_HEALTH_COLD;
1756 if (unlikely(bq27xxx_battery_dead(di, di->cache.flags)))
1757 return POWER_SUPPLY_HEALTH_DEAD;
1758 if (unlikely(bq27xxx_battery_capacity_inaccurate(di, di->cache.flags)))
1759 return POWER_SUPPLY_HEALTH_CALIBRATION_REQUIRED;
1760
1761 return POWER_SUPPLY_HEALTH_GOOD;
1762 }
1763
1764 void bq27xxx_battery_update(struct bq27xxx_device_info *di)
1765 {
1766 struct bq27xxx_reg_cache cache = {0, };
1767 bool has_singe_flag = di->opts & BQ27XXX_O_ZERO;
1768
1769 cache.flags = bq27xxx_read(di, BQ27XXX_REG_FLAGS, has_singe_flag);
1770 if ((cache.flags & 0xff) == 0xff)
1771 cache.flags = -1;
1772 if (cache.flags >= 0) {
1773 cache.temperature = bq27xxx_battery_read_temperature(di);
1774 if (di->regs[BQ27XXX_REG_TTE] != INVALID_REG_ADDR)
1775 cache.time_to_empty = bq27xxx_battery_read_time(di, BQ27XXX_REG_TTE);
1776 if (di->regs[BQ27XXX_REG_TTECP] != INVALID_REG_ADDR)
1777 cache.time_to_empty_avg = bq27xxx_battery_read_time(di, BQ27XXX_REG_TTECP);
1778 if (di->regs[BQ27XXX_REG_TTF] != INVALID_REG_ADDR)
1779 cache.time_to_full = bq27xxx_battery_read_time(di, BQ27XXX_REG_TTF);
1780
1781 cache.charge_full = bq27xxx_battery_read_fcc(di);
1782 cache.capacity = bq27xxx_battery_read_soc(di);
1783 if (di->regs[BQ27XXX_REG_AE] != INVALID_REG_ADDR)
1784 cache.energy = bq27xxx_battery_read_energy(di);
1785 di->cache.flags = cache.flags;
1786 cache.health = bq27xxx_battery_read_health(di);
1787 if (di->regs[BQ27XXX_REG_CYCT] != INVALID_REG_ADDR)
1788 cache.cycle_count = bq27xxx_battery_read_cyct(di);
1789
1790
1791 if (di->charge_design_full <= 0)
1792 di->charge_design_full = bq27xxx_battery_read_dcap(di);
1793 }
1794
1795 if ((di->cache.capacity != cache.capacity) ||
1796 (di->cache.flags != cache.flags))
1797 power_supply_changed(di->bat);
1798
1799 if (memcmp(&di->cache, &cache, sizeof(cache)) != 0)
1800 di->cache = cache;
1801
1802 di->last_update = jiffies;
1803 }
1804 EXPORT_SYMBOL_GPL(bq27xxx_battery_update);
1805
1806 static void bq27xxx_battery_poll(struct work_struct *work)
1807 {
1808 struct bq27xxx_device_info *di =
1809 container_of(work, struct bq27xxx_device_info,
1810 work.work);
1811
1812 bq27xxx_battery_update(di);
1813
1814 if (poll_interval > 0)
1815 schedule_delayed_work(&di->work, poll_interval * HZ);
1816 }
1817
1818 static bool bq27xxx_battery_is_full(struct bq27xxx_device_info *di, int flags)
1819 {
1820 if (di->opts & BQ27XXX_O_ZERO)
1821 return (flags & BQ27000_FLAG_FC);
1822 else if (di->opts & BQ27Z561_O_BITS)
1823 return (flags & BQ27Z561_FLAG_FC);
1824 else
1825 return (flags & BQ27XXX_FLAG_FC);
1826 }
1827
1828
1829
1830
1831
1832
1833 static int bq27xxx_battery_current_and_status(
1834 struct bq27xxx_device_info *di,
1835 union power_supply_propval *val_curr,
1836 union power_supply_propval *val_status)
1837 {
1838 bool single_flags = (di->opts & BQ27XXX_O_ZERO);
1839 int curr;
1840 int flags;
1841
1842 curr = bq27xxx_read(di, BQ27XXX_REG_AI, false);
1843 if (curr < 0) {
1844 dev_err(di->dev, "error reading current\n");
1845 return curr;
1846 }
1847
1848 flags = bq27xxx_read(di, BQ27XXX_REG_FLAGS, single_flags);
1849 if (flags < 0) {
1850 dev_err(di->dev, "error reading flags\n");
1851 return flags;
1852 }
1853
1854 if (di->opts & BQ27XXX_O_ZERO) {
1855 if (!(flags & BQ27000_FLAG_CHGS)) {
1856 dev_dbg(di->dev, "negative current!\n");
1857 curr = -curr;
1858 }
1859
1860 curr = curr * BQ27XXX_CURRENT_CONSTANT / BQ27XXX_RS;
1861 } else {
1862
1863 curr = (int)((s16)curr) * 1000;
1864 }
1865
1866 if (val_curr)
1867 val_curr->intval = curr;
1868
1869 if (val_status) {
1870 if (curr > 0) {
1871 val_status->intval = POWER_SUPPLY_STATUS_CHARGING;
1872 } else if (curr < 0) {
1873 val_status->intval = POWER_SUPPLY_STATUS_DISCHARGING;
1874 } else {
1875 if (bq27xxx_battery_is_full(di, flags))
1876 val_status->intval = POWER_SUPPLY_STATUS_FULL;
1877 else
1878 val_status->intval =
1879 POWER_SUPPLY_STATUS_NOT_CHARGING;
1880 }
1881 }
1882
1883 return 0;
1884 }
1885
1886
1887
1888
1889
1890 static int bq27xxx_battery_pwr_avg(struct bq27xxx_device_info *di,
1891 union power_supply_propval *val)
1892 {
1893 int power;
1894
1895 power = bq27xxx_read(di, BQ27XXX_REG_AP, false);
1896 if (power < 0) {
1897 dev_err(di->dev,
1898 "error reading average power register %02x: %d\n",
1899 BQ27XXX_REG_AP, power);
1900 return power;
1901 }
1902
1903 if (di->opts & BQ27XXX_O_ZERO)
1904 val->intval = (power * BQ27XXX_POWER_CONSTANT) / BQ27XXX_RS;
1905 else
1906
1907 val->intval = (int)((s16)power) * 10000;
1908
1909 return 0;
1910 }
1911
1912 static int bq27xxx_battery_capacity_level(struct bq27xxx_device_info *di,
1913 union power_supply_propval *val)
1914 {
1915 int level;
1916
1917 if (di->opts & BQ27XXX_O_ZERO) {
1918 if (di->cache.flags & BQ27000_FLAG_FC)
1919 level = POWER_SUPPLY_CAPACITY_LEVEL_FULL;
1920 else if (di->cache.flags & BQ27000_FLAG_EDV1)
1921 level = POWER_SUPPLY_CAPACITY_LEVEL_LOW;
1922 else if (di->cache.flags & BQ27000_FLAG_EDVF)
1923 level = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL;
1924 else
1925 level = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL;
1926 } else if (di->opts & BQ27Z561_O_BITS) {
1927 if (di->cache.flags & BQ27Z561_FLAG_FC)
1928 level = POWER_SUPPLY_CAPACITY_LEVEL_FULL;
1929 else if (di->cache.flags & BQ27Z561_FLAG_FDC)
1930 level = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL;
1931 else
1932 level = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL;
1933 } else {
1934 if (di->cache.flags & BQ27XXX_FLAG_FC)
1935 level = POWER_SUPPLY_CAPACITY_LEVEL_FULL;
1936 else if (di->cache.flags & BQ27XXX_FLAG_SOC1)
1937 level = POWER_SUPPLY_CAPACITY_LEVEL_LOW;
1938 else if (di->cache.flags & BQ27XXX_FLAG_SOCF)
1939 level = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL;
1940 else
1941 level = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL;
1942 }
1943
1944 val->intval = level;
1945
1946 return 0;
1947 }
1948
1949
1950
1951
1952
1953 static int bq27xxx_battery_voltage(struct bq27xxx_device_info *di,
1954 union power_supply_propval *val)
1955 {
1956 int volt;
1957
1958 volt = bq27xxx_read(di, BQ27XXX_REG_VOLT, false);
1959 if (volt < 0) {
1960 dev_err(di->dev, "error reading voltage\n");
1961 return volt;
1962 }
1963
1964 val->intval = volt * 1000;
1965
1966 return 0;
1967 }
1968
1969 static int bq27xxx_simple_value(int value,
1970 union power_supply_propval *val)
1971 {
1972 if (value < 0)
1973 return value;
1974
1975 val->intval = value;
1976
1977 return 0;
1978 }
1979
1980 static int bq27xxx_battery_get_property(struct power_supply *psy,
1981 enum power_supply_property psp,
1982 union power_supply_propval *val)
1983 {
1984 int ret = 0;
1985 struct bq27xxx_device_info *di = power_supply_get_drvdata(psy);
1986
1987 mutex_lock(&di->lock);
1988 if (time_is_before_jiffies(di->last_update + 5 * HZ)) {
1989 cancel_delayed_work_sync(&di->work);
1990 bq27xxx_battery_poll(&di->work.work);
1991 }
1992 mutex_unlock(&di->lock);
1993
1994 if (psp != POWER_SUPPLY_PROP_PRESENT && di->cache.flags < 0)
1995 return -ENODEV;
1996
1997 switch (psp) {
1998 case POWER_SUPPLY_PROP_STATUS:
1999 ret = bq27xxx_battery_current_and_status(di, NULL, val);
2000 break;
2001 case POWER_SUPPLY_PROP_VOLTAGE_NOW:
2002 ret = bq27xxx_battery_voltage(di, val);
2003 break;
2004 case POWER_SUPPLY_PROP_PRESENT:
2005 val->intval = di->cache.flags < 0 ? 0 : 1;
2006 break;
2007 case POWER_SUPPLY_PROP_CURRENT_NOW:
2008 ret = bq27xxx_battery_current_and_status(di, val, NULL);
2009 break;
2010 case POWER_SUPPLY_PROP_CAPACITY:
2011 ret = bq27xxx_simple_value(di->cache.capacity, val);
2012 break;
2013 case POWER_SUPPLY_PROP_CAPACITY_LEVEL:
2014 ret = bq27xxx_battery_capacity_level(di, val);
2015 break;
2016 case POWER_SUPPLY_PROP_TEMP:
2017 ret = bq27xxx_simple_value(di->cache.temperature, val);
2018 if (ret == 0)
2019 val->intval -= 2731;
2020 break;
2021 case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW:
2022 ret = bq27xxx_simple_value(di->cache.time_to_empty, val);
2023 break;
2024 case POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG:
2025 ret = bq27xxx_simple_value(di->cache.time_to_empty_avg, val);
2026 break;
2027 case POWER_SUPPLY_PROP_TIME_TO_FULL_NOW:
2028 ret = bq27xxx_simple_value(di->cache.time_to_full, val);
2029 break;
2030 case POWER_SUPPLY_PROP_TECHNOLOGY:
2031 if (di->opts & BQ27XXX_O_MUL_CHEM)
2032 val->intval = POWER_SUPPLY_TECHNOLOGY_UNKNOWN;
2033 else
2034 val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
2035 break;
2036 case POWER_SUPPLY_PROP_CHARGE_NOW:
2037 if (di->regs[BQ27XXX_REG_NAC] != INVALID_REG_ADDR)
2038 ret = bq27xxx_simple_value(bq27xxx_battery_read_nac(di), val);
2039 else
2040 ret = bq27xxx_simple_value(bq27xxx_battery_read_rc(di), val);
2041 break;
2042 case POWER_SUPPLY_PROP_CHARGE_FULL:
2043 ret = bq27xxx_simple_value(di->cache.charge_full, val);
2044 break;
2045 case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
2046 ret = bq27xxx_simple_value(di->charge_design_full, val);
2047 break;
2048
2049
2050
2051
2052 case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:
2053 case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
2054 return -EINVAL;
2055 case POWER_SUPPLY_PROP_CYCLE_COUNT:
2056 ret = bq27xxx_simple_value(di->cache.cycle_count, val);
2057 break;
2058 case POWER_SUPPLY_PROP_ENERGY_NOW:
2059 ret = bq27xxx_simple_value(di->cache.energy, val);
2060 break;
2061 case POWER_SUPPLY_PROP_POWER_AVG:
2062 ret = bq27xxx_battery_pwr_avg(di, val);
2063 break;
2064 case POWER_SUPPLY_PROP_HEALTH:
2065 ret = bq27xxx_simple_value(di->cache.health, val);
2066 break;
2067 case POWER_SUPPLY_PROP_MANUFACTURER:
2068 val->strval = BQ27XXX_MANUFACTURER;
2069 break;
2070 default:
2071 return -EINVAL;
2072 }
2073
2074 return ret;
2075 }
2076
2077 static void bq27xxx_external_power_changed(struct power_supply *psy)
2078 {
2079 struct bq27xxx_device_info *di = power_supply_get_drvdata(psy);
2080
2081 cancel_delayed_work_sync(&di->work);
2082 schedule_delayed_work(&di->work, 0);
2083 }
2084
2085 int bq27xxx_battery_setup(struct bq27xxx_device_info *di)
2086 {
2087 struct power_supply_desc *psy_desc;
2088 struct power_supply_config psy_cfg = {
2089 .of_node = di->dev->of_node,
2090 .drv_data = di,
2091 };
2092
2093 INIT_DELAYED_WORK(&di->work, bq27xxx_battery_poll);
2094 mutex_init(&di->lock);
2095
2096 di->regs = bq27xxx_chip_data[di->chip].regs;
2097 di->unseal_key = bq27xxx_chip_data[di->chip].unseal_key;
2098 di->dm_regs = bq27xxx_chip_data[di->chip].dm_regs;
2099 di->opts = bq27xxx_chip_data[di->chip].opts;
2100
2101 psy_desc = devm_kzalloc(di->dev, sizeof(*psy_desc), GFP_KERNEL);
2102 if (!psy_desc)
2103 return -ENOMEM;
2104
2105 psy_desc->name = di->name;
2106 psy_desc->type = POWER_SUPPLY_TYPE_BATTERY;
2107 psy_desc->properties = bq27xxx_chip_data[di->chip].props;
2108 psy_desc->num_properties = bq27xxx_chip_data[di->chip].props_size;
2109 psy_desc->get_property = bq27xxx_battery_get_property;
2110 psy_desc->external_power_changed = bq27xxx_external_power_changed;
2111
2112 di->bat = power_supply_register_no_ws(di->dev, psy_desc, &psy_cfg);
2113 if (IS_ERR(di->bat))
2114 return dev_err_probe(di->dev, PTR_ERR(di->bat),
2115 "failed to register battery\n");
2116
2117 bq27xxx_battery_settings(di);
2118 bq27xxx_battery_update(di);
2119
2120 mutex_lock(&bq27xxx_list_lock);
2121 list_add(&di->list, &bq27xxx_battery_devices);
2122 mutex_unlock(&bq27xxx_list_lock);
2123
2124 return 0;
2125 }
2126 EXPORT_SYMBOL_GPL(bq27xxx_battery_setup);
2127
2128 void bq27xxx_battery_teardown(struct bq27xxx_device_info *di)
2129 {
2130
2131
2132
2133
2134
2135
2136 poll_interval = 0;
2137
2138 cancel_delayed_work_sync(&di->work);
2139
2140 power_supply_unregister(di->bat);
2141
2142 mutex_lock(&bq27xxx_list_lock);
2143 list_del(&di->list);
2144 mutex_unlock(&bq27xxx_list_lock);
2145
2146 mutex_destroy(&di->lock);
2147 }
2148 EXPORT_SYMBOL_GPL(bq27xxx_battery_teardown);
2149
2150 MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>");
2151 MODULE_DESCRIPTION("BQ27xxx battery monitor driver");
2152 MODULE_LICENSE("GPL");
