power/reset/at91-reset.c

0001 /*
0002  * Atmel AT91 SAM9 & SAMA5 SoCs reset code
0003  *
0004  * Copyright (C) 2007 Atmel Corporation.
0005  * Copyright (C) BitBox Ltd 2010
0006  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
0007  * Copyright (C) 2014 Free Electrons
0008  *
0009  * This file is licensed under the terms of the GNU General Public
0010  * License version 2.  This program is licensed "as is" without any
0011  * warranty of any kind, whether express or implied.
0012  */
0013
0014 #include <linux/clk.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/of_address.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/reboot.h>
0020 #include <linux/reset-controller.h>
0021
0022 #include <soc/at91/at91sam9_ddrsdr.h>
0023 #include <soc/at91/at91sam9_sdramc.h>
0024
0025 #include <dt-bindings/reset/sama7g5-reset.h>
0026
0027 #define AT91_RSTC_CR    0x00        /* Reset Controller Control Register */
0028 #define AT91_RSTC_PROCRST   BIT(0)      /* Processor Reset */
0029 #define AT91_RSTC_PERRST    BIT(2)      /* Peripheral Reset */
0030 #define AT91_RSTC_EXTRST    BIT(3)      /* External Reset */
0031 #define AT91_RSTC_KEY       (0xa5 << 24)    /* KEY Password */
0032
0033 #define AT91_RSTC_SR    0x04        /* Reset Controller Status Register */
0034 #define AT91_RSTC_URSTS     BIT(0)      /* User Reset Status */
0035 #define AT91_RSTC_RSTTYP    GENMASK(10, 8)  /* Reset Type */
0036 #define AT91_RSTC_NRSTL     BIT(16)     /* NRST Pin Level */
0037 #define AT91_RSTC_SRCMP     BIT(17)     /* Software Reset Command in Progress */
0038
0039 #define AT91_RSTC_MR    0x08        /* Reset Controller Mode Register */
0040 #define AT91_RSTC_URSTEN    BIT(0)      /* User Reset Enable */
0041 #define AT91_RSTC_URSTASYNC BIT(2)      /* User Reset Asynchronous Control */
0042 #define AT91_RSTC_URSTIEN   BIT(4)      /* User Reset Interrupt Enable */
0043 #define AT91_RSTC_ERSTL     GENMASK(11, 8)  /* External Reset Length */
0044
0045 /**
0046  * enum reset_type - reset types
0047  * @RESET_TYPE_GENERAL:     first power-up reset
0048  * @RESET_TYPE_WAKEUP:      return from backup mode
0049  * @RESET_TYPE_WATCHDOG:    watchdog fault
0050  * @RESET_TYPE_SOFTWARE:    processor reset required by software
0051  * @RESET_TYPE_USER:        NRST pin detected low
0052  * @RESET_TYPE_CPU_FAIL:    CPU clock failure detection
0053  * @RESET_TYPE_XTAL_FAIL:   32KHz crystal failure dectection fault
0054  * @RESET_TYPE_ULP2:        ULP2 reset
0055  */
0056 enum reset_type {
0057     RESET_TYPE_GENERAL  = 0,
0058     RESET_TYPE_WAKEUP   = 1,
0059     RESET_TYPE_WATCHDOG = 2,
0060     RESET_TYPE_SOFTWARE = 3,
0061     RESET_TYPE_USER     = 4,
0062     RESET_TYPE_CPU_FAIL = 6,
0063     RESET_TYPE_XTAL_FAIL    = 7,
0064     RESET_TYPE_ULP2     = 8,
0065 };
0066
0067 /**
0068  * struct at91_reset - AT91 reset specific data structure
0069  * @rstc_base:      base address for system reset
0070  * @ramc_base:      array with base addresses of RAM controllers
0071  * @dev_base:       base address for devices reset
0072  * @sclk:       slow clock
0073  * @data:       platform specific reset data
0074  * @rcdev:      reset controller device
0075  * @lock:       lock for devices reset register access
0076  * @nb:         reset notifier block
0077  * @args:       SoC specific system reset arguments
0078  * @ramc_lpr:       SDRAM Controller Low Power Register
0079  */
0080 struct at91_reset {
0081     void __iomem *rstc_base;
0082     void __iomem *ramc_base[2];
0083     void __iomem *dev_base;
0084     struct clk *sclk;
0085     const struct at91_reset_data *data;
0086     struct reset_controller_dev rcdev;
0087     spinlock_t lock;
0088     struct notifier_block nb;
0089     u32 args;
0090     u32 ramc_lpr;
0091 };
0092
0093 #define to_at91_reset(r)    container_of(r, struct at91_reset, rcdev)
0094
0095 /**
0096  * struct at91_reset_data - AT91 reset data
0097  * @reset_args:         SoC specific system reset arguments
0098  * @n_device_reset:     number of device resets
0099  * @device_reset_min_id:    min id for device reset
0100  * @device_reset_max_id:    max id for device reset
0101  */
0102 struct at91_reset_data {
0103     u32 reset_args;
0104     u32 n_device_reset;
0105     u8 device_reset_min_id;
0106     u8 device_reset_max_id;
0107 };
0108
0109 /*
0110 * unless the SDRAM is cleanly shutdown before we hit the
0111 * reset register it can be left driving the data bus and
0112 * killing the chance of a subsequent boot from NAND
0113 */
0114 static int at91_reset(struct notifier_block *this, unsigned long mode,
0115               void *cmd)
0116 {
0117     struct at91_reset *reset = container_of(this, struct at91_reset, nb);
0118
0119     asm volatile(
0120         /* Align to cache lines */
0121         ".balign 32\n\t"
0122
0123         /* Disable SDRAM0 accesses */
0124         "   tst %0, #0\n\t"
0125         "   beq 1f\n\t"
0126         "   str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
0127         /* Power down SDRAM0 */
0128         "   str %4, [%0, %6]\n\t"
0129         /* Disable SDRAM1 accesses */
0130         "1: tst %1, #0\n\t"
0131         "   beq 2f\n\t"
0132         "   strne   %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
0133         /* Power down SDRAM1 */
0134         "   strne   %4, [%1, %6]\n\t"
0135         /* Reset CPU */
0136         "2: str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
0137
0138         "   b   .\n\t"
0139         :
0140         : "r" (reset->ramc_base[0]),
0141           "r" (reset->ramc_base[1]),
0142           "r" (reset->rstc_base),
0143           "r" (1),
0144           "r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN),
0145           "r" (reset->data->reset_args),
0146           "r" (reset->ramc_lpr)
0147         : "r4");
0148
0149     return NOTIFY_DONE;
0150 }
0151
0152 static void __init at91_reset_status(struct platform_device *pdev,
0153                      void __iomem *base)
0154 {
0155     const char *reason;
0156     u32 reg = readl(base + AT91_RSTC_SR);
0157
0158     switch ((reg & AT91_RSTC_RSTTYP) >> 8) {
0159     case RESET_TYPE_GENERAL:
0160         reason = "general reset";
0161         break;
0162     case RESET_TYPE_WAKEUP:
0163         reason = "wakeup";
0164         break;
0165     case RESET_TYPE_WATCHDOG:
0166         reason = "watchdog reset";
0167         break;
0168     case RESET_TYPE_SOFTWARE:
0169         reason = "software reset";
0170         break;
0171     case RESET_TYPE_USER:
0172         reason = "user reset";
0173         break;
0174     case RESET_TYPE_CPU_FAIL:
0175         reason = "CPU clock failure detection";
0176         break;
0177     case RESET_TYPE_XTAL_FAIL:
0178         reason = "32.768 kHz crystal failure detection";
0179         break;
0180     case RESET_TYPE_ULP2:
0181         reason = "ULP2 reset";
0182         break;
0183     default:
0184         reason = "unknown reset";
0185         break;
0186     }
0187
0188     dev_info(&pdev->dev, "Starting after %s\n", reason);
0189 }
0190
0191 static const struct of_device_id at91_ramc_of_match[] = {
0192     {
0193         .compatible = "atmel,at91sam9260-sdramc",
0194         .data = (void *)AT91_SDRAMC_LPR,
0195     },
0196     {
0197         .compatible = "atmel,at91sam9g45-ddramc",
0198         .data = (void *)AT91_DDRSDRC_LPR,
0199     },
0200     { /* sentinel */ }
0201 };
0202
0203 static const struct at91_reset_data sam9260 = {
0204     .reset_args = AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST,
0205 };
0206
0207 static const struct at91_reset_data samx7 = {
0208     .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST,
0209 };
0210
0211 static const struct at91_reset_data sama7g5 = {
0212     .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST,
0213     .n_device_reset = 3,
0214     .device_reset_min_id = SAMA7G5_RESET_USB_PHY1,
0215     .device_reset_max_id = SAMA7G5_RESET_USB_PHY3,
0216 };
0217
0218 static const struct of_device_id at91_reset_of_match[] = {
0219     {
0220         .compatible = "atmel,at91sam9260-rstc",
0221         .data = &sam9260,
0222     },
0223     {
0224         .compatible = "atmel,at91sam9g45-rstc",
0225         .data = &sam9260,
0226     },
0227     {
0228         .compatible = "atmel,sama5d3-rstc",
0229         .data = &sam9260,
0230     },
0231     {
0232         .compatible = "atmel,samx7-rstc",
0233         .data = &samx7,
0234     },
0235     {
0236         .compatible = "microchip,sam9x60-rstc",
0237         .data = &samx7,
0238     },
0239     {
0240         .compatible = "microchip,sama7g5-rstc",
0241         .data = &sama7g5,
0242     },
0243     { /* sentinel */ }
0244 };
0245 MODULE_DEVICE_TABLE(of, at91_reset_of_match);
0246
0247 static int at91_reset_update(struct reset_controller_dev *rcdev,
0248                  unsigned long id, bool assert)
0249 {
0250     struct at91_reset *reset = to_at91_reset(rcdev);
0251     unsigned long flags;
0252     u32 val;
0253
0254     spin_lock_irqsave(&reset->lock, flags);
0255     val = readl_relaxed(reset->dev_base);
0256     if (assert)
0257         val |= BIT(id);
0258     else
0259         val &= ~BIT(id);
0260     writel_relaxed(val, reset->dev_base);
0261     spin_unlock_irqrestore(&reset->lock, flags);
0262
0263     return 0;
0264 }
0265
0266 static int at91_reset_assert(struct reset_controller_dev *rcdev,
0267                  unsigned long id)
0268 {
0269     return at91_reset_update(rcdev, id, true);
0270 }
0271
0272 static int at91_reset_deassert(struct reset_controller_dev *rcdev,
0273                    unsigned long id)
0274 {
0275     return at91_reset_update(rcdev, id, false);
0276 }
0277
0278 static int at91_reset_dev_status(struct reset_controller_dev *rcdev,
0279                  unsigned long id)
0280 {
0281     struct at91_reset *reset = to_at91_reset(rcdev);
0282     u32 val;
0283
0284     val = readl_relaxed(reset->dev_base);
0285
0286     return !!(val & BIT(id));
0287 }
0288
0289 static const struct reset_control_ops at91_reset_ops = {
0290     .assert = at91_reset_assert,
0291     .deassert = at91_reset_deassert,
0292     .status = at91_reset_dev_status,
0293 };
0294
0295 static int at91_reset_of_xlate(struct reset_controller_dev *rcdev,
0296                    const struct of_phandle_args *reset_spec)
0297 {
0298     struct at91_reset *reset = to_at91_reset(rcdev);
0299
0300     if (!reset->data->n_device_reset ||
0301         (reset_spec->args[0] < reset->data->device_reset_min_id ||
0302          reset_spec->args[0] > reset->data->device_reset_max_id))
0303         return -EINVAL;
0304
0305     return reset_spec->args[0];
0306 }
0307
0308 static int at91_rcdev_init(struct at91_reset *reset,
0309                struct platform_device *pdev)
0310 {
0311     if (!reset->data->n_device_reset)
0312         return 0;
0313
0314     reset->dev_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 1,
0315                     NULL);
0316     if (IS_ERR(reset->dev_base))
0317         return -ENODEV;
0318
0319     spin_lock_init(&reset->lock);
0320     reset->rcdev.ops = &at91_reset_ops;
0321     reset->rcdev.owner = THIS_MODULE;
0322     reset->rcdev.of_node = pdev->dev.of_node;
0323     reset->rcdev.nr_resets = reset->data->n_device_reset;
0324     reset->rcdev.of_reset_n_cells = 1;
0325     reset->rcdev.of_xlate = at91_reset_of_xlate;
0326
0327     return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
0328 }
0329
0330 static int __init at91_reset_probe(struct platform_device *pdev)
0331 {
0332     const struct of_device_id *match;
0333     struct at91_reset *reset;
0334     struct device_node *np;
0335     int ret, idx = 0;
0336
0337     reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
0338     if (!reset)
0339         return -ENOMEM;
0340
0341     reset->rstc_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
0342     if (IS_ERR(reset->rstc_base)) {
0343         dev_err(&pdev->dev, "Could not map reset controller address\n");
0344         return -ENODEV;
0345     }
0346
0347     if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) {
0348         /* we need to shutdown the ddr controller, so get ramc base */
0349         for_each_matching_node_and_match(np, at91_ramc_of_match, &match) {
0350             reset->ramc_lpr = (u32)match->data;
0351             reset->ramc_base[idx] = devm_of_iomap(&pdev->dev, np, 0, NULL);
0352             if (IS_ERR(reset->ramc_base[idx])) {
0353                 dev_err(&pdev->dev, "Could not map ram controller address\n");
0354                 of_node_put(np);
0355                 return -ENODEV;
0356             }
0357             idx++;
0358         }
0359     }
0360
0361     reset->data = device_get_match_data(&pdev->dev);
0362     if (!reset->data)
0363         return -ENODEV;
0364
0365     reset->nb.notifier_call = at91_reset;
0366     reset->nb.priority = 192;
0367
0368     reset->sclk = devm_clk_get(&pdev->dev, NULL);
0369     if (IS_ERR(reset->sclk))
0370         return PTR_ERR(reset->sclk);
0371
0372     ret = clk_prepare_enable(reset->sclk);
0373     if (ret) {
0374         dev_err(&pdev->dev, "Could not enable slow clock\n");
0375         return ret;
0376     }
0377
0378     platform_set_drvdata(pdev, reset);
0379
0380     ret = at91_rcdev_init(reset, pdev);
0381     if (ret)
0382         goto disable_clk;
0383
0384     if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) {
0385         u32 val = readl(reset->rstc_base + AT91_RSTC_MR);
0386
0387         writel(AT91_RSTC_KEY | AT91_RSTC_URSTASYNC | val,
0388                reset->rstc_base + AT91_RSTC_MR);
0389     }
0390
0391     ret = register_restart_handler(&reset->nb);
0392     if (ret)
0393         goto disable_clk;
0394
0395     at91_reset_status(pdev, reset->rstc_base);
0396
0397     return 0;
0398
0399 disable_clk:
0400     clk_disable_unprepare(reset->sclk);
0401     return ret;
0402 }
0403
0404 static int __exit at91_reset_remove(struct platform_device *pdev)
0405 {
0406     struct at91_reset *reset = platform_get_drvdata(pdev);
0407
0408     unregister_restart_handler(&reset->nb);
0409     clk_disable_unprepare(reset->sclk);
0410
0411     return 0;
0412 }
0413
0414 static struct platform_driver at91_reset_driver = {
0415     .remove = __exit_p(at91_reset_remove),
0416     .driver = {
0417         .name = "at91-reset",
0418         .of_match_table = at91_reset_of_match,
0419     },
0420 };
0421 module_platform_driver_probe(at91_reset_driver, at91_reset_probe);
0422
0423 MODULE_AUTHOR("Atmel Corporation");
0424 MODULE_DESCRIPTION("Reset driver for Atmel SoCs");
0425 MODULE_LICENSE("GPL v2");