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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Intel Atom SOC Power Management Controller Driver
0004  * Copyright (c) 2014, Intel Corporation.
0005  */
0006 
0007 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0008 
0009 #include <linux/debugfs.h>
0010 #include <linux/device.h>
0011 #include <linux/dmi.h>
0012 #include <linux/init.h>
0013 #include <linux/io.h>
0014 #include <linux/platform_data/x86/clk-pmc-atom.h>
0015 #include <linux/platform_data/x86/pmc_atom.h>
0016 #include <linux/platform_data/x86/simatic-ipc.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pci.h>
0019 #include <linux/seq_file.h>
0020 
0021 struct pmc_bit_map {
0022     const char *name;
0023     u32 bit_mask;
0024 };
0025 
0026 struct pmc_reg_map {
0027     const struct pmc_bit_map *d3_sts_0;
0028     const struct pmc_bit_map *d3_sts_1;
0029     const struct pmc_bit_map *func_dis;
0030     const struct pmc_bit_map *func_dis_2;
0031     const struct pmc_bit_map *pss;
0032 };
0033 
0034 struct pmc_data {
0035     const struct pmc_reg_map *map;
0036     const struct pmc_clk *clks;
0037 };
0038 
0039 struct pmc_dev {
0040     u32 base_addr;
0041     void __iomem *regmap;
0042     const struct pmc_reg_map *map;
0043 #ifdef CONFIG_DEBUG_FS
0044     struct dentry *dbgfs_dir;
0045 #endif /* CONFIG_DEBUG_FS */
0046     bool init;
0047 };
0048 
0049 static struct pmc_dev pmc_device;
0050 static u32 acpi_base_addr;
0051 
0052 static const struct pmc_clk byt_clks[] = {
0053     {
0054         .name = "xtal",
0055         .freq = 25000000,
0056         .parent_name = NULL,
0057     },
0058     {
0059         .name = "pll",
0060         .freq = 19200000,
0061         .parent_name = "xtal",
0062     },
0063     {},
0064 };
0065 
0066 static const struct pmc_clk cht_clks[] = {
0067     {
0068         .name = "xtal",
0069         .freq = 19200000,
0070         .parent_name = NULL,
0071     },
0072     {},
0073 };
0074 
0075 static const struct pmc_bit_map d3_sts_0_map[] = {
0076     {"LPSS1_F0_DMA",    BIT_LPSS1_F0_DMA},
0077     {"LPSS1_F1_PWM1",   BIT_LPSS1_F1_PWM1},
0078     {"LPSS1_F2_PWM2",   BIT_LPSS1_F2_PWM2},
0079     {"LPSS1_F3_HSUART1",    BIT_LPSS1_F3_HSUART1},
0080     {"LPSS1_F4_HSUART2",    BIT_LPSS1_F4_HSUART2},
0081     {"LPSS1_F5_SPI",    BIT_LPSS1_F5_SPI},
0082     {"LPSS1_F6_Reserved",   BIT_LPSS1_F6_XXX},
0083     {"LPSS1_F7_Reserved",   BIT_LPSS1_F7_XXX},
0084     {"SCC_EMMC",        BIT_SCC_EMMC},
0085     {"SCC_SDIO",        BIT_SCC_SDIO},
0086     {"SCC_SDCARD",      BIT_SCC_SDCARD},
0087     {"SCC_MIPI",        BIT_SCC_MIPI},
0088     {"HDA",         BIT_HDA},
0089     {"LPE",         BIT_LPE},
0090     {"OTG",         BIT_OTG},
0091     {"USH",         BIT_USH},
0092     {"GBE",         BIT_GBE},
0093     {"SATA",        BIT_SATA},
0094     {"USB_EHCI",        BIT_USB_EHCI},
0095     {"SEC",         BIT_SEC},
0096     {"PCIE_PORT0",      BIT_PCIE_PORT0},
0097     {"PCIE_PORT1",      BIT_PCIE_PORT1},
0098     {"PCIE_PORT2",      BIT_PCIE_PORT2},
0099     {"PCIE_PORT3",      BIT_PCIE_PORT3},
0100     {"LPSS2_F0_DMA",    BIT_LPSS2_F0_DMA},
0101     {"LPSS2_F1_I2C1",   BIT_LPSS2_F1_I2C1},
0102     {"LPSS2_F2_I2C2",   BIT_LPSS2_F2_I2C2},
0103     {"LPSS2_F3_I2C3",   BIT_LPSS2_F3_I2C3},
0104     {"LPSS2_F3_I2C4",   BIT_LPSS2_F4_I2C4},
0105     {"LPSS2_F5_I2C5",   BIT_LPSS2_F5_I2C5},
0106     {"LPSS2_F6_I2C6",   BIT_LPSS2_F6_I2C6},
0107     {"LPSS2_F7_I2C7",   BIT_LPSS2_F7_I2C7},
0108     {},
0109 };
0110 
0111 static struct pmc_bit_map byt_d3_sts_1_map[] = {
0112     {"SMB",         BIT_SMB},
0113     {"OTG_SS_PHY",      BIT_OTG_SS_PHY},
0114     {"USH_SS_PHY",      BIT_USH_SS_PHY},
0115     {"DFX",         BIT_DFX},
0116     {},
0117 };
0118 
0119 static struct pmc_bit_map cht_d3_sts_1_map[] = {
0120     {"SMB",         BIT_SMB},
0121     {"GMM",         BIT_STS_GMM},
0122     {"ISH",         BIT_STS_ISH},
0123     {},
0124 };
0125 
0126 static struct pmc_bit_map cht_func_dis_2_map[] = {
0127     {"SMB",         BIT_SMB},
0128     {"GMM",         BIT_FD_GMM},
0129     {"ISH",         BIT_FD_ISH},
0130     {},
0131 };
0132 
0133 static const struct pmc_bit_map byt_pss_map[] = {
0134     {"GBE",         PMC_PSS_BIT_GBE},
0135     {"SATA",        PMC_PSS_BIT_SATA},
0136     {"HDA",         PMC_PSS_BIT_HDA},
0137     {"SEC",         PMC_PSS_BIT_SEC},
0138     {"PCIE",        PMC_PSS_BIT_PCIE},
0139     {"LPSS",        PMC_PSS_BIT_LPSS},
0140     {"LPE",         PMC_PSS_BIT_LPE},
0141     {"DFX",         PMC_PSS_BIT_DFX},
0142     {"USH_CTRL",        PMC_PSS_BIT_USH_CTRL},
0143     {"USH_SUS",     PMC_PSS_BIT_USH_SUS},
0144     {"USH_VCCS",        PMC_PSS_BIT_USH_VCCS},
0145     {"USH_VCCA",        PMC_PSS_BIT_USH_VCCA},
0146     {"OTG_CTRL",        PMC_PSS_BIT_OTG_CTRL},
0147     {"OTG_VCCS",        PMC_PSS_BIT_OTG_VCCS},
0148     {"OTG_VCCA_CLK",    PMC_PSS_BIT_OTG_VCCA_CLK},
0149     {"OTG_VCCA",        PMC_PSS_BIT_OTG_VCCA},
0150     {"USB",         PMC_PSS_BIT_USB},
0151     {"USB_SUS",     PMC_PSS_BIT_USB_SUS},
0152     {},
0153 };
0154 
0155 static const struct pmc_bit_map cht_pss_map[] = {
0156     {"SATA",        PMC_PSS_BIT_SATA},
0157     {"HDA",         PMC_PSS_BIT_HDA},
0158     {"SEC",         PMC_PSS_BIT_SEC},
0159     {"PCIE",        PMC_PSS_BIT_PCIE},
0160     {"LPSS",        PMC_PSS_BIT_LPSS},
0161     {"LPE",         PMC_PSS_BIT_LPE},
0162     {"UFS",         PMC_PSS_BIT_CHT_UFS},
0163     {"UXD",         PMC_PSS_BIT_CHT_UXD},
0164     {"UXD_FD",      PMC_PSS_BIT_CHT_UXD_FD},
0165     {"UX_ENG",      PMC_PSS_BIT_CHT_UX_ENG},
0166     {"USB_SUS",     PMC_PSS_BIT_CHT_USB_SUS},
0167     {"GMM",         PMC_PSS_BIT_CHT_GMM},
0168     {"ISH",         PMC_PSS_BIT_CHT_ISH},
0169     {"DFX_MASTER",      PMC_PSS_BIT_CHT_DFX_MASTER},
0170     {"DFX_CLUSTER1",    PMC_PSS_BIT_CHT_DFX_CLUSTER1},
0171     {"DFX_CLUSTER2",    PMC_PSS_BIT_CHT_DFX_CLUSTER2},
0172     {"DFX_CLUSTER3",    PMC_PSS_BIT_CHT_DFX_CLUSTER3},
0173     {"DFX_CLUSTER4",    PMC_PSS_BIT_CHT_DFX_CLUSTER4},
0174     {"DFX_CLUSTER5",    PMC_PSS_BIT_CHT_DFX_CLUSTER5},
0175     {},
0176 };
0177 
0178 static const struct pmc_reg_map byt_reg_map = {
0179     .d3_sts_0   = d3_sts_0_map,
0180     .d3_sts_1   = byt_d3_sts_1_map,
0181     .func_dis   = d3_sts_0_map,
0182     .func_dis_2 = byt_d3_sts_1_map,
0183     .pss        = byt_pss_map,
0184 };
0185 
0186 static const struct pmc_reg_map cht_reg_map = {
0187     .d3_sts_0   = d3_sts_0_map,
0188     .d3_sts_1   = cht_d3_sts_1_map,
0189     .func_dis   = d3_sts_0_map,
0190     .func_dis_2 = cht_func_dis_2_map,
0191     .pss        = cht_pss_map,
0192 };
0193 
0194 static const struct pmc_data byt_data = {
0195     .map = &byt_reg_map,
0196     .clks = byt_clks,
0197 };
0198 
0199 static const struct pmc_data cht_data = {
0200     .map = &cht_reg_map,
0201     .clks = cht_clks,
0202 };
0203 
0204 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
0205 {
0206     return readl(pmc->regmap + reg_offset);
0207 }
0208 
0209 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
0210 {
0211     writel(val, pmc->regmap + reg_offset);
0212 }
0213 
0214 int pmc_atom_read(int offset, u32 *value)
0215 {
0216     struct pmc_dev *pmc = &pmc_device;
0217 
0218     if (!pmc->init)
0219         return -ENODEV;
0220 
0221     *value = pmc_reg_read(pmc, offset);
0222     return 0;
0223 }
0224 
0225 static void pmc_power_off(void)
0226 {
0227     u16 pm1_cnt_port;
0228     u32 pm1_cnt_value;
0229 
0230     pr_info("Preparing to enter system sleep state S5\n");
0231 
0232     pm1_cnt_port = acpi_base_addr + PM1_CNT;
0233 
0234     pm1_cnt_value = inl(pm1_cnt_port);
0235     pm1_cnt_value &= ~SLEEP_TYPE_MASK;
0236     pm1_cnt_value |= SLEEP_TYPE_S5;
0237     pm1_cnt_value |= SLEEP_ENABLE;
0238 
0239     outl(pm1_cnt_value, pm1_cnt_port);
0240 }
0241 
0242 static void pmc_hw_reg_setup(struct pmc_dev *pmc)
0243 {
0244     /*
0245      * Disable PMC S0IX_WAKE_EN events coming from:
0246      * - LPC clock run
0247      * - GPIO_SUS ored dedicated IRQs
0248      * - GPIO_SCORE ored dedicated IRQs
0249      * - GPIO_SUS shared IRQ
0250      * - GPIO_SCORE shared IRQ
0251      */
0252     pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
0253 }
0254 
0255 #ifdef CONFIG_DEBUG_FS
0256 static void pmc_dev_state_print(struct seq_file *s, int reg_index,
0257                 u32 sts, const struct pmc_bit_map *sts_map,
0258                 u32 fd, const struct pmc_bit_map *fd_map)
0259 {
0260     int offset = PMC_REG_BIT_WIDTH * reg_index;
0261     int index;
0262 
0263     for (index = 0; sts_map[index].name; index++) {
0264         seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
0265             offset + index, sts_map[index].name,
0266             fd_map[index].bit_mask & fd ?  "Disabled" : "Enabled ",
0267             sts_map[index].bit_mask & sts ?  "D3" : "D0");
0268     }
0269 }
0270 
0271 static int pmc_dev_state_show(struct seq_file *s, void *unused)
0272 {
0273     struct pmc_dev *pmc = s->private;
0274     const struct pmc_reg_map *m = pmc->map;
0275     u32 func_dis, func_dis_2;
0276     u32 d3_sts_0, d3_sts_1;
0277 
0278     func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
0279     func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
0280     d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
0281     d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
0282 
0283     /* Low part */
0284     pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
0285 
0286     /* High part */
0287     pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
0288 
0289     return 0;
0290 }
0291 
0292 DEFINE_SHOW_ATTRIBUTE(pmc_dev_state);
0293 
0294 static int pmc_pss_state_show(struct seq_file *s, void *unused)
0295 {
0296     struct pmc_dev *pmc = s->private;
0297     const struct pmc_bit_map *map = pmc->map->pss;
0298     u32 pss = pmc_reg_read(pmc, PMC_PSS);
0299     int index;
0300 
0301     for (index = 0; map[index].name; index++) {
0302         seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
0303             index, map[index].name,
0304             map[index].bit_mask & pss ? "Off" : "On");
0305     }
0306     return 0;
0307 }
0308 
0309 DEFINE_SHOW_ATTRIBUTE(pmc_pss_state);
0310 
0311 static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
0312 {
0313     struct pmc_dev *pmc = s->private;
0314     u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
0315 
0316     s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
0317     s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
0318     s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
0319     s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
0320     s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
0321 
0322     seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
0323     seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
0324     seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
0325     seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
0326     seq_printf(s, "S0   Residency:\t%lldus\n", s0_tmr);
0327     return 0;
0328 }
0329 
0330 DEFINE_SHOW_ATTRIBUTE(pmc_sleep_tmr);
0331 
0332 static void pmc_dbgfs_register(struct pmc_dev *pmc)
0333 {
0334     struct dentry *dir;
0335 
0336     dir = debugfs_create_dir("pmc_atom", NULL);
0337 
0338     pmc->dbgfs_dir = dir;
0339 
0340     debugfs_create_file("dev_state", S_IFREG | S_IRUGO, dir, pmc,
0341                 &pmc_dev_state_fops);
0342     debugfs_create_file("pss_state", S_IFREG | S_IRUGO, dir, pmc,
0343                 &pmc_pss_state_fops);
0344     debugfs_create_file("sleep_state", S_IFREG | S_IRUGO, dir, pmc,
0345                 &pmc_sleep_tmr_fops);
0346 }
0347 #else
0348 static void pmc_dbgfs_register(struct pmc_dev *pmc)
0349 {
0350 }
0351 #endif /* CONFIG_DEBUG_FS */
0352 
0353 static bool pmc_clk_is_critical = true;
0354 
0355 static int dmi_callback(const struct dmi_system_id *d)
0356 {
0357     pr_info("%s critclks quirk enabled\n", d->ident);
0358 
0359     return 1;
0360 }
0361 
0362 static int dmi_callback_siemens(const struct dmi_system_id *d)
0363 {
0364     u32 st_id;
0365 
0366     if (dmi_walk(simatic_ipc_find_dmi_entry_helper, &st_id))
0367         goto out;
0368 
0369     if (st_id == SIMATIC_IPC_IPC227E || st_id == SIMATIC_IPC_IPC277E)
0370         return dmi_callback(d);
0371 
0372 out:
0373     pmc_clk_is_critical = false;
0374     return 1;
0375 }
0376 
0377 /*
0378  * Some systems need one or more of their pmc_plt_clks to be
0379  * marked as critical.
0380  */
0381 static const struct dmi_system_id critclk_systems[] = {
0382     {
0383         /* pmc_plt_clk0 is used for an external HSIC USB HUB */
0384         .ident = "MPL CEC1x",
0385         .callback = dmi_callback,
0386         .matches = {
0387             DMI_MATCH(DMI_SYS_VENDOR, "MPL AG"),
0388             DMI_MATCH(DMI_PRODUCT_NAME, "CEC10 Family"),
0389         },
0390     },
0391     {
0392         /*
0393          * Lex System / Lex Computech Co. makes a lot of Bay Trail
0394          * based embedded boards which often come with multiple
0395          * ethernet controllers using multiple pmc_plt_clks. See:
0396          * https://www.lex.com.tw/products/embedded-ipc-board/
0397          */
0398         .ident = "Lex BayTrail",
0399         .callback = dmi_callback,
0400         .matches = {
0401             DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
0402         },
0403     },
0404     {
0405         /* pmc_plt_clk* - are used for ethernet controllers */
0406         .ident = "Beckhoff Baytrail",
0407         .callback = dmi_callback,
0408         .matches = {
0409             DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"),
0410             DMI_MATCH(DMI_PRODUCT_FAMILY, "CBxx63"),
0411         },
0412     },
0413     {
0414         .ident = "SIEMENS AG",
0415         .callback = dmi_callback_siemens,
0416         .matches = {
0417             DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
0418         },
0419     },
0420 
0421     { /*sentinel*/ }
0422 };
0423 
0424 static int pmc_setup_clks(struct pci_dev *pdev, void __iomem *pmc_regmap,
0425               const struct pmc_data *pmc_data)
0426 {
0427     struct platform_device *clkdev;
0428     struct pmc_clk_data *clk_data;
0429 
0430     clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
0431     if (!clk_data)
0432         return -ENOMEM;
0433 
0434     clk_data->base = pmc_regmap; /* offset is added by client */
0435     clk_data->clks = pmc_data->clks;
0436     if (dmi_check_system(critclk_systems))
0437         clk_data->critical = pmc_clk_is_critical;
0438 
0439     clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom",
0440                            PLATFORM_DEVID_NONE,
0441                            clk_data, sizeof(*clk_data));
0442     if (IS_ERR(clkdev)) {
0443         kfree(clk_data);
0444         return PTR_ERR(clkdev);
0445     }
0446 
0447     kfree(clk_data);
0448 
0449     return 0;
0450 }
0451 
0452 static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
0453 {
0454     struct pmc_dev *pmc = &pmc_device;
0455     const struct pmc_data *data = (struct pmc_data *)ent->driver_data;
0456     const struct pmc_reg_map *map = data->map;
0457     int ret;
0458 
0459     /* Obtain ACPI base address */
0460     pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
0461     acpi_base_addr &= ACPI_BASE_ADDR_MASK;
0462 
0463     /* Install power off function */
0464     if (acpi_base_addr != 0 && pm_power_off == NULL)
0465         pm_power_off = pmc_power_off;
0466 
0467     pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
0468     pmc->base_addr &= PMC_BASE_ADDR_MASK;
0469 
0470     pmc->regmap = ioremap(pmc->base_addr, PMC_MMIO_REG_LEN);
0471     if (!pmc->regmap) {
0472         dev_err(&pdev->dev, "error: ioremap failed\n");
0473         return -ENOMEM;
0474     }
0475 
0476     pmc->map = map;
0477 
0478     /* PMC hardware registers setup */
0479     pmc_hw_reg_setup(pmc);
0480 
0481     pmc_dbgfs_register(pmc);
0482 
0483     /* Register platform clocks - PMC_PLT_CLK [0..5] */
0484     ret = pmc_setup_clks(pdev, pmc->regmap, data);
0485     if (ret)
0486         dev_warn(&pdev->dev, "platform clocks register failed: %d\n",
0487              ret);
0488 
0489     pmc->init = true;
0490     return ret;
0491 }
0492 
0493 /*
0494  * Data for PCI driver interface
0495  *
0496  * used by pci_match_id() call below.
0497  */
0498 static const struct pci_device_id pmc_pci_ids[] = {
0499     { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_data },
0500     { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_data },
0501     { 0, },
0502 };
0503 
0504 static int __init pmc_atom_init(void)
0505 {
0506     struct pci_dev *pdev = NULL;
0507     const struct pci_device_id *ent;
0508 
0509     /* We look for our device - PCU PMC
0510      * we assume that there is max. one device.
0511      *
0512      * We can't use plain pci_driver mechanism,
0513      * as the device is really a multiple function device,
0514      * main driver that binds to the pci_device is lpc_ich
0515      * and have to find & bind to the device this way.
0516      */
0517     for_each_pci_dev(pdev) {
0518         ent = pci_match_id(pmc_pci_ids, pdev);
0519         if (ent)
0520             return pmc_setup_dev(pdev, ent);
0521     }
0522     /* Device not found. */
0523     return -ENODEV;
0524 }
0525 
0526 device_initcall(pmc_atom_init);
0527 
0528 /*
0529 MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
0530 MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
0531 MODULE_LICENSE("GPL v2");
0532 */
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