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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel Core SoC Power Management Controller Driver
0004  *
0005  * Copyright (c) 2016, Intel Corporation.
0006  * All Rights Reserved.
0007  *
0008  * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
0009  *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
0010  */
0011 
0012 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0013 
0014 #include <linux/acpi.h>
0015 #include <linux/bitfield.h>
0016 #include <linux/debugfs.h>
0017 #include <linux/delay.h>
0018 #include <linux/dmi.h>
0019 #include <linux/io.h>
0020 #include <linux/module.h>
0021 #include <linux/pci.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/slab.h>
0024 #include <linux/suspend.h>
0025 #include <linux/uaccess.h>
0026 #include <linux/uuid.h>
0027 
0028 #include <acpi/acpi_bus.h>
0029 #include <asm/cpu_device_id.h>
0030 #include <asm/intel-family.h>
0031 #include <asm/msr.h>
0032 #include <asm/tsc.h>
0033 
0034 #include "core.h"
0035 
0036 #define ACPI_S0IX_DSM_UUID      "57a6512e-3979-4e9d-9708-ff13b2508972"
0037 #define ACPI_GET_LOW_MODE_REGISTERS 1
0038 
0039 /* PKGC MSRs are common across Intel Core SoCs */
0040 static const struct pmc_bit_map msr_map[] = {
0041     {"Package C2",                  MSR_PKG_C2_RESIDENCY},
0042     {"Package C3",                  MSR_PKG_C3_RESIDENCY},
0043     {"Package C6",                  MSR_PKG_C6_RESIDENCY},
0044     {"Package C7",                  MSR_PKG_C7_RESIDENCY},
0045     {"Package C8",                  MSR_PKG_C8_RESIDENCY},
0046     {"Package C9",                  MSR_PKG_C9_RESIDENCY},
0047     {"Package C10",                 MSR_PKG_C10_RESIDENCY},
0048     {}
0049 };
0050 
0051 static const struct pmc_bit_map spt_pll_map[] = {
0052     {"MIPI PLL",            SPT_PMC_BIT_MPHY_CMN_LANE0},
0053     {"GEN2 USB2PCIE2 PLL",      SPT_PMC_BIT_MPHY_CMN_LANE1},
0054     {"DMIPCIE3 PLL",        SPT_PMC_BIT_MPHY_CMN_LANE2},
0055     {"SATA PLL",            SPT_PMC_BIT_MPHY_CMN_LANE3},
0056     {}
0057 };
0058 
0059 static const struct pmc_bit_map spt_mphy_map[] = {
0060     {"MPHY CORE LANE 0",           SPT_PMC_BIT_MPHY_LANE0},
0061     {"MPHY CORE LANE 1",           SPT_PMC_BIT_MPHY_LANE1},
0062     {"MPHY CORE LANE 2",           SPT_PMC_BIT_MPHY_LANE2},
0063     {"MPHY CORE LANE 3",           SPT_PMC_BIT_MPHY_LANE3},
0064     {"MPHY CORE LANE 4",           SPT_PMC_BIT_MPHY_LANE4},
0065     {"MPHY CORE LANE 5",           SPT_PMC_BIT_MPHY_LANE5},
0066     {"MPHY CORE LANE 6",           SPT_PMC_BIT_MPHY_LANE6},
0067     {"MPHY CORE LANE 7",           SPT_PMC_BIT_MPHY_LANE7},
0068     {"MPHY CORE LANE 8",           SPT_PMC_BIT_MPHY_LANE8},
0069     {"MPHY CORE LANE 9",           SPT_PMC_BIT_MPHY_LANE9},
0070     {"MPHY CORE LANE 10",          SPT_PMC_BIT_MPHY_LANE10},
0071     {"MPHY CORE LANE 11",          SPT_PMC_BIT_MPHY_LANE11},
0072     {"MPHY CORE LANE 12",          SPT_PMC_BIT_MPHY_LANE12},
0073     {"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
0074     {"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
0075     {"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
0076     {}
0077 };
0078 
0079 static const struct pmc_bit_map spt_pfear_map[] = {
0080     {"PMC",             SPT_PMC_BIT_PMC},
0081     {"OPI-DMI",         SPT_PMC_BIT_OPI},
0082     {"SPI / eSPI",          SPT_PMC_BIT_SPI},
0083     {"XHCI",            SPT_PMC_BIT_XHCI},
0084     {"SPA",             SPT_PMC_BIT_SPA},
0085     {"SPB",             SPT_PMC_BIT_SPB},
0086     {"SPC",             SPT_PMC_BIT_SPC},
0087     {"GBE",             SPT_PMC_BIT_GBE},
0088     {"SATA",            SPT_PMC_BIT_SATA},
0089     {"HDA-PGD0",            SPT_PMC_BIT_HDA_PGD0},
0090     {"HDA-PGD1",            SPT_PMC_BIT_HDA_PGD1},
0091     {"HDA-PGD2",            SPT_PMC_BIT_HDA_PGD2},
0092     {"HDA-PGD3",            SPT_PMC_BIT_HDA_PGD3},
0093     {"RSVD",            SPT_PMC_BIT_RSVD_0B},
0094     {"LPSS",            SPT_PMC_BIT_LPSS},
0095     {"LPC",             SPT_PMC_BIT_LPC},
0096     {"SMB",             SPT_PMC_BIT_SMB},
0097     {"ISH",             SPT_PMC_BIT_ISH},
0098     {"P2SB",            SPT_PMC_BIT_P2SB},
0099     {"DFX",             SPT_PMC_BIT_DFX},
0100     {"SCC",             SPT_PMC_BIT_SCC},
0101     {"RSVD",            SPT_PMC_BIT_RSVD_0C},
0102     {"FUSE",            SPT_PMC_BIT_FUSE},
0103     {"CAMERA",          SPT_PMC_BIT_CAMREA},
0104     {"RSVD",            SPT_PMC_BIT_RSVD_0D},
0105     {"USB3-OTG",            SPT_PMC_BIT_USB3_OTG},
0106     {"EXI",             SPT_PMC_BIT_EXI},
0107     {"CSE",             SPT_PMC_BIT_CSE},
0108     {"CSME_KVM",            SPT_PMC_BIT_CSME_KVM},
0109     {"CSME_PMT",            SPT_PMC_BIT_CSME_PMT},
0110     {"CSME_CLINK",          SPT_PMC_BIT_CSME_CLINK},
0111     {"CSME_PTIO",           SPT_PMC_BIT_CSME_PTIO},
0112     {"CSME_USBR",           SPT_PMC_BIT_CSME_USBR},
0113     {"CSME_SUSRAM",         SPT_PMC_BIT_CSME_SUSRAM},
0114     {"CSME_SMT",            SPT_PMC_BIT_CSME_SMT},
0115     {"RSVD",            SPT_PMC_BIT_RSVD_1A},
0116     {"CSME_SMS2",           SPT_PMC_BIT_CSME_SMS2},
0117     {"CSME_SMS1",           SPT_PMC_BIT_CSME_SMS1},
0118     {"CSME_RTC",            SPT_PMC_BIT_CSME_RTC},
0119     {"CSME_PSF",            SPT_PMC_BIT_CSME_PSF},
0120     {}
0121 };
0122 
0123 static const struct pmc_bit_map *ext_spt_pfear_map[] = {
0124     /*
0125      * Check intel_pmc_core_ids[] users of spt_reg_map for
0126      * a list of core SoCs using this.
0127      */
0128     spt_pfear_map,
0129     NULL
0130 };
0131 
0132 static const struct pmc_bit_map spt_ltr_show_map[] = {
0133     {"SOUTHPORT_A",     SPT_PMC_LTR_SPA},
0134     {"SOUTHPORT_B",     SPT_PMC_LTR_SPB},
0135     {"SATA",        SPT_PMC_LTR_SATA},
0136     {"GIGABIT_ETHERNET",    SPT_PMC_LTR_GBE},
0137     {"XHCI",        SPT_PMC_LTR_XHCI},
0138     {"Reserved",        SPT_PMC_LTR_RESERVED},
0139     {"ME",          SPT_PMC_LTR_ME},
0140     /* EVA is Enterprise Value Add, doesn't really exist on PCH */
0141     {"EVA",         SPT_PMC_LTR_EVA},
0142     {"SOUTHPORT_C",     SPT_PMC_LTR_SPC},
0143     {"HD_AUDIO",        SPT_PMC_LTR_AZ},
0144     {"LPSS",        SPT_PMC_LTR_LPSS},
0145     {"SOUTHPORT_D",     SPT_PMC_LTR_SPD},
0146     {"SOUTHPORT_E",     SPT_PMC_LTR_SPE},
0147     {"CAMERA",      SPT_PMC_LTR_CAM},
0148     {"ESPI",        SPT_PMC_LTR_ESPI},
0149     {"SCC",         SPT_PMC_LTR_SCC},
0150     {"ISH",         SPT_PMC_LTR_ISH},
0151     /* Below two cannot be used for LTR_IGNORE */
0152     {"CURRENT_PLATFORM",    SPT_PMC_LTR_CUR_PLT},
0153     {"AGGREGATED_SYSTEM",   SPT_PMC_LTR_CUR_ASLT},
0154     {}
0155 };
0156 
0157 static const struct pmc_reg_map spt_reg_map = {
0158     .pfear_sts = ext_spt_pfear_map,
0159     .mphy_sts = spt_mphy_map,
0160     .pll_sts = spt_pll_map,
0161     .ltr_show_sts = spt_ltr_show_map,
0162     .msr_sts = msr_map,
0163     .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
0164     .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
0165     .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
0166     .regmap_length = SPT_PMC_MMIO_REG_LEN,
0167     .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
0168     .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
0169     .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
0170     .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
0171     .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
0172     .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
0173 };
0174 
0175 /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
0176 static const struct pmc_bit_map cnp_pfear_map[] = {
0177     {"PMC",                 BIT(0)},
0178     {"OPI-DMI",             BIT(1)},
0179     {"SPI/eSPI",            BIT(2)},
0180     {"XHCI",                BIT(3)},
0181     {"SPA",                 BIT(4)},
0182     {"SPB",                 BIT(5)},
0183     {"SPC",                 BIT(6)},
0184     {"GBE",                 BIT(7)},
0185 
0186     {"SATA",                BIT(0)},
0187     {"HDA_PGD0",            BIT(1)},
0188     {"HDA_PGD1",            BIT(2)},
0189     {"HDA_PGD2",            BIT(3)},
0190     {"HDA_PGD3",            BIT(4)},
0191     {"SPD",                 BIT(5)},
0192     {"LPSS",                BIT(6)},
0193     {"LPC",                 BIT(7)},
0194 
0195     {"SMB",                 BIT(0)},
0196     {"ISH",                 BIT(1)},
0197     {"P2SB",                BIT(2)},
0198     {"NPK_VNN",             BIT(3)},
0199     {"SDX",                 BIT(4)},
0200     {"SPE",                 BIT(5)},
0201     {"Fuse",                BIT(6)},
0202     {"SBR8",        BIT(7)},
0203 
0204     {"CSME_FSC",            BIT(0)},
0205     {"USB3_OTG",            BIT(1)},
0206     {"EXI",                 BIT(2)},
0207     {"CSE",                 BIT(3)},
0208     {"CSME_KVM",            BIT(4)},
0209     {"CSME_PMT",            BIT(5)},
0210     {"CSME_CLINK",          BIT(6)},
0211     {"CSME_PTIO",           BIT(7)},
0212 
0213     {"CSME_USBR",           BIT(0)},
0214     {"CSME_SUSRAM",         BIT(1)},
0215     {"CSME_SMT1",           BIT(2)},
0216     {"CSME_SMT4",           BIT(3)},
0217     {"CSME_SMS2",           BIT(4)},
0218     {"CSME_SMS1",           BIT(5)},
0219     {"CSME_RTC",            BIT(6)},
0220     {"CSME_PSF",            BIT(7)},
0221 
0222     {"SBR0",                BIT(0)},
0223     {"SBR1",                BIT(1)},
0224     {"SBR2",                BIT(2)},
0225     {"SBR3",                BIT(3)},
0226     {"SBR4",                BIT(4)},
0227     {"SBR5",                BIT(5)},
0228     {"CSME_PECI",           BIT(6)},
0229     {"PSF1",                BIT(7)},
0230 
0231     {"PSF2",                BIT(0)},
0232     {"PSF3",                BIT(1)},
0233     {"PSF4",                BIT(2)},
0234     {"CNVI",                BIT(3)},
0235     {"UFS0",                BIT(4)},
0236     {"EMMC",                BIT(5)},
0237     {"SPF",         BIT(6)},
0238     {"SBR6",                BIT(7)},
0239 
0240     {"SBR7",                BIT(0)},
0241     {"NPK_AON",             BIT(1)},
0242     {"HDA_PGD4",            BIT(2)},
0243     {"HDA_PGD5",            BIT(3)},
0244     {"HDA_PGD6",            BIT(4)},
0245     {"PSF6",        BIT(5)},
0246     {"PSF7",        BIT(6)},
0247     {"PSF8",        BIT(7)},
0248     {}
0249 };
0250 
0251 static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
0252     /*
0253      * Check intel_pmc_core_ids[] users of cnp_reg_map for
0254      * a list of core SoCs using this.
0255      */
0256     cnp_pfear_map,
0257     NULL
0258 };
0259 
0260 static const struct pmc_bit_map icl_pfear_map[] = {
0261     {"RES_65",      BIT(0)},
0262     {"RES_66",      BIT(1)},
0263     {"RES_67",      BIT(2)},
0264     {"TAM",         BIT(3)},
0265     {"GBETSN",      BIT(4)},
0266     {"TBTLSX",      BIT(5)},
0267     {"RES_71",      BIT(6)},
0268     {"RES_72",      BIT(7)},
0269     {}
0270 };
0271 
0272 static const struct pmc_bit_map *ext_icl_pfear_map[] = {
0273     /*
0274      * Check intel_pmc_core_ids[] users of icl_reg_map for
0275      * a list of core SoCs using this.
0276      */
0277     cnp_pfear_map,
0278     icl_pfear_map,
0279     NULL
0280 };
0281 
0282 static const struct pmc_bit_map tgl_pfear_map[] = {
0283     {"PSF9",        BIT(0)},
0284     {"RES_66",      BIT(1)},
0285     {"RES_67",      BIT(2)},
0286     {"RES_68",      BIT(3)},
0287     {"RES_69",      BIT(4)},
0288     {"RES_70",      BIT(5)},
0289     {"TBTLSX",      BIT(6)},
0290     {}
0291 };
0292 
0293 static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
0294     /*
0295      * Check intel_pmc_core_ids[] users of tgl_reg_map for
0296      * a list of core SoCs using this.
0297      */
0298     cnp_pfear_map,
0299     tgl_pfear_map,
0300     NULL
0301 };
0302 
0303 static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
0304     {"AUDIO_D3",        BIT(0)},
0305     {"OTG_D3",      BIT(1)},
0306     {"XHCI_D3",     BIT(2)},
0307     {"LPIO_D3",     BIT(3)},
0308     {"SDX_D3",      BIT(4)},
0309     {"SATA_D3",     BIT(5)},
0310     {"UFS0_D3",     BIT(6)},
0311     {"UFS1_D3",     BIT(7)},
0312     {"EMMC_D3",     BIT(8)},
0313     {}
0314 };
0315 
0316 static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
0317     {"SDIO_PLL_OFF",    BIT(0)},
0318     {"USB2_PLL_OFF",    BIT(1)},
0319     {"AUDIO_PLL_OFF",   BIT(2)},
0320     {"OC_PLL_OFF",      BIT(3)},
0321     {"MAIN_PLL_OFF",    BIT(4)},
0322     {"XOSC_OFF",        BIT(5)},
0323     {"LPC_CLKS_GATED",  BIT(6)},
0324     {"PCIE_CLKREQS_IDLE",   BIT(7)},
0325     {"AUDIO_ROSC_OFF",  BIT(8)},
0326     {"HPET_XOSC_CLK_REQ",   BIT(9)},
0327     {"PMC_ROSC_SLOW_CLK",   BIT(10)},
0328     {"AON2_ROSC_GATED", BIT(11)},
0329     {"CLKACKS_DEASSERTED",  BIT(12)},
0330     {}
0331 };
0332 
0333 static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
0334     {"MPHY_CORE_GATED", BIT(0)},
0335     {"CSME_GATED",      BIT(1)},
0336     {"USB2_SUS_GATED",  BIT(2)},
0337     {"DYN_FLEX_IO_IDLE",    BIT(3)},
0338     {"GBE_NO_LINK",     BIT(4)},
0339     {"THERM_SEN_DISABLED",  BIT(5)},
0340     {"PCIE_LOW_POWER",  BIT(6)},
0341     {"ISH_VNNAON_REQ_ACT",  BIT(7)},
0342     {"ISH_VNN_REQ_ACT", BIT(8)},
0343     {"CNV_VNNAON_REQ_ACT",  BIT(9)},
0344     {"CNV_VNN_REQ_ACT", BIT(10)},
0345     {"NPK_VNNON_REQ_ACT",   BIT(11)},
0346     {"PMSYNC_STATE_IDLE",   BIT(12)},
0347     {"ALST_GT_THRES",   BIT(13)},
0348     {"PMC_ARC_PG_READY",    BIT(14)},
0349     {}
0350 };
0351 
0352 static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
0353     cnp_slps0_dbg0_map,
0354     cnp_slps0_dbg1_map,
0355     cnp_slps0_dbg2_map,
0356     NULL
0357 };
0358 
0359 static const struct pmc_bit_map cnp_ltr_show_map[] = {
0360     {"SOUTHPORT_A",     CNP_PMC_LTR_SPA},
0361     {"SOUTHPORT_B",     CNP_PMC_LTR_SPB},
0362     {"SATA",        CNP_PMC_LTR_SATA},
0363     {"GIGABIT_ETHERNET",    CNP_PMC_LTR_GBE},
0364     {"XHCI",        CNP_PMC_LTR_XHCI},
0365     {"Reserved",        CNP_PMC_LTR_RESERVED},
0366     {"ME",          CNP_PMC_LTR_ME},
0367     /* EVA is Enterprise Value Add, doesn't really exist on PCH */
0368     {"EVA",         CNP_PMC_LTR_EVA},
0369     {"SOUTHPORT_C",     CNP_PMC_LTR_SPC},
0370     {"HD_AUDIO",        CNP_PMC_LTR_AZ},
0371     {"CNV",         CNP_PMC_LTR_CNV},
0372     {"LPSS",        CNP_PMC_LTR_LPSS},
0373     {"SOUTHPORT_D",     CNP_PMC_LTR_SPD},
0374     {"SOUTHPORT_E",     CNP_PMC_LTR_SPE},
0375     {"CAMERA",      CNP_PMC_LTR_CAM},
0376     {"ESPI",        CNP_PMC_LTR_ESPI},
0377     {"SCC",         CNP_PMC_LTR_SCC},
0378     {"ISH",         CNP_PMC_LTR_ISH},
0379     {"UFSX2",       CNP_PMC_LTR_UFSX2},
0380     {"EMMC",        CNP_PMC_LTR_EMMC},
0381     /*
0382      * Check intel_pmc_core_ids[] users of cnp_reg_map for
0383      * a list of core SoCs using this.
0384      */
0385     {"WIGIG",       ICL_PMC_LTR_WIGIG},
0386     {"THC0",                TGL_PMC_LTR_THC0},
0387     {"THC1",                TGL_PMC_LTR_THC1},
0388     /* Below two cannot be used for LTR_IGNORE */
0389     {"CURRENT_PLATFORM",    CNP_PMC_LTR_CUR_PLT},
0390     {"AGGREGATED_SYSTEM",   CNP_PMC_LTR_CUR_ASLT},
0391     {}
0392 };
0393 
0394 static const struct pmc_reg_map cnp_reg_map = {
0395     .pfear_sts = ext_cnp_pfear_map,
0396     .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
0397     .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
0398     .slps0_dbg_maps = cnp_slps0_dbg_maps,
0399     .ltr_show_sts = cnp_ltr_show_map,
0400     .msr_sts = msr_map,
0401     .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
0402     .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
0403     .regmap_length = CNP_PMC_MMIO_REG_LEN,
0404     .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
0405     .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
0406     .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
0407     .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
0408     .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
0409     .etr3_offset = ETR3_OFFSET,
0410 };
0411 
0412 static const struct pmc_reg_map icl_reg_map = {
0413     .pfear_sts = ext_icl_pfear_map,
0414     .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
0415     .slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
0416     .slps0_dbg_maps = cnp_slps0_dbg_maps,
0417     .ltr_show_sts = cnp_ltr_show_map,
0418     .msr_sts = msr_map,
0419     .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
0420     .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
0421     .regmap_length = CNP_PMC_MMIO_REG_LEN,
0422     .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
0423     .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
0424     .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
0425     .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
0426     .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
0427     .etr3_offset = ETR3_OFFSET,
0428 };
0429 
0430 static const struct pmc_bit_map tgl_clocksource_status_map[] = {
0431     {"USB2PLL_OFF_STS",         BIT(18)},
0432     {"PCIe/USB3.1_Gen2PLL_OFF_STS",     BIT(19)},
0433     {"PCIe_Gen3PLL_OFF_STS",        BIT(20)},
0434     {"OPIOPLL_OFF_STS",         BIT(21)},
0435     {"OCPLL_OFF_STS",           BIT(22)},
0436     {"MainPLL_OFF_STS",         BIT(23)},
0437     {"MIPIPLL_OFF_STS",         BIT(24)},
0438     {"Fast_XTAL_Osc_OFF_STS",       BIT(25)},
0439     {"AC_Ring_Osc_OFF_STS",         BIT(26)},
0440     {"MC_Ring_Osc_OFF_STS",         BIT(27)},
0441     {"SATAPLL_OFF_STS",         BIT(29)},
0442     {"XTAL_USB2PLL_OFF_STS",        BIT(31)},
0443     {}
0444 };
0445 
0446 static const struct pmc_bit_map tgl_power_gating_status_map[] = {
0447     {"CSME_PG_STS",             BIT(0)},
0448     {"SATA_PG_STS",             BIT(1)},
0449     {"xHCI_PG_STS",             BIT(2)},
0450     {"UFSX2_PG_STS",            BIT(3)},
0451     {"OTG_PG_STS",              BIT(5)},
0452     {"SPA_PG_STS",              BIT(6)},
0453     {"SPB_PG_STS",              BIT(7)},
0454     {"SPC_PG_STS",              BIT(8)},
0455     {"SPD_PG_STS",              BIT(9)},
0456     {"SPE_PG_STS",              BIT(10)},
0457     {"SPF_PG_STS",              BIT(11)},
0458     {"LSX_PG_STS",              BIT(13)},
0459     {"P2SB_PG_STS",             BIT(14)},
0460     {"PSF_PG_STS",              BIT(15)},
0461     {"SBR_PG_STS",              BIT(16)},
0462     {"OPIDMI_PG_STS",           BIT(17)},
0463     {"THC0_PG_STS",             BIT(18)},
0464     {"THC1_PG_STS",             BIT(19)},
0465     {"GBETSN_PG_STS",           BIT(20)},
0466     {"GBE_PG_STS",              BIT(21)},
0467     {"LPSS_PG_STS",             BIT(22)},
0468     {"MMP_UFSX2_PG_STS",            BIT(23)},
0469     {"MMP_UFSX2B_PG_STS",           BIT(24)},
0470     {"FIA_PG_STS",              BIT(25)},
0471     {}
0472 };
0473 
0474 static const struct pmc_bit_map tgl_d3_status_map[] = {
0475     {"ADSP_D3_STS",             BIT(0)},
0476     {"SATA_D3_STS",             BIT(1)},
0477     {"xHCI0_D3_STS",            BIT(2)},
0478     {"xDCI1_D3_STS",            BIT(5)},
0479     {"SDX_D3_STS",              BIT(6)},
0480     {"EMMC_D3_STS",             BIT(7)},
0481     {"IS_D3_STS",               BIT(8)},
0482     {"THC0_D3_STS",             BIT(9)},
0483     {"THC1_D3_STS",             BIT(10)},
0484     {"GBE_D3_STS",              BIT(11)},
0485     {"GBE_TSN_D3_STS",          BIT(12)},
0486     {}
0487 };
0488 
0489 static const struct pmc_bit_map tgl_vnn_req_status_map[] = {
0490     {"GPIO_COM0_VNN_REQ_STS",       BIT(1)},
0491     {"GPIO_COM1_VNN_REQ_STS",       BIT(2)},
0492     {"GPIO_COM2_VNN_REQ_STS",       BIT(3)},
0493     {"GPIO_COM3_VNN_REQ_STS",       BIT(4)},
0494     {"GPIO_COM4_VNN_REQ_STS",       BIT(5)},
0495     {"GPIO_COM5_VNN_REQ_STS",       BIT(6)},
0496     {"Audio_VNN_REQ_STS",           BIT(7)},
0497     {"ISH_VNN_REQ_STS",         BIT(8)},
0498     {"CNVI_VNN_REQ_STS",            BIT(9)},
0499     {"eSPI_VNN_REQ_STS",            BIT(10)},
0500     {"Display_VNN_REQ_STS",         BIT(11)},
0501     {"DTS_VNN_REQ_STS",         BIT(12)},
0502     {"SMBUS_VNN_REQ_STS",           BIT(14)},
0503     {"CSME_VNN_REQ_STS",            BIT(15)},
0504     {"SMLINK0_VNN_REQ_STS",         BIT(16)},
0505     {"SMLINK1_VNN_REQ_STS",         BIT(17)},
0506     {"CLINK_VNN_REQ_STS",           BIT(20)},
0507     {"DCI_VNN_REQ_STS",         BIT(21)},
0508     {"ITH_VNN_REQ_STS",         BIT(22)},
0509     {"CSME_VNN_REQ_STS",            BIT(24)},
0510     {"GBE_VNN_REQ_STS",         BIT(25)},
0511     {}
0512 };
0513 
0514 static const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
0515     {"CPU_C10_REQ_STS_0",           BIT(0)},
0516     {"PCIe_LPM_En_REQ_STS_3",       BIT(3)},
0517     {"ITH_REQ_STS_5",           BIT(5)},
0518     {"CNVI_REQ_STS_6",          BIT(6)},
0519     {"ISH_REQ_STS_7",           BIT(7)},
0520     {"USB2_SUS_PG_Sys_REQ_STS_10",      BIT(10)},
0521     {"PCIe_Clk_REQ_STS_12",         BIT(12)},
0522     {"MPHY_Core_DL_REQ_STS_16",     BIT(16)},
0523     {"Break-even_En_REQ_STS_17",        BIT(17)},
0524     {"Auto-demo_En_REQ_STS_18",     BIT(18)},
0525     {"MPHY_SUS_REQ_STS_22",         BIT(22)},
0526     {"xDCI_attached_REQ_STS_24",        BIT(24)},
0527     {}
0528 };
0529 
0530 static const struct pmc_bit_map tgl_signal_status_map[] = {
0531     {"LSX_Wake0_En_STS",            BIT(0)},
0532     {"LSX_Wake0_Pol_STS",           BIT(1)},
0533     {"LSX_Wake1_En_STS",            BIT(2)},
0534     {"LSX_Wake1_Pol_STS",           BIT(3)},
0535     {"LSX_Wake2_En_STS",            BIT(4)},
0536     {"LSX_Wake2_Pol_STS",           BIT(5)},
0537     {"LSX_Wake3_En_STS",            BIT(6)},
0538     {"LSX_Wake3_Pol_STS",           BIT(7)},
0539     {"LSX_Wake4_En_STS",            BIT(8)},
0540     {"LSX_Wake4_Pol_STS",           BIT(9)},
0541     {"LSX_Wake5_En_STS",            BIT(10)},
0542     {"LSX_Wake5_Pol_STS",           BIT(11)},
0543     {"LSX_Wake6_En_STS",            BIT(12)},
0544     {"LSX_Wake6_Pol_STS",           BIT(13)},
0545     {"LSX_Wake7_En_STS",            BIT(14)},
0546     {"LSX_Wake7_Pol_STS",           BIT(15)},
0547     {"Intel_Se_IO_Wake0_En_STS",        BIT(16)},
0548     {"Intel_Se_IO_Wake0_Pol_STS",       BIT(17)},
0549     {"Intel_Se_IO_Wake1_En_STS",        BIT(18)},
0550     {"Intel_Se_IO_Wake1_Pol_STS",       BIT(19)},
0551     {"Int_Timer_SS_Wake0_En_STS",       BIT(20)},
0552     {"Int_Timer_SS_Wake0_Pol_STS",      BIT(21)},
0553     {"Int_Timer_SS_Wake1_En_STS",       BIT(22)},
0554     {"Int_Timer_SS_Wake1_Pol_STS",      BIT(23)},
0555     {"Int_Timer_SS_Wake2_En_STS",       BIT(24)},
0556     {"Int_Timer_SS_Wake2_Pol_STS",      BIT(25)},
0557     {"Int_Timer_SS_Wake3_En_STS",       BIT(26)},
0558     {"Int_Timer_SS_Wake3_Pol_STS",      BIT(27)},
0559     {"Int_Timer_SS_Wake4_En_STS",       BIT(28)},
0560     {"Int_Timer_SS_Wake4_Pol_STS",      BIT(29)},
0561     {"Int_Timer_SS_Wake5_En_STS",       BIT(30)},
0562     {"Int_Timer_SS_Wake5_Pol_STS",      BIT(31)},
0563     {}
0564 };
0565 
0566 static const struct pmc_bit_map *tgl_lpm_maps[] = {
0567     tgl_clocksource_status_map,
0568     tgl_power_gating_status_map,
0569     tgl_d3_status_map,
0570     tgl_vnn_req_status_map,
0571     tgl_vnn_misc_status_map,
0572     tgl_signal_status_map,
0573     NULL
0574 };
0575 
0576 static const struct pmc_reg_map tgl_reg_map = {
0577     .pfear_sts = ext_tgl_pfear_map,
0578     .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
0579     .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
0580     .ltr_show_sts = cnp_ltr_show_map,
0581     .msr_sts = msr_map,
0582     .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
0583     .regmap_length = CNP_PMC_MMIO_REG_LEN,
0584     .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
0585     .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
0586     .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
0587     .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
0588     .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
0589     .lpm_num_maps = TGL_LPM_NUM_MAPS,
0590     .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
0591     .lpm_sts_latch_en_offset = TGL_LPM_STS_LATCH_EN_OFFSET,
0592     .lpm_en_offset = TGL_LPM_EN_OFFSET,
0593     .lpm_priority_offset = TGL_LPM_PRI_OFFSET,
0594     .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
0595     .lpm_sts = tgl_lpm_maps,
0596     .lpm_status_offset = TGL_LPM_STATUS_OFFSET,
0597     .lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET,
0598     .etr3_offset = ETR3_OFFSET,
0599 };
0600 
0601 static void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)
0602 {
0603     struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
0604     const int num_maps = pmcdev->map->lpm_num_maps;
0605     u32 lpm_size = LPM_MAX_NUM_MODES * num_maps * 4;
0606     union acpi_object *out_obj;
0607     struct acpi_device *adev;
0608     guid_t s0ix_dsm_guid;
0609     u32 *lpm_req_regs, *addr;
0610 
0611     adev = ACPI_COMPANION(&pdev->dev);
0612     if (!adev)
0613         return;
0614 
0615     guid_parse(ACPI_S0IX_DSM_UUID, &s0ix_dsm_guid);
0616 
0617     out_obj = acpi_evaluate_dsm(adev->handle, &s0ix_dsm_guid, 0,
0618                     ACPI_GET_LOW_MODE_REGISTERS, NULL);
0619     if (out_obj && out_obj->type == ACPI_TYPE_BUFFER) {
0620         u32 size = out_obj->buffer.length;
0621 
0622         if (size != lpm_size) {
0623             acpi_handle_debug(adev->handle,
0624                 "_DSM returned unexpected buffer size, have %u, expect %u\n",
0625                 size, lpm_size);
0626             goto free_acpi_obj;
0627         }
0628     } else {
0629         acpi_handle_debug(adev->handle,
0630                   "_DSM function 0 evaluation failed\n");
0631         goto free_acpi_obj;
0632     }
0633 
0634     addr = (u32 *)out_obj->buffer.pointer;
0635 
0636     lpm_req_regs = devm_kzalloc(&pdev->dev, lpm_size * sizeof(u32),
0637                      GFP_KERNEL);
0638     if (!lpm_req_regs)
0639         goto free_acpi_obj;
0640 
0641     memcpy(lpm_req_regs, addr, lpm_size);
0642     pmcdev->lpm_req_regs = lpm_req_regs;
0643 
0644 free_acpi_obj:
0645     ACPI_FREE(out_obj);
0646 }
0647 
0648 /* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */
0649 static const struct pmc_bit_map adl_pfear_map[] = {
0650     {"SPI/eSPI",        BIT(2)},
0651     {"XHCI",        BIT(3)},
0652     {"SPA",         BIT(4)},
0653     {"SPB",         BIT(5)},
0654     {"SPC",         BIT(6)},
0655     {"GBE",         BIT(7)},
0656 
0657     {"SATA",        BIT(0)},
0658     {"HDA_PGD0",        BIT(1)},
0659     {"HDA_PGD1",        BIT(2)},
0660     {"HDA_PGD2",        BIT(3)},
0661     {"HDA_PGD3",        BIT(4)},
0662     {"SPD",         BIT(5)},
0663     {"LPSS",        BIT(6)},
0664 
0665     {"SMB",         BIT(0)},
0666     {"ISH",         BIT(1)},
0667     {"ITH",         BIT(3)},
0668 
0669     {"XDCI",        BIT(1)},
0670     {"DCI",         BIT(2)},
0671     {"CSE",         BIT(3)},
0672     {"CSME_KVM",        BIT(4)},
0673     {"CSME_PMT",        BIT(5)},
0674     {"CSME_CLINK",      BIT(6)},
0675     {"CSME_PTIO",       BIT(7)},
0676 
0677     {"CSME_USBR",       BIT(0)},
0678     {"CSME_SUSRAM",     BIT(1)},
0679     {"CSME_SMT1",       BIT(2)},
0680     {"CSME_SMS2",       BIT(4)},
0681     {"CSME_SMS1",       BIT(5)},
0682     {"CSME_RTC",        BIT(6)},
0683     {"CSME_PSF",        BIT(7)},
0684 
0685     {"CNVI",        BIT(3)},
0686 
0687     {"HDA_PGD4",        BIT(2)},
0688     {"HDA_PGD5",        BIT(3)},
0689     {"HDA_PGD6",        BIT(4)},
0690     {}
0691 };
0692 
0693 static const struct pmc_bit_map *ext_adl_pfear_map[] = {
0694     /*
0695      * Check intel_pmc_core_ids[] users of cnp_reg_map for
0696      * a list of core SoCs using this.
0697      */
0698     adl_pfear_map,
0699     NULL
0700 };
0701 
0702 static const struct pmc_bit_map adl_ltr_show_map[] = {
0703     {"SOUTHPORT_A",     CNP_PMC_LTR_SPA},
0704     {"SOUTHPORT_B",     CNP_PMC_LTR_SPB},
0705     {"SATA",        CNP_PMC_LTR_SATA},
0706     {"GIGABIT_ETHERNET",    CNP_PMC_LTR_GBE},
0707     {"XHCI",        CNP_PMC_LTR_XHCI},
0708     {"SOUTHPORT_F",     ADL_PMC_LTR_SPF},
0709     {"ME",          CNP_PMC_LTR_ME},
0710     /* EVA is Enterprise Value Add, doesn't really exist on PCH */
0711     {"SATA1",       CNP_PMC_LTR_EVA},
0712     {"SOUTHPORT_C",     CNP_PMC_LTR_SPC},
0713     {"HD_AUDIO",        CNP_PMC_LTR_AZ},
0714     {"CNV",         CNP_PMC_LTR_CNV},
0715     {"LPSS",        CNP_PMC_LTR_LPSS},
0716     {"SOUTHPORT_D",     CNP_PMC_LTR_SPD},
0717     {"SOUTHPORT_E",     CNP_PMC_LTR_SPE},
0718     {"SATA2",       CNP_PMC_LTR_CAM},
0719     {"ESPI",        CNP_PMC_LTR_ESPI},
0720     {"SCC",         CNP_PMC_LTR_SCC},
0721     {"ISH",         CNP_PMC_LTR_ISH},
0722     {"UFSX2",       CNP_PMC_LTR_UFSX2},
0723     {"EMMC",        CNP_PMC_LTR_EMMC},
0724     /*
0725      * Check intel_pmc_core_ids[] users of cnp_reg_map for
0726      * a list of core SoCs using this.
0727      */
0728     {"WIGIG",       ICL_PMC_LTR_WIGIG},
0729     {"THC0",        TGL_PMC_LTR_THC0},
0730     {"THC1",        TGL_PMC_LTR_THC1},
0731     {"SOUTHPORT_G",     CNP_PMC_LTR_RESERVED},
0732 
0733     /* Below two cannot be used for LTR_IGNORE */
0734     {"CURRENT_PLATFORM",    CNP_PMC_LTR_CUR_PLT},
0735     {"AGGREGATED_SYSTEM",   CNP_PMC_LTR_CUR_ASLT},
0736     {}
0737 };
0738 
0739 static const struct pmc_bit_map adl_clocksource_status_map[] = {
0740     {"CLKPART1_OFF_STS",            BIT(0)},
0741     {"CLKPART2_OFF_STS",            BIT(1)},
0742     {"CLKPART3_OFF_STS",            BIT(2)},
0743     {"CLKPART4_OFF_STS",            BIT(3)},
0744     {"CLKPART5_OFF_STS",            BIT(4)},
0745     {"CLKPART6_OFF_STS",            BIT(5)},
0746     {"CLKPART7_OFF_STS",            BIT(6)},
0747     {"CLKPART8_OFF_STS",            BIT(7)},
0748     {"PCIE0PLL_OFF_STS",            BIT(10)},
0749     {"PCIE1PLL_OFF_STS",            BIT(11)},
0750     {"PCIE2PLL_OFF_STS",            BIT(12)},
0751     {"PCIE3PLL_OFF_STS",            BIT(13)},
0752     {"PCIE4PLL_OFF_STS",            BIT(14)},
0753     {"PCIE5PLL_OFF_STS",            BIT(15)},
0754     {"PCIE6PLL_OFF_STS",            BIT(16)},
0755     {"USB2PLL_OFF_STS",         BIT(18)},
0756     {"OCPLL_OFF_STS",           BIT(22)},
0757     {"AUDIOPLL_OFF_STS",            BIT(23)},
0758     {"GBEPLL_OFF_STS",          BIT(24)},
0759     {"Fast_XTAL_Osc_OFF_STS",       BIT(25)},
0760     {"AC_Ring_Osc_OFF_STS",         BIT(26)},
0761     {"MC_Ring_Osc_OFF_STS",         BIT(27)},
0762     {"SATAPLL_OFF_STS",         BIT(29)},
0763     {"USB3PLL_OFF_STS",         BIT(31)},
0764     {}
0765 };
0766 
0767 static const struct pmc_bit_map adl_power_gating_status_0_map[] = {
0768     {"PMC_PGD0_PG_STS",         BIT(0)},
0769     {"DMI_PGD0_PG_STS",         BIT(1)},
0770     {"ESPISPI_PGD0_PG_STS",         BIT(2)},
0771     {"XHCI_PGD0_PG_STS",            BIT(3)},
0772     {"SPA_PGD0_PG_STS",         BIT(4)},
0773     {"SPB_PGD0_PG_STS",         BIT(5)},
0774     {"SPC_PGD0_PG_STS",         BIT(6)},
0775     {"GBE_PGD0_PG_STS",         BIT(7)},
0776     {"SATA_PGD0_PG_STS",            BIT(8)},
0777     {"DSP_PGD0_PG_STS",         BIT(9)},
0778     {"DSP_PGD1_PG_STS",         BIT(10)},
0779     {"DSP_PGD2_PG_STS",         BIT(11)},
0780     {"DSP_PGD3_PG_STS",         BIT(12)},
0781     {"SPD_PGD0_PG_STS",         BIT(13)},
0782     {"LPSS_PGD0_PG_STS",            BIT(14)},
0783     {"SMB_PGD0_PG_STS",         BIT(16)},
0784     {"ISH_PGD0_PG_STS",         BIT(17)},
0785     {"NPK_PGD0_PG_STS",         BIT(19)},
0786     {"PECI_PGD0_PG_STS",            BIT(21)},
0787     {"XDCI_PGD0_PG_STS",            BIT(25)},
0788     {"EXI_PGD0_PG_STS",         BIT(26)},
0789     {"CSE_PGD0_PG_STS",         BIT(27)},
0790     {"KVMCC_PGD0_PG_STS",           BIT(28)},
0791     {"PMT_PGD0_PG_STS",         BIT(29)},
0792     {"CLINK_PGD0_PG_STS",           BIT(30)},
0793     {"PTIO_PGD0_PG_STS",            BIT(31)},
0794     {}
0795 };
0796 
0797 static const struct pmc_bit_map adl_power_gating_status_1_map[] = {
0798     {"USBR0_PGD0_PG_STS",           BIT(0)},
0799     {"SMT1_PGD0_PG_STS",            BIT(2)},
0800     {"CSMERTC_PGD0_PG_STS",         BIT(6)},
0801     {"CSMEPSF_PGD0_PG_STS",         BIT(7)},
0802     {"CNVI_PGD0_PG_STS",            BIT(19)},
0803     {"DSP_PGD4_PG_STS",         BIT(26)},
0804     {"SPG_PGD0_PG_STS",         BIT(27)},
0805     {"SPE_PGD0_PG_STS",         BIT(28)},
0806     {}
0807 };
0808 
0809 static const struct pmc_bit_map adl_power_gating_status_2_map[] = {
0810     {"THC0_PGD0_PG_STS",            BIT(7)},
0811     {"THC1_PGD0_PG_STS",            BIT(8)},
0812     {"SPF_PGD0_PG_STS",         BIT(14)},
0813     {}
0814 };
0815 
0816 static const struct pmc_bit_map adl_d3_status_0_map[] = {
0817     {"ISH_D3_STS",              BIT(2)},
0818     {"LPSS_D3_STS",             BIT(3)},
0819     {"XDCI_D3_STS",             BIT(4)},
0820     {"XHCI_D3_STS",             BIT(5)},
0821     {"SPA_D3_STS",              BIT(12)},
0822     {"SPB_D3_STS",              BIT(13)},
0823     {"SPC_D3_STS",              BIT(14)},
0824     {"SPD_D3_STS",              BIT(15)},
0825     {"SPE_D3_STS",              BIT(16)},
0826     {"DSP_D3_STS",              BIT(19)},
0827     {"SATA_D3_STS",             BIT(20)},
0828     {"DMI_D3_STS",              BIT(22)},
0829     {}
0830 };
0831 
0832 static const struct pmc_bit_map adl_d3_status_1_map[] = {
0833     {"GBE_D3_STS",              BIT(19)},
0834     {"CNVI_D3_STS",             BIT(27)},
0835     {}
0836 };
0837 
0838 static const struct pmc_bit_map adl_d3_status_2_map[] = {
0839     {"CSMERTC_D3_STS",          BIT(1)},
0840     {"CSE_D3_STS",              BIT(4)},
0841     {"KVMCC_D3_STS",            BIT(5)},
0842     {"USBR0_D3_STS",            BIT(6)},
0843     {"SMT1_D3_STS",             BIT(8)},
0844     {"PTIO_D3_STS",             BIT(16)},
0845     {"PMT_D3_STS",              BIT(17)},
0846     {}
0847 };
0848 
0849 static const struct pmc_bit_map adl_d3_status_3_map[] = {
0850     {"THC0_D3_STS",             BIT(14)},
0851     {"THC1_D3_STS",             BIT(15)},
0852     {}
0853 };
0854 
0855 static const struct pmc_bit_map adl_vnn_req_status_0_map[] = {
0856     {"ISH_VNN_REQ_STS",         BIT(2)},
0857     {"ESPISPI_VNN_REQ_STS",         BIT(18)},
0858     {"DSP_VNN_REQ_STS",         BIT(19)},
0859     {}
0860 };
0861 
0862 static const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
0863     {"NPK_VNN_REQ_STS",         BIT(4)},
0864     {"EXI_VNN_REQ_STS",         BIT(9)},
0865     {"GBE_VNN_REQ_STS",         BIT(19)},
0866     {"SMB_VNN_REQ_STS",         BIT(25)},
0867     {"CNVI_VNN_REQ_STS",            BIT(27)},
0868     {}
0869 };
0870 
0871 static const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
0872     {"CSMERTC_VNN_REQ_STS",         BIT(1)},
0873     {"CSE_VNN_REQ_STS",         BIT(4)},
0874     {"SMT1_VNN_REQ_STS",            BIT(8)},
0875     {"CLINK_VNN_REQ_STS",           BIT(14)},
0876     {"GPIOCOM4_VNN_REQ_STS",        BIT(20)},
0877     {"GPIOCOM3_VNN_REQ_STS",        BIT(21)},
0878     {"GPIOCOM2_VNN_REQ_STS",        BIT(22)},
0879     {"GPIOCOM1_VNN_REQ_STS",        BIT(23)},
0880     {"GPIOCOM0_VNN_REQ_STS",        BIT(24)},
0881     {}
0882 };
0883 
0884 static const struct pmc_bit_map adl_vnn_req_status_3_map[] = {
0885     {"GPIOCOM5_VNN_REQ_STS",        BIT(11)},
0886     {}
0887 };
0888 
0889 static const struct pmc_bit_map adl_vnn_misc_status_map[] = {
0890     {"CPU_C10_REQ_STS",         BIT(0)},
0891     {"PCIe_LPM_En_REQ_STS",         BIT(3)},
0892     {"ITH_REQ_STS",             BIT(5)},
0893     {"CNVI_REQ_STS",            BIT(6)},
0894     {"ISH_REQ_STS",             BIT(7)},
0895     {"USB2_SUS_PG_Sys_REQ_STS",     BIT(10)},
0896     {"PCIe_Clk_REQ_STS",            BIT(12)},
0897     {"MPHY_Core_DL_REQ_STS",        BIT(16)},
0898     {"Break-even_En_REQ_STS",       BIT(17)},
0899     {"MPHY_SUS_REQ_STS",            BIT(22)},
0900     {"xDCI_attached_REQ_STS",       BIT(24)},
0901     {}
0902 };
0903 
0904 static const struct pmc_bit_map *adl_lpm_maps[] = {
0905     adl_clocksource_status_map,
0906     adl_power_gating_status_0_map,
0907     adl_power_gating_status_1_map,
0908     adl_power_gating_status_2_map,
0909     adl_d3_status_0_map,
0910     adl_d3_status_1_map,
0911     adl_d3_status_2_map,
0912     adl_d3_status_3_map,
0913     adl_vnn_req_status_0_map,
0914     adl_vnn_req_status_1_map,
0915     adl_vnn_req_status_2_map,
0916     adl_vnn_req_status_3_map,
0917     adl_vnn_misc_status_map,
0918     tgl_signal_status_map,
0919     NULL
0920 };
0921 
0922 static const struct pmc_reg_map adl_reg_map = {
0923     .pfear_sts = ext_adl_pfear_map,
0924     .slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
0925     .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
0926     .ltr_show_sts = adl_ltr_show_map,
0927     .msr_sts = msr_map,
0928     .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
0929     .regmap_length = CNP_PMC_MMIO_REG_LEN,
0930     .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
0931     .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
0932     .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
0933     .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
0934     .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
0935     .lpm_num_modes = ADL_LPM_NUM_MODES,
0936     .lpm_num_maps = ADL_LPM_NUM_MAPS,
0937     .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
0938     .etr3_offset = ETR3_OFFSET,
0939     .lpm_sts_latch_en_offset = ADL_LPM_STATUS_LATCH_EN_OFFSET,
0940     .lpm_priority_offset = ADL_LPM_PRI_OFFSET,
0941     .lpm_en_offset = ADL_LPM_EN_OFFSET,
0942     .lpm_residency_offset = ADL_LPM_RESIDENCY_OFFSET,
0943     .lpm_sts = adl_lpm_maps,
0944     .lpm_status_offset = ADL_LPM_STATUS_OFFSET,
0945     .lpm_live_status_offset = ADL_LPM_LIVE_STATUS_OFFSET,
0946 };
0947 
0948 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
0949 {
0950     return readl(pmcdev->regbase + reg_offset);
0951 }
0952 
0953 static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
0954                       u32 val)
0955 {
0956     writel(val, pmcdev->regbase + reg_offset);
0957 }
0958 
0959 static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
0960 {
0961     return (u64)value * pmcdev->map->slp_s0_res_counter_step;
0962 }
0963 
0964 static int set_etr3(struct pmc_dev *pmcdev)
0965 {
0966     const struct pmc_reg_map *map = pmcdev->map;
0967     u32 reg;
0968     int err;
0969 
0970     if (!map->etr3_offset)
0971         return -EOPNOTSUPP;
0972 
0973     mutex_lock(&pmcdev->lock);
0974 
0975     /* check if CF9 is locked */
0976     reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
0977     if (reg & ETR3_CF9LOCK) {
0978         err = -EACCES;
0979         goto out_unlock;
0980     }
0981 
0982     /* write CF9 global reset bit */
0983     reg |= ETR3_CF9GR;
0984     pmc_core_reg_write(pmcdev, map->etr3_offset, reg);
0985 
0986     reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
0987     if (!(reg & ETR3_CF9GR)) {
0988         err = -EIO;
0989         goto out_unlock;
0990     }
0991 
0992     err = 0;
0993 
0994 out_unlock:
0995     mutex_unlock(&pmcdev->lock);
0996     return err;
0997 }
0998 static umode_t etr3_is_visible(struct kobject *kobj,
0999                 struct attribute *attr,
1000                 int idx)
1001 {
1002     struct device *dev = kobj_to_dev(kobj);
1003     struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1004     const struct pmc_reg_map *map = pmcdev->map;
1005     u32 reg;
1006 
1007     mutex_lock(&pmcdev->lock);
1008     reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
1009     mutex_unlock(&pmcdev->lock);
1010 
1011     return reg & ETR3_CF9LOCK ? attr->mode & (SYSFS_PREALLOC | 0444) : attr->mode;
1012 }
1013 
1014 static ssize_t etr3_show(struct device *dev,
1015                  struct device_attribute *attr, char *buf)
1016 {
1017     struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1018     const struct pmc_reg_map *map = pmcdev->map;
1019     u32 reg;
1020 
1021     if (!map->etr3_offset)
1022         return -EOPNOTSUPP;
1023 
1024     mutex_lock(&pmcdev->lock);
1025 
1026     reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
1027     reg &= ETR3_CF9GR | ETR3_CF9LOCK;
1028 
1029     mutex_unlock(&pmcdev->lock);
1030 
1031     return sysfs_emit(buf, "0x%08x", reg);
1032 }
1033 
1034 static ssize_t etr3_store(struct device *dev,
1035                   struct device_attribute *attr,
1036                   const char *buf, size_t len)
1037 {
1038     struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1039     int err;
1040     u32 reg;
1041 
1042     err = kstrtouint(buf, 16, &reg);
1043     if (err)
1044         return err;
1045 
1046     /* allow only CF9 writes */
1047     if (reg != ETR3_CF9GR)
1048         return -EINVAL;
1049 
1050     err = set_etr3(pmcdev);
1051     if (err)
1052         return err;
1053 
1054     return len;
1055 }
1056 static DEVICE_ATTR_RW(etr3);
1057 
1058 static struct attribute *pmc_attrs[] = {
1059     &dev_attr_etr3.attr,
1060     NULL
1061 };
1062 
1063 static const struct attribute_group pmc_attr_group = {
1064     .attrs = pmc_attrs,
1065     .is_visible = etr3_is_visible,
1066 };
1067 
1068 static const struct attribute_group *pmc_dev_groups[] = {
1069     &pmc_attr_group,
1070     NULL
1071 };
1072 
1073 static int pmc_core_dev_state_get(void *data, u64 *val)
1074 {
1075     struct pmc_dev *pmcdev = data;
1076     const struct pmc_reg_map *map = pmcdev->map;
1077     u32 value;
1078 
1079     value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
1080     *val = pmc_core_adjust_slp_s0_step(pmcdev, value);
1081 
1082     return 0;
1083 }
1084 
1085 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
1086 
1087 static int pmc_core_check_read_lock_bit(struct pmc_dev *pmcdev)
1088 {
1089     u32 value;
1090 
1091     value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
1092     return value & BIT(pmcdev->map->pm_read_disable_bit);
1093 }
1094 
1095 static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev,
1096                    struct seq_file *s)
1097 {
1098     const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
1099     const struct pmc_bit_map *map;
1100     int offset = pmcdev->map->slps0_dbg_offset;
1101     u32 data;
1102 
1103     while (*maps) {
1104         map = *maps;
1105         data = pmc_core_reg_read(pmcdev, offset);
1106         offset += 4;
1107         while (map->name) {
1108             if (dev)
1109                 dev_info(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
1110                     map->name,
1111                     data & map->bit_mask ? "Yes" : "No");
1112             if (s)
1113                 seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
1114                        map->name,
1115                        data & map->bit_mask ? "Yes" : "No");
1116             ++map;
1117         }
1118         ++maps;
1119     }
1120 }
1121 
1122 static int pmc_core_lpm_get_arr_size(const struct pmc_bit_map **maps)
1123 {
1124     int idx;
1125 
1126     for (idx = 0; maps[idx]; idx++)
1127         ;/* Nothing */
1128 
1129     return idx;
1130 }
1131 
1132 static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev,
1133                  struct seq_file *s, u32 offset,
1134                  const char *str,
1135                  const struct pmc_bit_map **maps)
1136 {
1137     int index, idx, len = 32, bit_mask, arr_size;
1138     u32 *lpm_regs;
1139 
1140     arr_size = pmc_core_lpm_get_arr_size(maps);
1141     lpm_regs = kmalloc_array(arr_size, sizeof(*lpm_regs), GFP_KERNEL);
1142     if (!lpm_regs)
1143         return;
1144 
1145     for (index = 0; index < arr_size; index++) {
1146         lpm_regs[index] = pmc_core_reg_read(pmcdev, offset);
1147         offset += 4;
1148     }
1149 
1150     for (idx = 0; idx < arr_size; idx++) {
1151         if (dev)
1152             dev_info(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx,
1153                 lpm_regs[idx]);
1154         if (s)
1155             seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx,
1156                    lpm_regs[idx]);
1157         for (index = 0; maps[idx][index].name && index < len; index++) {
1158             bit_mask = maps[idx][index].bit_mask;
1159             if (dev)
1160                 dev_info(dev, "%-30s %-30d\n",
1161                     maps[idx][index].name,
1162                     lpm_regs[idx] & bit_mask ? 1 : 0);
1163             if (s)
1164                 seq_printf(s, "%-30s %-30d\n",
1165                        maps[idx][index].name,
1166                        lpm_regs[idx] & bit_mask ? 1 : 0);
1167         }
1168     }
1169 
1170     kfree(lpm_regs);
1171 }
1172 
1173 static bool slps0_dbg_latch;
1174 
1175 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
1176 {
1177     return readb(pmcdev->regbase + offset);
1178 }
1179 
1180 static void pmc_core_display_map(struct seq_file *s, int index, int idx, int ip,
1181                  u8 pf_reg, const struct pmc_bit_map **pf_map)
1182 {
1183     seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
1184            ip, pf_map[idx][index].name,
1185            pf_map[idx][index].bit_mask & pf_reg ? "Off" : "On");
1186 }
1187 
1188 static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
1189 {
1190     struct pmc_dev *pmcdev = s->private;
1191     const struct pmc_bit_map **maps = pmcdev->map->pfear_sts;
1192     u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
1193     int index, iter, idx, ip = 0;
1194 
1195     iter = pmcdev->map->ppfear0_offset;
1196 
1197     for (index = 0; index < pmcdev->map->ppfear_buckets &&
1198          index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
1199         pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
1200 
1201     for (idx = 0; maps[idx]; idx++) {
1202         for (index = 0; maps[idx][index].name &&
1203              index < pmcdev->map->ppfear_buckets * 8; ip++, index++)
1204             pmc_core_display_map(s, index, idx, ip,
1205                          pf_regs[index / 8], maps);
1206     }
1207 
1208     return 0;
1209 }
1210 DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear);
1211 
1212 /* This function should return link status, 0 means ready */
1213 static int pmc_core_mtpmc_link_status(struct pmc_dev *pmcdev)
1214 {
1215     u32 value;
1216 
1217     value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
1218     return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
1219 }
1220 
1221 static int pmc_core_send_msg(struct pmc_dev *pmcdev, u32 *addr_xram)
1222 {
1223     u32 dest;
1224     int timeout;
1225 
1226     for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
1227         if (pmc_core_mtpmc_link_status(pmcdev) == 0)
1228             break;
1229         msleep(5);
1230     }
1231 
1232     if (timeout <= 0 && pmc_core_mtpmc_link_status(pmcdev))
1233         return -EBUSY;
1234 
1235     dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
1236     pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
1237     return 0;
1238 }
1239 
1240 static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused)
1241 {
1242     struct pmc_dev *pmcdev = s->private;
1243     const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
1244     u32 mphy_core_reg_low, mphy_core_reg_high;
1245     u32 val_low, val_high;
1246     int index, err = 0;
1247 
1248     if (pmcdev->pmc_xram_read_bit) {
1249         seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
1250         return 0;
1251     }
1252 
1253     mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
1254     mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
1255 
1256     mutex_lock(&pmcdev->lock);
1257 
1258     if (pmc_core_send_msg(pmcdev, &mphy_core_reg_low) != 0) {
1259         err = -EBUSY;
1260         goto out_unlock;
1261     }
1262 
1263     msleep(10);
1264     val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
1265 
1266     if (pmc_core_send_msg(pmcdev, &mphy_core_reg_high) != 0) {
1267         err = -EBUSY;
1268         goto out_unlock;
1269     }
1270 
1271     msleep(10);
1272     val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
1273 
1274     for (index = 0; index < 8 && map[index].name; index++) {
1275         seq_printf(s, "%-32s\tState: %s\n",
1276                map[index].name,
1277                map[index].bit_mask & val_low ? "Not power gated" :
1278                "Power gated");
1279     }
1280 
1281     for (index = 8; map[index].name; index++) {
1282         seq_printf(s, "%-32s\tState: %s\n",
1283                map[index].name,
1284                map[index].bit_mask & val_high ? "Not power gated" :
1285                "Power gated");
1286     }
1287 
1288 out_unlock:
1289     mutex_unlock(&pmcdev->lock);
1290     return err;
1291 }
1292 DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg);
1293 
1294 static int pmc_core_pll_show(struct seq_file *s, void *unused)
1295 {
1296     struct pmc_dev *pmcdev = s->private;
1297     const struct pmc_bit_map *map = pmcdev->map->pll_sts;
1298     u32 mphy_common_reg, val;
1299     int index, err = 0;
1300 
1301     if (pmcdev->pmc_xram_read_bit) {
1302         seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
1303         return 0;
1304     }
1305 
1306     mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
1307     mutex_lock(&pmcdev->lock);
1308 
1309     if (pmc_core_send_msg(pmcdev, &mphy_common_reg) != 0) {
1310         err = -EBUSY;
1311         goto out_unlock;
1312     }
1313 
1314     /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
1315     msleep(10);
1316     val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
1317 
1318     for (index = 0; map[index].name ; index++) {
1319         seq_printf(s, "%-32s\tState: %s\n",
1320                map[index].name,
1321                map[index].bit_mask & val ? "Active" : "Idle");
1322     }
1323 
1324 out_unlock:
1325     mutex_unlock(&pmcdev->lock);
1326     return err;
1327 }
1328 DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
1329 
1330 static int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value)
1331 {
1332     const struct pmc_reg_map *map = pmcdev->map;
1333     u32 reg;
1334     int err = 0;
1335 
1336     mutex_lock(&pmcdev->lock);
1337 
1338     if (value > map->ltr_ignore_max) {
1339         err = -EINVAL;
1340         goto out_unlock;
1341     }
1342 
1343     reg = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
1344     reg |= BIT(value);
1345     pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, reg);
1346 
1347 out_unlock:
1348     mutex_unlock(&pmcdev->lock);
1349 
1350     return err;
1351 }
1352 
1353 static ssize_t pmc_core_ltr_ignore_write(struct file *file,
1354                      const char __user *userbuf,
1355                      size_t count, loff_t *ppos)
1356 {
1357     struct seq_file *s = file->private_data;
1358     struct pmc_dev *pmcdev = s->private;
1359     u32 buf_size, value;
1360     int err;
1361 
1362     buf_size = min_t(u32, count, 64);
1363 
1364     err = kstrtou32_from_user(userbuf, buf_size, 10, &value);
1365     if (err)
1366         return err;
1367 
1368     err = pmc_core_send_ltr_ignore(pmcdev, value);
1369 
1370     return err == 0 ? count : err;
1371 }
1372 
1373 static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
1374 {
1375     return 0;
1376 }
1377 
1378 static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
1379 {
1380     return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
1381 }
1382 
1383 static const struct file_operations pmc_core_ltr_ignore_ops = {
1384     .open           = pmc_core_ltr_ignore_open,
1385     .read           = seq_read,
1386     .write          = pmc_core_ltr_ignore_write,
1387     .llseek         = seq_lseek,
1388     .release        = single_release,
1389 };
1390 
1391 static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
1392 {
1393     const struct pmc_reg_map *map = pmcdev->map;
1394     u32 fd;
1395 
1396     mutex_lock(&pmcdev->lock);
1397 
1398     if (!reset && !slps0_dbg_latch)
1399         goto out_unlock;
1400 
1401     fd = pmc_core_reg_read(pmcdev, map->slps0_dbg_offset);
1402     if (reset)
1403         fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
1404     else
1405         fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
1406     pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd);
1407 
1408     slps0_dbg_latch = false;
1409 
1410 out_unlock:
1411     mutex_unlock(&pmcdev->lock);
1412 }
1413 
1414 static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
1415 {
1416     struct pmc_dev *pmcdev = s->private;
1417 
1418     pmc_core_slps0_dbg_latch(pmcdev, false);
1419     pmc_core_slps0_display(pmcdev, NULL, s);
1420     pmc_core_slps0_dbg_latch(pmcdev, true);
1421 
1422     return 0;
1423 }
1424 DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
1425 
1426 static u32 convert_ltr_scale(u32 val)
1427 {
1428     /*
1429      * As per PCIE specification supporting document
1430      * ECN_LatencyTolnReporting_14Aug08.pdf the Latency
1431      * Tolerance Reporting data payload is encoded in a
1432      * 3 bit scale and 10 bit value fields. Values are
1433      * multiplied by the indicated scale to yield an absolute time
1434      * value, expressible in a range from 1 nanosecond to
1435      * 2^25*(2^10-1) = 34,326,183,936 nanoseconds.
1436      *
1437      * scale encoding is as follows:
1438      *
1439      * ----------------------------------------------
1440      * |scale factor    |   Multiplier (ns) |
1441      * ----------------------------------------------
1442      * |    0       |   1       |
1443      * |    1       |   32      |
1444      * |    2       |   1024        |
1445      * |    3       |   32768       |
1446      * |    4       |   1048576     |
1447      * |    5       |   33554432    |
1448      * |    6       |   Invalid     |
1449      * |    7       |   Invalid     |
1450      * ----------------------------------------------
1451      */
1452     if (val > 5) {
1453         pr_warn("Invalid LTR scale factor.\n");
1454         return 0;
1455     }
1456 
1457     return 1U << (5 * val);
1458 }
1459 
1460 static int pmc_core_ltr_show(struct seq_file *s, void *unused)
1461 {
1462     struct pmc_dev *pmcdev = s->private;
1463     const struct pmc_bit_map *map = pmcdev->map->ltr_show_sts;
1464     u64 decoded_snoop_ltr, decoded_non_snoop_ltr;
1465     u32 ltr_raw_data, scale, val;
1466     u16 snoop_ltr, nonsnoop_ltr;
1467     int index;
1468 
1469     for (index = 0; map[index].name ; index++) {
1470         decoded_snoop_ltr = decoded_non_snoop_ltr = 0;
1471         ltr_raw_data = pmc_core_reg_read(pmcdev,
1472                          map[index].bit_mask);
1473         snoop_ltr = ltr_raw_data & ~MTPMC_MASK;
1474         nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK;
1475 
1476         if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) {
1477             scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr);
1478             val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr);
1479             decoded_non_snoop_ltr = val * convert_ltr_scale(scale);
1480         }
1481 
1482         if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) {
1483             scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr);
1484             val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr);
1485             decoded_snoop_ltr = val * convert_ltr_scale(scale);
1486         }
1487 
1488         seq_printf(s, "%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\n",
1489                map[index].name, ltr_raw_data,
1490                decoded_non_snoop_ltr,
1491                decoded_snoop_ltr);
1492     }
1493     return 0;
1494 }
1495 DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
1496 
1497 static inline u64 adjust_lpm_residency(struct pmc_dev *pmcdev, u32 offset,
1498                        const int lpm_adj_x2)
1499 {
1500     u64 lpm_res = pmc_core_reg_read(pmcdev, offset);
1501 
1502     return GET_X2_COUNTER((u64)lpm_adj_x2 * lpm_res);
1503 }
1504 
1505 static int pmc_core_substate_res_show(struct seq_file *s, void *unused)
1506 {
1507     struct pmc_dev *pmcdev = s->private;
1508     const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
1509     u32 offset = pmcdev->map->lpm_residency_offset;
1510     int i, mode;
1511 
1512     seq_printf(s, "%-10s %-15s\n", "Substate", "Residency");
1513 
1514     pmc_for_each_mode(i, mode, pmcdev) {
1515         seq_printf(s, "%-10s %-15llu\n", pmc_lpm_modes[mode],
1516                adjust_lpm_residency(pmcdev, offset + (4 * mode), lpm_adj_x2));
1517     }
1518 
1519     return 0;
1520 }
1521 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res);
1522 
1523 static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused)
1524 {
1525     struct pmc_dev *pmcdev = s->private;
1526     const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
1527     u32 offset = pmcdev->map->lpm_status_offset;
1528 
1529     pmc_core_lpm_display(pmcdev, NULL, s, offset, "STATUS", maps);
1530 
1531     return 0;
1532 }
1533 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs);
1534 
1535 static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unused)
1536 {
1537     struct pmc_dev *pmcdev = s->private;
1538     const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
1539     u32 offset = pmcdev->map->lpm_live_status_offset;
1540 
1541     pmc_core_lpm_display(pmcdev, NULL, s, offset, "LIVE_STATUS", maps);
1542 
1543     return 0;
1544 }
1545 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs);
1546 
1547 static void pmc_core_substate_req_header_show(struct seq_file *s)
1548 {
1549     struct pmc_dev *pmcdev = s->private;
1550     int i, mode;
1551 
1552     seq_printf(s, "%30s |", "Element");
1553     pmc_for_each_mode(i, mode, pmcdev)
1554         seq_printf(s, " %9s |", pmc_lpm_modes[mode]);
1555 
1556     seq_printf(s, " %9s |\n", "Status");
1557 }
1558 
1559 static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused)
1560 {
1561     struct pmc_dev *pmcdev = s->private;
1562     const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
1563     const struct pmc_bit_map *map;
1564     const int num_maps = pmcdev->map->lpm_num_maps;
1565     u32 sts_offset = pmcdev->map->lpm_status_offset;
1566     u32 *lpm_req_regs = pmcdev->lpm_req_regs;
1567     int mp;
1568 
1569     /* Display the header */
1570     pmc_core_substate_req_header_show(s);
1571 
1572     /* Loop over maps */
1573     for (mp = 0; mp < num_maps; mp++) {
1574         u32 req_mask = 0;
1575         u32 lpm_status;
1576         int mode, idx, i, len = 32;
1577 
1578         /*
1579          * Capture the requirements and create a mask so that we only
1580          * show an element if it's required for at least one of the
1581          * enabled low power modes
1582          */
1583         pmc_for_each_mode(idx, mode, pmcdev)
1584             req_mask |= lpm_req_regs[mp + (mode * num_maps)];
1585 
1586         /* Get the last latched status for this map */
1587         lpm_status = pmc_core_reg_read(pmcdev, sts_offset + (mp * 4));
1588 
1589         /*  Loop over elements in this map */
1590         map = maps[mp];
1591         for (i = 0; map[i].name && i < len; i++) {
1592             u32 bit_mask = map[i].bit_mask;
1593 
1594             if (!(bit_mask & req_mask))
1595                 /*
1596                  * Not required for any enabled states
1597                  * so don't display
1598                  */
1599                 continue;
1600 
1601             /* Display the element name in the first column */
1602             seq_printf(s, "%30s |", map[i].name);
1603 
1604             /* Loop over the enabled states and display if required */
1605             pmc_for_each_mode(idx, mode, pmcdev) {
1606                 if (lpm_req_regs[mp + (mode * num_maps)] & bit_mask)
1607                     seq_printf(s, " %9s |",
1608                            "Required");
1609                 else
1610                     seq_printf(s, " %9s |", " ");
1611             }
1612 
1613             /* In Status column, show the last captured state of this agent */
1614             if (lpm_status & bit_mask)
1615                 seq_printf(s, " %9s |", "Yes");
1616             else
1617                 seq_printf(s, " %9s |", " ");
1618 
1619             seq_puts(s, "\n");
1620         }
1621     }
1622 
1623     return 0;
1624 }
1625 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs);
1626 
1627 static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
1628 {
1629     struct pmc_dev *pmcdev = s->private;
1630     bool c10;
1631     u32 reg;
1632     int idx, mode;
1633 
1634     reg = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_sts_latch_en_offset);
1635     if (reg & LPM_STS_LATCH_MODE) {
1636         seq_puts(s, "c10");
1637         c10 = false;
1638     } else {
1639         seq_puts(s, "[c10]");
1640         c10 = true;
1641     }
1642 
1643     pmc_for_each_mode(idx, mode, pmcdev) {
1644         if ((BIT(mode) & reg) && !c10)
1645             seq_printf(s, " [%s]", pmc_lpm_modes[mode]);
1646         else
1647             seq_printf(s, " %s", pmc_lpm_modes[mode]);
1648     }
1649 
1650     seq_puts(s, " clear\n");
1651 
1652     return 0;
1653 }
1654 
1655 static ssize_t pmc_core_lpm_latch_mode_write(struct file *file,
1656                          const char __user *userbuf,
1657                          size_t count, loff_t *ppos)
1658 {
1659     struct seq_file *s = file->private_data;
1660     struct pmc_dev *pmcdev = s->private;
1661     bool clear = false, c10 = false;
1662     unsigned char buf[8];
1663     int idx, m, mode;
1664     u32 reg;
1665 
1666     if (count > sizeof(buf) - 1)
1667         return -EINVAL;
1668     if (copy_from_user(buf, userbuf, count))
1669         return -EFAULT;
1670     buf[count] = '\0';
1671 
1672     /*
1673      * Allowed strings are:
1674      *  Any enabled substate, e.g. 'S0i2.0'
1675      *  'c10'
1676      *  'clear'
1677      */
1678     mode = sysfs_match_string(pmc_lpm_modes, buf);
1679 
1680     /* Check string matches enabled mode */
1681     pmc_for_each_mode(idx, m, pmcdev)
1682         if (mode == m)
1683             break;
1684 
1685     if (mode != m || mode < 0) {
1686         if (sysfs_streq(buf, "clear"))
1687             clear = true;
1688         else if (sysfs_streq(buf, "c10"))
1689             c10 = true;
1690         else
1691             return -EINVAL;
1692     }
1693 
1694     if (clear) {
1695         mutex_lock(&pmcdev->lock);
1696 
1697         reg = pmc_core_reg_read(pmcdev, pmcdev->map->etr3_offset);
1698         reg |= ETR3_CLEAR_LPM_EVENTS;
1699         pmc_core_reg_write(pmcdev, pmcdev->map->etr3_offset, reg);
1700 
1701         mutex_unlock(&pmcdev->lock);
1702 
1703         return count;
1704     }
1705 
1706     if (c10) {
1707         mutex_lock(&pmcdev->lock);
1708 
1709         reg = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_sts_latch_en_offset);
1710         reg &= ~LPM_STS_LATCH_MODE;
1711         pmc_core_reg_write(pmcdev, pmcdev->map->lpm_sts_latch_en_offset, reg);
1712 
1713         mutex_unlock(&pmcdev->lock);
1714 
1715         return count;
1716     }
1717 
1718     /*
1719      * For LPM mode latching we set the latch enable bit and selected mode
1720      * and clear everything else.
1721      */
1722     reg = LPM_STS_LATCH_MODE | BIT(mode);
1723     mutex_lock(&pmcdev->lock);
1724     pmc_core_reg_write(pmcdev, pmcdev->map->lpm_sts_latch_en_offset, reg);
1725     mutex_unlock(&pmcdev->lock);
1726 
1727     return count;
1728 }
1729 DEFINE_PMC_CORE_ATTR_WRITE(pmc_core_lpm_latch_mode);
1730 
1731 static int pmc_core_pkgc_show(struct seq_file *s, void *unused)
1732 {
1733     struct pmc_dev *pmcdev = s->private;
1734     const struct pmc_bit_map *map = pmcdev->map->msr_sts;
1735     u64 pcstate_count;
1736     int index;
1737 
1738     for (index = 0; map[index].name ; index++) {
1739         if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
1740             continue;
1741 
1742         pcstate_count *= 1000;
1743         do_div(pcstate_count, tsc_khz);
1744         seq_printf(s, "%-8s : %llu\n", map[index].name,
1745                pcstate_count);
1746     }
1747 
1748     return 0;
1749 }
1750 DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
1751 
1752 static bool pmc_core_pri_verify(u32 lpm_pri, u8 *mode_order)
1753 {
1754     int i, j;
1755 
1756     if (!lpm_pri)
1757         return false;
1758     /*
1759      * Each byte contains the priority level for 2 modes (7:4 and 3:0).
1760      * In a 32 bit register this allows for describing 8 modes. Store the
1761      * levels and look for values out of range.
1762      */
1763     for (i = 0; i < 8; i++) {
1764         int level = lpm_pri & GENMASK(3, 0);
1765 
1766         if (level >= LPM_MAX_NUM_MODES)
1767             return false;
1768 
1769         mode_order[i] = level;
1770         lpm_pri >>= 4;
1771     }
1772 
1773     /* Check that we have unique values */
1774     for (i = 0; i < LPM_MAX_NUM_MODES - 1; i++)
1775         for (j = i + 1; j < LPM_MAX_NUM_MODES; j++)
1776             if (mode_order[i] == mode_order[j])
1777                 return false;
1778 
1779     return true;
1780 }
1781 
1782 static void pmc_core_get_low_power_modes(struct platform_device *pdev)
1783 {
1784     struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
1785     u8 pri_order[LPM_MAX_NUM_MODES] = LPM_DEFAULT_PRI;
1786     u8 mode_order[LPM_MAX_NUM_MODES];
1787     u32 lpm_pri;
1788     u32 lpm_en;
1789     int mode, i, p;
1790 
1791     /* Use LPM Maps to indicate support for substates */
1792     if (!pmcdev->map->lpm_num_maps)
1793         return;
1794 
1795     lpm_en = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_en_offset);
1796     pmcdev->num_lpm_modes = hweight32(lpm_en);
1797 
1798     /* Read 32 bit LPM_PRI register */
1799     lpm_pri = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_priority_offset);
1800 
1801 
1802     /*
1803      * If lpm_pri value passes verification, then override the default
1804      * modes here. Otherwise stick with the default.
1805      */
1806     if (pmc_core_pri_verify(lpm_pri, mode_order))
1807         /* Get list of modes in priority order */
1808         for (mode = 0; mode < LPM_MAX_NUM_MODES; mode++)
1809             pri_order[mode_order[mode]] = mode;
1810     else
1811         dev_warn(&pdev->dev, "Assuming a default substate order for this platform\n");
1812 
1813     /*
1814      * Loop through all modes from lowest to highest priority,
1815      * and capture all enabled modes in order
1816      */
1817     i = 0;
1818     for (p = LPM_MAX_NUM_MODES - 1; p >= 0; p--) {
1819         int mode = pri_order[p];
1820 
1821         if (!(BIT(mode) & lpm_en))
1822             continue;
1823 
1824         pmcdev->lpm_en_modes[i++] = mode;
1825     }
1826 }
1827 
1828 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
1829 {
1830     debugfs_remove_recursive(pmcdev->dbgfs_dir);
1831 }
1832 
1833 static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
1834 {
1835     struct dentry *dir;
1836 
1837     dir = debugfs_create_dir("pmc_core", NULL);
1838     pmcdev->dbgfs_dir = dir;
1839 
1840     debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
1841                 &pmc_core_dev_state);
1842 
1843     if (pmcdev->map->pfear_sts)
1844         debugfs_create_file("pch_ip_power_gating_status", 0444, dir,
1845                     pmcdev, &pmc_core_ppfear_fops);
1846 
1847     debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
1848                 &pmc_core_ltr_ignore_ops);
1849 
1850     debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
1851 
1852     debugfs_create_file("package_cstate_show", 0444, dir, pmcdev,
1853                 &pmc_core_pkgc_fops);
1854 
1855     if (pmcdev->map->pll_sts)
1856         debugfs_create_file("pll_status", 0444, dir, pmcdev,
1857                     &pmc_core_pll_fops);
1858 
1859     if (pmcdev->map->mphy_sts)
1860         debugfs_create_file("mphy_core_lanes_power_gating_status",
1861                     0444, dir, pmcdev,
1862                     &pmc_core_mphy_pg_fops);
1863 
1864     if (pmcdev->map->slps0_dbg_maps) {
1865         debugfs_create_file("slp_s0_debug_status", 0444,
1866                     dir, pmcdev,
1867                     &pmc_core_slps0_dbg_fops);
1868 
1869         debugfs_create_bool("slp_s0_dbg_latch", 0644,
1870                     dir, &slps0_dbg_latch);
1871     }
1872 
1873     if (pmcdev->map->lpm_en_offset) {
1874         debugfs_create_file("substate_residencies", 0444,
1875                     pmcdev->dbgfs_dir, pmcdev,
1876                     &pmc_core_substate_res_fops);
1877     }
1878 
1879     if (pmcdev->map->lpm_status_offset) {
1880         debugfs_create_file("substate_status_registers", 0444,
1881                     pmcdev->dbgfs_dir, pmcdev,
1882                     &pmc_core_substate_sts_regs_fops);
1883         debugfs_create_file("substate_live_status_registers", 0444,
1884                     pmcdev->dbgfs_dir, pmcdev,
1885                     &pmc_core_substate_l_sts_regs_fops);
1886         debugfs_create_file("lpm_latch_mode", 0644,
1887                     pmcdev->dbgfs_dir, pmcdev,
1888                     &pmc_core_lpm_latch_mode_fops);
1889     }
1890 
1891     if (pmcdev->lpm_req_regs) {
1892         debugfs_create_file("substate_requirements", 0444,
1893                     pmcdev->dbgfs_dir, pmcdev,
1894                     &pmc_core_substate_req_regs_fops);
1895     }
1896 }
1897 
1898 static const struct x86_cpu_id intel_pmc_core_ids[] = {
1899     X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,       &spt_reg_map),
1900     X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,     &spt_reg_map),
1901     X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,      &spt_reg_map),
1902     X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,        &spt_reg_map),
1903     X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L,    &cnp_reg_map),
1904     X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,       &icl_reg_map),
1905     X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI,    &icl_reg_map),
1906     X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE,       &cnp_reg_map),
1907     X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L,     &cnp_reg_map),
1908     X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,     &tgl_reg_map),
1909     X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,       &tgl_reg_map),
1910     X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,    &tgl_reg_map),
1911     X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,  &icl_reg_map),
1912     X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,      &tgl_reg_map),
1913     X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,     &tgl_reg_map),
1914     X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,     &tgl_reg_map),
1915     X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,       &adl_reg_map),
1916     X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        &tgl_reg_map),
1917     {}
1918 };
1919 
1920 MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
1921 
1922 static const struct pci_device_id pmc_pci_ids[] = {
1923     { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) },
1924     { }
1925 };
1926 
1927 /*
1928  * This quirk can be used on those platforms where
1929  * the platform BIOS enforces 24Mhz crystal to shutdown
1930  * before PMC can assert SLP_S0#.
1931  */
1932 static bool xtal_ignore;
1933 static int quirk_xtal_ignore(const struct dmi_system_id *id)
1934 {
1935     xtal_ignore = true;
1936     return 0;
1937 }
1938 
1939 static void pmc_core_xtal_ignore(struct pmc_dev *pmcdev)
1940 {
1941     u32 value;
1942 
1943     value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset);
1944     /* 24MHz Crystal Shutdown Qualification Disable */
1945     value |= SPT_PMC_VRIC1_XTALSDQDIS;
1946     /* Low Voltage Mode Enable */
1947     value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
1948     pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value);
1949 }
1950 
1951 static const struct dmi_system_id pmc_core_dmi_table[]  = {
1952     {
1953     .callback = quirk_xtal_ignore,
1954     .ident = "HP Elite x2 1013 G3",
1955     .matches = {
1956         DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1957         DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"),
1958         },
1959     },
1960     {}
1961 };
1962 
1963 static void pmc_core_do_dmi_quirks(struct pmc_dev *pmcdev)
1964 {
1965     dmi_check_system(pmc_core_dmi_table);
1966 
1967     if (xtal_ignore)
1968         pmc_core_xtal_ignore(pmcdev);
1969 }
1970 
1971 static int pmc_core_probe(struct platform_device *pdev)
1972 {
1973     static bool device_initialized;
1974     struct pmc_dev *pmcdev;
1975     const struct x86_cpu_id *cpu_id;
1976     u64 slp_s0_addr;
1977 
1978     if (device_initialized)
1979         return -ENODEV;
1980 
1981     pmcdev = devm_kzalloc(&pdev->dev, sizeof(*pmcdev), GFP_KERNEL);
1982     if (!pmcdev)
1983         return -ENOMEM;
1984 
1985     platform_set_drvdata(pdev, pmcdev);
1986 
1987     cpu_id = x86_match_cpu(intel_pmc_core_ids);
1988     if (!cpu_id)
1989         return -ENODEV;
1990 
1991     pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
1992 
1993     /*
1994      * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here
1995      * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap
1996      * in this case.
1997      */
1998     if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
1999         pmcdev->map = &cnp_reg_map;
2000 
2001     if (lpit_read_residency_count_address(&slp_s0_addr)) {
2002         pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
2003 
2004         if (page_is_ram(PHYS_PFN(pmcdev->base_addr)))
2005             return -ENODEV;
2006     } else {
2007         pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
2008     }
2009 
2010     pmcdev->regbase = ioremap(pmcdev->base_addr,
2011                   pmcdev->map->regmap_length);
2012     if (!pmcdev->regbase)
2013         return -ENOMEM;
2014 
2015     mutex_init(&pmcdev->lock);
2016 
2017     pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit(pmcdev);
2018     pmc_core_get_low_power_modes(pdev);
2019     pmc_core_do_dmi_quirks(pmcdev);
2020 
2021     if (pmcdev->map == &tgl_reg_map)
2022         pmc_core_get_tgl_lpm_reqs(pdev);
2023 
2024     /*
2025      * On TGL and ADL, due to a hardware limitation, the GBE LTR blocks PC10
2026      * when a cable is attached. Tell the PMC to ignore it.
2027      */
2028     if (pmcdev->map == &tgl_reg_map || pmcdev->map == &adl_reg_map) {
2029         dev_dbg(&pdev->dev, "ignoring GBE LTR\n");
2030         pmc_core_send_ltr_ignore(pmcdev, 3);
2031     }
2032 
2033     pmc_core_dbgfs_register(pmcdev);
2034 
2035     device_initialized = true;
2036     dev_info(&pdev->dev, " initialized\n");
2037 
2038     return 0;
2039 }
2040 
2041 static int pmc_core_remove(struct platform_device *pdev)
2042 {
2043     struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
2044 
2045     pmc_core_dbgfs_unregister(pmcdev);
2046     platform_set_drvdata(pdev, NULL);
2047     mutex_destroy(&pmcdev->lock);
2048     iounmap(pmcdev->regbase);
2049     return 0;
2050 }
2051 
2052 static bool warn_on_s0ix_failures;
2053 module_param(warn_on_s0ix_failures, bool, 0644);
2054 MODULE_PARM_DESC(warn_on_s0ix_failures, "Check and warn for S0ix failures");
2055 
2056 static __maybe_unused int pmc_core_suspend(struct device *dev)
2057 {
2058     struct pmc_dev *pmcdev = dev_get_drvdata(dev);
2059 
2060     pmcdev->check_counters = false;
2061 
2062     /* No warnings on S0ix failures */
2063     if (!warn_on_s0ix_failures)
2064         return 0;
2065 
2066     /* Check if the syspend will actually use S0ix */
2067     if (pm_suspend_via_firmware())
2068         return 0;
2069 
2070     /* Save PC10 residency for checking later */
2071     if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pmcdev->pc10_counter))
2072         return -EIO;
2073 
2074     /* Save S0ix residency for checking later */
2075     if (pmc_core_dev_state_get(pmcdev, &pmcdev->s0ix_counter))
2076         return -EIO;
2077 
2078     pmcdev->check_counters = true;
2079     return 0;
2080 }
2081 
2082 static inline bool pmc_core_is_pc10_failed(struct pmc_dev *pmcdev)
2083 {
2084     u64 pc10_counter;
2085 
2086     if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pc10_counter))
2087         return false;
2088 
2089     if (pc10_counter == pmcdev->pc10_counter)
2090         return true;
2091 
2092     return false;
2093 }
2094 
2095 static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev)
2096 {
2097     u64 s0ix_counter;
2098 
2099     if (pmc_core_dev_state_get(pmcdev, &s0ix_counter))
2100         return false;
2101 
2102     if (s0ix_counter == pmcdev->s0ix_counter)
2103         return true;
2104 
2105     return false;
2106 }
2107 
2108 static __maybe_unused int pmc_core_resume(struct device *dev)
2109 {
2110     struct pmc_dev *pmcdev = dev_get_drvdata(dev);
2111     const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
2112     int offset = pmcdev->map->lpm_status_offset;
2113 
2114     if (!pmcdev->check_counters)
2115         return 0;
2116 
2117     if (!pmc_core_is_s0ix_failed(pmcdev))
2118         return 0;
2119 
2120     if (pmc_core_is_pc10_failed(pmcdev)) {
2121         /* S0ix failed because of PC10 entry failure */
2122         dev_info(dev, "CPU did not enter PC10!!! (PC10 cnt=0x%llx)\n",
2123              pmcdev->pc10_counter);
2124         return 0;
2125     }
2126 
2127     /* The real interesting case - S0ix failed - lets ask PMC why. */
2128     dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=%llu)\n",
2129          pmcdev->s0ix_counter);
2130     if (pmcdev->map->slps0_dbg_maps)
2131         pmc_core_slps0_display(pmcdev, dev, NULL);
2132     if (pmcdev->map->lpm_sts)
2133         pmc_core_lpm_display(pmcdev, dev, NULL, offset, "STATUS", maps);
2134 
2135     return 0;
2136 }
2137 
2138 static const struct dev_pm_ops pmc_core_pm_ops = {
2139     SET_LATE_SYSTEM_SLEEP_PM_OPS(pmc_core_suspend, pmc_core_resume)
2140 };
2141 
2142 static const struct acpi_device_id pmc_core_acpi_ids[] = {
2143     {"INT33A1", 0}, /* _HID for Intel Power Engine, _CID PNP0D80*/
2144     { }
2145 };
2146 MODULE_DEVICE_TABLE(acpi, pmc_core_acpi_ids);
2147 
2148 static struct platform_driver pmc_core_driver = {
2149     .driver = {
2150         .name = "intel_pmc_core",
2151         .acpi_match_table = ACPI_PTR(pmc_core_acpi_ids),
2152         .pm = &pmc_core_pm_ops,
2153         .dev_groups = pmc_dev_groups,
2154     },
2155     .probe = pmc_core_probe,
2156     .remove = pmc_core_remove,
2157 };
2158 
2159 module_platform_driver(pmc_core_driver);
2160 
2161 MODULE_LICENSE("GPL v2");
2162 MODULE_DESCRIPTION("Intel PMC Core Driver");
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