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0001 // SPDX-License-Identifier: GPL-2.0-only OR Linux-OpenIB
0002 /*
0003  * Mellanox BlueField Performance Monitoring Counters driver
0004  *
0005  * This driver provides a sysfs interface for monitoring
0006  * performance statistics in BlueField SoC.
0007  *
0008  * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
0009  */
0010 
0011 #include <linux/acpi.h>
0012 #include <linux/arm-smccc.h>
0013 #include <linux/bitfield.h>
0014 #include <linux/errno.h>
0015 #include <linux/hwmon.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/string.h>
0018 #include <uapi/linux/psci.h>
0019 
0020 #define MLXBF_PMC_WRITE_REG_32 0x82000009
0021 #define MLXBF_PMC_READ_REG_32 0x8200000A
0022 #define MLXBF_PMC_WRITE_REG_64 0x8200000B
0023 #define MLXBF_PMC_READ_REG_64 0x8200000C
0024 #define MLXBF_PMC_SIP_SVC_UID 0x8200ff01
0025 #define MLXBF_PMC_SIP_SVC_VERSION 0x8200ff03
0026 #define MLXBF_PMC_SVC_REQ_MAJOR 0
0027 #define MLXBF_PMC_SVC_MIN_MINOR 3
0028 
0029 #define MLXBF_PMC_SMCCC_ACCESS_VIOLATION -4
0030 
0031 #define MLXBF_PMC_EVENT_SET_BF1 0
0032 #define MLXBF_PMC_EVENT_SET_BF2 1
0033 #define MLXBF_PMC_EVENT_INFO_LEN 100
0034 
0035 #define MLXBF_PMC_MAX_BLOCKS 30
0036 #define MLXBF_PMC_MAX_ATTRS 30
0037 #define MLXBF_PMC_INFO_SZ 4
0038 #define MLXBF_PMC_REG_SIZE 8
0039 #define MLXBF_PMC_L3C_REG_SIZE 4
0040 
0041 #define MLXBF_PMC_TYPE_COUNTER 1
0042 #define MLXBF_PMC_TYPE_REGISTER 0
0043 
0044 #define MLXBF_PMC_PERFCTL 0
0045 #define MLXBF_PMC_PERFEVT 1
0046 #define MLXBF_PMC_PERFACC0 4
0047 
0048 #define MLXBF_PMC_PERFMON_CONFIG_WR_R_B BIT(0)
0049 #define MLXBF_PMC_PERFMON_CONFIG_STROBE BIT(1)
0050 #define MLXBF_PMC_PERFMON_CONFIG_ADDR GENMASK_ULL(4, 2)
0051 #define MLXBF_PMC_PERFMON_CONFIG_WDATA GENMASK_ULL(60, 5)
0052 
0053 #define MLXBF_PMC_PERFCTL_FM0 GENMASK_ULL(18, 16)
0054 #define MLXBF_PMC_PERFCTL_MS0 GENMASK_ULL(21, 20)
0055 #define MLXBF_PMC_PERFCTL_ACCM0 GENMASK_ULL(26, 24)
0056 #define MLXBF_PMC_PERFCTL_AD0 BIT(27)
0057 #define MLXBF_PMC_PERFCTL_ETRIG0 GENMASK_ULL(29, 28)
0058 #define MLXBF_PMC_PERFCTL_EB0 BIT(30)
0059 #define MLXBF_PMC_PERFCTL_EN0 BIT(31)
0060 
0061 #define MLXBF_PMC_PERFEVT_EVTSEL GENMASK_ULL(31, 24)
0062 
0063 #define MLXBF_PMC_L3C_PERF_CNT_CFG 0x0
0064 #define MLXBF_PMC_L3C_PERF_CNT_SEL 0x10
0065 #define MLXBF_PMC_L3C_PERF_CNT_SEL_1 0x14
0066 #define MLXBF_PMC_L3C_PERF_CNT_LOW 0x40
0067 #define MLXBF_PMC_L3C_PERF_CNT_HIGH 0x60
0068 
0069 #define MLXBF_PMC_L3C_PERF_CNT_CFG_EN BIT(0)
0070 #define MLXBF_PMC_L3C_PERF_CNT_CFG_RST BIT(1)
0071 #define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_0 GENMASK(5, 0)
0072 #define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_1 GENMASK(13, 8)
0073 #define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_2 GENMASK(21, 16)
0074 #define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_3 GENMASK(29, 24)
0075 
0076 #define MLXBF_PMC_L3C_PERF_CNT_SEL_1_CNT_4 GENMASK(5, 0)
0077 
0078 #define MLXBF_PMC_L3C_PERF_CNT_LOW_VAL GENMASK(31, 0)
0079 #define MLXBF_PMC_L3C_PERF_CNT_HIGH_VAL GENMASK(24, 0)
0080 
0081 /**
0082  * struct mlxbf_pmc_attribute - Structure to hold attribute and block info
0083  * for each sysfs entry
0084  * @dev_attr: Device attribute struct
0085  * @index: index to identify counter number within a block
0086  * @nr: block number to which the sysfs belongs
0087  */
0088 struct mlxbf_pmc_attribute {
0089     struct device_attribute dev_attr;
0090     int index;
0091     int nr;
0092 };
0093 
0094 /**
0095  * struct mlxbf_pmc_block_info - Structure to hold info for each HW block
0096  *
0097  * @mmio_base: The VA at which the PMC block is mapped
0098  * @blk_size: Size of each mapped region
0099  * @counters: Number of counters in the block
0100  * @type: Type of counters in the block
0101  * @attr_counter: Attributes for "counter" sysfs files
0102  * @attr_event: Attributes for "event" sysfs files
0103  * @attr_event_list: Attributes for "event_list" sysfs files
0104  * @attr_enable: Attributes for "enable" sysfs files
0105  * @block_attr: All attributes needed for the block
0106  * @block_attr_grp: Attribute group for the block
0107  */
0108 struct mlxbf_pmc_block_info {
0109     void __iomem *mmio_base;
0110     size_t blk_size;
0111     size_t counters;
0112     int type;
0113     struct mlxbf_pmc_attribute *attr_counter;
0114     struct mlxbf_pmc_attribute *attr_event;
0115     struct mlxbf_pmc_attribute attr_event_list;
0116     struct mlxbf_pmc_attribute attr_enable;
0117     struct attribute *block_attr[MLXBF_PMC_MAX_ATTRS];
0118     struct attribute_group block_attr_grp;
0119 };
0120 
0121 /**
0122  * struct mlxbf_pmc_context - Structure to hold PMC context info
0123  *
0124  * @pdev: The kernel structure representing the device
0125  * @total_blocks: Total number of blocks
0126  * @tile_count: Number of tiles in the system
0127  * @hwmon_dev: Hwmon device for bfperf
0128  * @block_name: Block name
0129  * @block:  Block info
0130  * @groups:  Attribute groups from each block
0131  * @svc_sreg_support: Whether SMCs are used to access performance registers
0132  * @sreg_tbl_perf: Secure register access table number
0133  * @event_set: Event set to use
0134  */
0135 struct mlxbf_pmc_context {
0136     struct platform_device *pdev;
0137     uint32_t total_blocks;
0138     uint32_t tile_count;
0139     struct device *hwmon_dev;
0140     const char *block_name[MLXBF_PMC_MAX_BLOCKS];
0141     struct mlxbf_pmc_block_info block[MLXBF_PMC_MAX_BLOCKS];
0142     const struct attribute_group *groups[MLXBF_PMC_MAX_BLOCKS];
0143     bool svc_sreg_support;
0144     uint32_t sreg_tbl_perf;
0145     unsigned int event_set;
0146 };
0147 
0148 /**
0149  * struct mlxbf_pmc_events - Structure to hold supported events for each block
0150  * @evt_num: Event number used to program counters
0151  * @evt_name: Name of the event
0152  */
0153 struct mlxbf_pmc_events {
0154     int evt_num;
0155     char *evt_name;
0156 };
0157 
0158 static const struct mlxbf_pmc_events mlxbf_pmc_pcie_events[] = {
0159     { 0x0, "IN_P_PKT_CNT" },
0160     { 0x10, "IN_NP_PKT_CNT" },
0161     { 0x18, "IN_C_PKT_CNT" },
0162     { 0x20, "OUT_P_PKT_CNT" },
0163     { 0x28, "OUT_NP_PKT_CNT" },
0164     { 0x30, "OUT_C_PKT_CNT" },
0165     { 0x38, "IN_P_BYTE_CNT" },
0166     { 0x40, "IN_NP_BYTE_CNT" },
0167     { 0x48, "IN_C_BYTE_CNT" },
0168     { 0x50, "OUT_P_BYTE_CNT" },
0169     { 0x58, "OUT_NP_BYTE_CNT" },
0170     { 0x60, "OUT_C_BYTE_CNT" },
0171 };
0172 
0173 static const struct mlxbf_pmc_events mlxbf_pmc_smgen_events[] = {
0174     { 0x0, "AW_REQ" },
0175     { 0x1, "AW_BEATS" },
0176     { 0x2, "AW_TRANS" },
0177     { 0x3, "AW_RESP" },
0178     { 0x4, "AW_STL" },
0179     { 0x5, "AW_LAT" },
0180     { 0x6, "AW_REQ_TBU" },
0181     { 0x8, "AR_REQ" },
0182     { 0x9, "AR_BEATS" },
0183     { 0xa, "AR_TRANS" },
0184     { 0xb, "AR_STL" },
0185     { 0xc, "AR_LAT" },
0186     { 0xd, "AR_REQ_TBU" },
0187     { 0xe, "TBU_MISS" },
0188     { 0xf, "TX_DAT_AF" },
0189     { 0x10, "RX_DAT_AF" },
0190     { 0x11, "RETRYQ_CRED" },
0191 };
0192 
0193 static const struct mlxbf_pmc_events mlxbf_pmc_trio_events_1[] = {
0194     { 0xa0, "TPIO_DATA_BEAT" },
0195     { 0xa1, "TDMA_DATA_BEAT" },
0196     { 0xa2, "MAP_DATA_BEAT" },
0197     { 0xa3, "TXMSG_DATA_BEAT" },
0198     { 0xa4, "TPIO_DATA_PACKET" },
0199     { 0xa5, "TDMA_DATA_PACKET" },
0200     { 0xa6, "MAP_DATA_PACKET" },
0201     { 0xa7, "TXMSG_DATA_PACKET" },
0202     { 0xa8, "TDMA_RT_AF" },
0203     { 0xa9, "TDMA_PBUF_MAC_AF" },
0204     { 0xaa, "TRIO_MAP_WRQ_BUF_EMPTY" },
0205     { 0xab, "TRIO_MAP_CPL_BUF_EMPTY" },
0206     { 0xac, "TRIO_MAP_RDQ0_BUF_EMPTY" },
0207     { 0xad, "TRIO_MAP_RDQ1_BUF_EMPTY" },
0208     { 0xae, "TRIO_MAP_RDQ2_BUF_EMPTY" },
0209     { 0xaf, "TRIO_MAP_RDQ3_BUF_EMPTY" },
0210     { 0xb0, "TRIO_MAP_RDQ4_BUF_EMPTY" },
0211     { 0xb1, "TRIO_MAP_RDQ5_BUF_EMPTY" },
0212     { 0xb2, "TRIO_MAP_RDQ6_BUF_EMPTY" },
0213     { 0xb3, "TRIO_MAP_RDQ7_BUF_EMPTY" },
0214 };
0215 
0216 static const struct mlxbf_pmc_events mlxbf_pmc_trio_events_2[] = {
0217     { 0xa0, "TPIO_DATA_BEAT" },
0218     { 0xa1, "TDMA_DATA_BEAT" },
0219     { 0xa2, "MAP_DATA_BEAT" },
0220     { 0xa3, "TXMSG_DATA_BEAT" },
0221     { 0xa4, "TPIO_DATA_PACKET" },
0222     { 0xa5, "TDMA_DATA_PACKET" },
0223     { 0xa6, "MAP_DATA_PACKET" },
0224     { 0xa7, "TXMSG_DATA_PACKET" },
0225     { 0xa8, "TDMA_RT_AF" },
0226     { 0xa9, "TDMA_PBUF_MAC_AF" },
0227     { 0xaa, "TRIO_MAP_WRQ_BUF_EMPTY" },
0228     { 0xab, "TRIO_MAP_CPL_BUF_EMPTY" },
0229     { 0xac, "TRIO_MAP_RDQ0_BUF_EMPTY" },
0230     { 0xad, "TRIO_MAP_RDQ1_BUF_EMPTY" },
0231     { 0xae, "TRIO_MAP_RDQ2_BUF_EMPTY" },
0232     { 0xaf, "TRIO_MAP_RDQ3_BUF_EMPTY" },
0233     { 0xb0, "TRIO_MAP_RDQ4_BUF_EMPTY" },
0234     { 0xb1, "TRIO_MAP_RDQ5_BUF_EMPTY" },
0235     { 0xb2, "TRIO_MAP_RDQ6_BUF_EMPTY" },
0236     { 0xb3, "TRIO_MAP_RDQ7_BUF_EMPTY" },
0237     { 0xb4, "TRIO_RING_TX_FLIT_CH0" },
0238     { 0xb5, "TRIO_RING_TX_FLIT_CH1" },
0239     { 0xb6, "TRIO_RING_TX_FLIT_CH2" },
0240     { 0xb7, "TRIO_RING_TX_FLIT_CH3" },
0241     { 0xb8, "TRIO_RING_TX_FLIT_CH4" },
0242     { 0xb9, "TRIO_RING_RX_FLIT_CH0" },
0243     { 0xba, "TRIO_RING_RX_FLIT_CH1" },
0244     { 0xbb, "TRIO_RING_RX_FLIT_CH2" },
0245     { 0xbc, "TRIO_RING_RX_FLIT_CH3" },
0246 };
0247 
0248 static const struct mlxbf_pmc_events mlxbf_pmc_ecc_events[] = {
0249     { 0x100, "ECC_SINGLE_ERROR_CNT" },
0250     { 0x104, "ECC_DOUBLE_ERROR_CNT" },
0251     { 0x114, "SERR_INJ" },
0252     { 0x118, "DERR_INJ" },
0253     { 0x124, "ECC_SINGLE_ERROR_0" },
0254     { 0x164, "ECC_DOUBLE_ERROR_0" },
0255     { 0x340, "DRAM_ECC_COUNT" },
0256     { 0x344, "DRAM_ECC_INJECT" },
0257     { 0x348, "DRAM_ECC_ERROR" },
0258 };
0259 
0260 static const struct mlxbf_pmc_events mlxbf_pmc_mss_events[] = {
0261     { 0xc0, "RXREQ_MSS" },
0262     { 0xc1, "RXDAT_MSS" },
0263     { 0xc2, "TXRSP_MSS" },
0264     { 0xc3, "TXDAT_MSS" },
0265 };
0266 
0267 static const struct mlxbf_pmc_events mlxbf_pmc_hnf_events[] = {
0268     { 0x45, "HNF_REQUESTS" },
0269     { 0x46, "HNF_REJECTS" },
0270     { 0x47, "ALL_BUSY" },
0271     { 0x48, "MAF_BUSY" },
0272     { 0x49, "MAF_REQUESTS" },
0273     { 0x4a, "RNF_REQUESTS" },
0274     { 0x4b, "REQUEST_TYPE" },
0275     { 0x4c, "MEMORY_READS" },
0276     { 0x4d, "MEMORY_WRITES" },
0277     { 0x4e, "VICTIM_WRITE" },
0278     { 0x4f, "POC_FULL" },
0279     { 0x50, "POC_FAIL" },
0280     { 0x51, "POC_SUCCESS" },
0281     { 0x52, "POC_WRITES" },
0282     { 0x53, "POC_READS" },
0283     { 0x54, "FORWARD" },
0284     { 0x55, "RXREQ_HNF" },
0285     { 0x56, "RXRSP_HNF" },
0286     { 0x57, "RXDAT_HNF" },
0287     { 0x58, "TXREQ_HNF" },
0288     { 0x59, "TXRSP_HNF" },
0289     { 0x5a, "TXDAT_HNF" },
0290     { 0x5b, "TXSNP_HNF" },
0291     { 0x5c, "INDEX_MATCH" },
0292     { 0x5d, "A72_ACCESS" },
0293     { 0x5e, "IO_ACCESS" },
0294     { 0x5f, "TSO_WRITE" },
0295     { 0x60, "TSO_CONFLICT" },
0296     { 0x61, "DIR_HIT" },
0297     { 0x62, "HNF_ACCEPTS" },
0298     { 0x63, "REQ_BUF_EMPTY" },
0299     { 0x64, "REQ_BUF_IDLE_MAF" },
0300     { 0x65, "TSO_NOARB" },
0301     { 0x66, "TSO_NOARB_CYCLES" },
0302     { 0x67, "MSS_NO_CREDIT" },
0303     { 0x68, "TXDAT_NO_LCRD" },
0304     { 0x69, "TXSNP_NO_LCRD" },
0305     { 0x6a, "TXRSP_NO_LCRD" },
0306     { 0x6b, "TXREQ_NO_LCRD" },
0307     { 0x6c, "TSO_CL_MATCH" },
0308     { 0x6d, "MEMORY_READS_BYPASS" },
0309     { 0x6e, "TSO_NOARB_TIMEOUT" },
0310     { 0x6f, "ALLOCATE" },
0311     { 0x70, "VICTIM" },
0312     { 0x71, "A72_WRITE" },
0313     { 0x72, "A72_READ" },
0314     { 0x73, "IO_WRITE" },
0315     { 0x74, "IO_READ" },
0316     { 0x75, "TSO_REJECT" },
0317     { 0x80, "TXREQ_RN" },
0318     { 0x81, "TXRSP_RN" },
0319     { 0x82, "TXDAT_RN" },
0320     { 0x83, "RXSNP_RN" },
0321     { 0x84, "RXRSP_RN" },
0322     { 0x85, "RXDAT_RN" },
0323 };
0324 
0325 static const struct mlxbf_pmc_events mlxbf_pmc_hnfnet_events[] = {
0326     { 0x12, "CDN_REQ" },
0327     { 0x13, "DDN_REQ" },
0328     { 0x14, "NDN_REQ" },
0329     { 0x15, "CDN_DIAG_N_OUT_OF_CRED" },
0330     { 0x16, "CDN_DIAG_S_OUT_OF_CRED" },
0331     { 0x17, "CDN_DIAG_E_OUT_OF_CRED" },
0332     { 0x18, "CDN_DIAG_W_OUT_OF_CRED" },
0333     { 0x19, "CDN_DIAG_C_OUT_OF_CRED" },
0334     { 0x1a, "CDN_DIAG_N_EGRESS" },
0335     { 0x1b, "CDN_DIAG_S_EGRESS" },
0336     { 0x1c, "CDN_DIAG_E_EGRESS" },
0337     { 0x1d, "CDN_DIAG_W_EGRESS" },
0338     { 0x1e, "CDN_DIAG_C_EGRESS" },
0339     { 0x1f, "CDN_DIAG_N_INGRESS" },
0340     { 0x20, "CDN_DIAG_S_INGRESS" },
0341     { 0x21, "CDN_DIAG_E_INGRESS" },
0342     { 0x22, "CDN_DIAG_W_INGRESS" },
0343     { 0x23, "CDN_DIAG_C_INGRESS" },
0344     { 0x24, "CDN_DIAG_CORE_SENT" },
0345     { 0x25, "DDN_DIAG_N_OUT_OF_CRED" },
0346     { 0x26, "DDN_DIAG_S_OUT_OF_CRED" },
0347     { 0x27, "DDN_DIAG_E_OUT_OF_CRED" },
0348     { 0x28, "DDN_DIAG_W_OUT_OF_CRED" },
0349     { 0x29, "DDN_DIAG_C_OUT_OF_CRED" },
0350     { 0x2a, "DDN_DIAG_N_EGRESS" },
0351     { 0x2b, "DDN_DIAG_S_EGRESS" },
0352     { 0x2c, "DDN_DIAG_E_EGRESS" },
0353     { 0x2d, "DDN_DIAG_W_EGRESS" },
0354     { 0x2e, "DDN_DIAG_C_EGRESS" },
0355     { 0x2f, "DDN_DIAG_N_INGRESS" },
0356     { 0x30, "DDN_DIAG_S_INGRESS" },
0357     { 0x31, "DDN_DIAG_E_INGRESS" },
0358     { 0x32, "DDN_DIAG_W_INGRESS" },
0359     { 0x33, "DDN_DIAG_C_INGRESS" },
0360     { 0x34, "DDN_DIAG_CORE_SENT" },
0361     { 0x35, "NDN_DIAG_S_OUT_OF_CRED" },
0362     { 0x36, "NDN_DIAG_S_OUT_OF_CRED" },
0363     { 0x37, "NDN_DIAG_E_OUT_OF_CRED" },
0364     { 0x38, "NDN_DIAG_W_OUT_OF_CRED" },
0365     { 0x39, "NDN_DIAG_C_OUT_OF_CRED" },
0366     { 0x3a, "NDN_DIAG_N_EGRESS" },
0367     { 0x3b, "NDN_DIAG_S_EGRESS" },
0368     { 0x3c, "NDN_DIAG_E_EGRESS" },
0369     { 0x3d, "NDN_DIAG_W_EGRESS" },
0370     { 0x3e, "NDN_DIAG_C_EGRESS" },
0371     { 0x3f, "NDN_DIAG_N_INGRESS" },
0372     { 0x40, "NDN_DIAG_S_INGRESS" },
0373     { 0x41, "NDN_DIAG_E_INGRESS" },
0374     { 0x42, "NDN_DIAG_W_INGRESS" },
0375     { 0x43, "NDN_DIAG_C_INGRESS" },
0376     { 0x44, "NDN_DIAG_CORE_SENT" },
0377 };
0378 
0379 static const struct mlxbf_pmc_events mlxbf_pmc_l3c_events[] = {
0380     { 0x00, "DISABLE" },
0381     { 0x01, "CYCLES" },
0382     { 0x02, "TOTAL_RD_REQ_IN" },
0383     { 0x03, "TOTAL_WR_REQ_IN" },
0384     { 0x04, "TOTAL_WR_DBID_ACK" },
0385     { 0x05, "TOTAL_WR_DATA_IN" },
0386     { 0x06, "TOTAL_WR_COMP" },
0387     { 0x07, "TOTAL_RD_DATA_OUT" },
0388     { 0x08, "TOTAL_CDN_REQ_IN_BANK0" },
0389     { 0x09, "TOTAL_CDN_REQ_IN_BANK1" },
0390     { 0x0a, "TOTAL_DDN_REQ_IN_BANK0" },
0391     { 0x0b, "TOTAL_DDN_REQ_IN_BANK1" },
0392     { 0x0c, "TOTAL_EMEM_RD_RES_IN_BANK0" },
0393     { 0x0d, "TOTAL_EMEM_RD_RES_IN_BANK1" },
0394     { 0x0e, "TOTAL_CACHE_RD_RES_IN_BANK0" },
0395     { 0x0f, "TOTAL_CACHE_RD_RES_IN_BANK1" },
0396     { 0x10, "TOTAL_EMEM_RD_REQ_BANK0" },
0397     { 0x11, "TOTAL_EMEM_RD_REQ_BANK1" },
0398     { 0x12, "TOTAL_EMEM_WR_REQ_BANK0" },
0399     { 0x13, "TOTAL_EMEM_WR_REQ_BANK1" },
0400     { 0x14, "TOTAL_RD_REQ_OUT" },
0401     { 0x15, "TOTAL_WR_REQ_OUT" },
0402     { 0x16, "TOTAL_RD_RES_IN" },
0403     { 0x17, "HITS_BANK0" },
0404     { 0x18, "HITS_BANK1" },
0405     { 0x19, "MISSES_BANK0" },
0406     { 0x1a, "MISSES_BANK1" },
0407     { 0x1b, "ALLOCATIONS_BANK0" },
0408     { 0x1c, "ALLOCATIONS_BANK1" },
0409     { 0x1d, "EVICTIONS_BANK0" },
0410     { 0x1e, "EVICTIONS_BANK1" },
0411     { 0x1f, "DBID_REJECT" },
0412     { 0x20, "WRDB_REJECT_BANK0" },
0413     { 0x21, "WRDB_REJECT_BANK1" },
0414     { 0x22, "CMDQ_REJECT_BANK0" },
0415     { 0x23, "CMDQ_REJECT_BANK1" },
0416     { 0x24, "COB_REJECT_BANK0" },
0417     { 0x25, "COB_REJECT_BANK1" },
0418     { 0x26, "TRB_REJECT_BANK0" },
0419     { 0x27, "TRB_REJECT_BANK1" },
0420     { 0x28, "TAG_REJECT_BANK0" },
0421     { 0x29, "TAG_REJECT_BANK1" },
0422     { 0x2a, "ANY_REJECT_BANK0" },
0423     { 0x2b, "ANY_REJECT_BANK1" },
0424 };
0425 
0426 static struct mlxbf_pmc_context *pmc;
0427 
0428 /* UUID used to probe ATF service. */
0429 static const char *mlxbf_pmc_svc_uuid_str = "89c036b4-e7d7-11e6-8797-001aca00bfc4";
0430 
0431 /* Calls an SMC to access a performance register */
0432 static int mlxbf_pmc_secure_read(void __iomem *addr, uint32_t command,
0433                  uint64_t *result)
0434 {
0435     struct arm_smccc_res res;
0436     int status, err = 0;
0437 
0438     arm_smccc_smc(command, pmc->sreg_tbl_perf, (uintptr_t)addr, 0, 0, 0, 0,
0439               0, &res);
0440 
0441     status = res.a0;
0442 
0443     switch (status) {
0444     case PSCI_RET_NOT_SUPPORTED:
0445         err = -EINVAL;
0446         break;
0447     case MLXBF_PMC_SMCCC_ACCESS_VIOLATION:
0448         err = -EACCES;
0449         break;
0450     default:
0451         *result = res.a1;
0452         break;
0453     }
0454 
0455     return err;
0456 }
0457 
0458 /* Read from a performance counter */
0459 static int mlxbf_pmc_read(void __iomem *addr, uint32_t command,
0460               uint64_t *result)
0461 {
0462     if (pmc->svc_sreg_support)
0463         return mlxbf_pmc_secure_read(addr, command, result);
0464 
0465     if (command == MLXBF_PMC_READ_REG_32)
0466         *result = readl(addr);
0467     else
0468         *result = readq(addr);
0469 
0470     return 0;
0471 }
0472 
0473 /* Convenience function for 32-bit reads */
0474 static int mlxbf_pmc_readl(void __iomem *addr, uint32_t *result)
0475 {
0476     uint64_t read_out;
0477     int status;
0478 
0479     status = mlxbf_pmc_read(addr, MLXBF_PMC_READ_REG_32, &read_out);
0480     if (status)
0481         return status;
0482     *result = (uint32_t)read_out;
0483 
0484     return 0;
0485 }
0486 
0487 /* Calls an SMC to access a performance register */
0488 static int mlxbf_pmc_secure_write(void __iomem *addr, uint32_t command,
0489                   uint64_t value)
0490 {
0491     struct arm_smccc_res res;
0492     int status, err = 0;
0493 
0494     arm_smccc_smc(command, pmc->sreg_tbl_perf, value, (uintptr_t)addr, 0, 0,
0495               0, 0, &res);
0496 
0497     status = res.a0;
0498 
0499     switch (status) {
0500     case PSCI_RET_NOT_SUPPORTED:
0501         err = -EINVAL;
0502         break;
0503     case MLXBF_PMC_SMCCC_ACCESS_VIOLATION:
0504         err = -EACCES;
0505         break;
0506     }
0507 
0508     return err;
0509 }
0510 
0511 /* Write to a performance counter */
0512 static int mlxbf_pmc_write(void __iomem *addr, int command, uint64_t value)
0513 {
0514     if (pmc->svc_sreg_support)
0515         return mlxbf_pmc_secure_write(addr, command, value);
0516 
0517     if (command == MLXBF_PMC_WRITE_REG_32)
0518         writel(value, addr);
0519     else
0520         writeq(value, addr);
0521 
0522     return 0;
0523 }
0524 
0525 /* Check if the register offset is within the mapped region for the block */
0526 static bool mlxbf_pmc_valid_range(int blk_num, uint32_t offset)
0527 {
0528     if ((offset >= 0) && !(offset % MLXBF_PMC_REG_SIZE) &&
0529         (offset + MLXBF_PMC_REG_SIZE <= pmc->block[blk_num].blk_size))
0530         return true; /* inside the mapped PMC space */
0531 
0532     return false;
0533 }
0534 
0535 /* Get the event list corresponding to a certain block */
0536 static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk,
0537                                int *size)
0538 {
0539     const struct mlxbf_pmc_events *events;
0540 
0541     if (strstr(blk, "tilenet")) {
0542         events = mlxbf_pmc_hnfnet_events;
0543         *size = ARRAY_SIZE(mlxbf_pmc_hnfnet_events);
0544     } else if (strstr(blk, "tile")) {
0545         events = mlxbf_pmc_hnf_events;
0546         *size = ARRAY_SIZE(mlxbf_pmc_hnf_events);
0547     } else if (strstr(blk, "triogen")) {
0548         events = mlxbf_pmc_smgen_events;
0549         *size = ARRAY_SIZE(mlxbf_pmc_smgen_events);
0550     } else if (strstr(blk, "trio")) {
0551         switch (pmc->event_set) {
0552         case MLXBF_PMC_EVENT_SET_BF1:
0553             events = mlxbf_pmc_trio_events_1;
0554             *size = ARRAY_SIZE(mlxbf_pmc_trio_events_1);
0555             break;
0556         case MLXBF_PMC_EVENT_SET_BF2:
0557             events = mlxbf_pmc_trio_events_2;
0558             *size = ARRAY_SIZE(mlxbf_pmc_trio_events_2);
0559             break;
0560         default:
0561             events = NULL;
0562             *size = 0;
0563             break;
0564         }
0565     } else if (strstr(blk, "mss")) {
0566         events = mlxbf_pmc_mss_events;
0567         *size = ARRAY_SIZE(mlxbf_pmc_mss_events);
0568     } else if (strstr(blk, "ecc")) {
0569         events = mlxbf_pmc_ecc_events;
0570         *size = ARRAY_SIZE(mlxbf_pmc_ecc_events);
0571     } else if (strstr(blk, "pcie")) {
0572         events = mlxbf_pmc_pcie_events;
0573         *size = ARRAY_SIZE(mlxbf_pmc_pcie_events);
0574     } else if (strstr(blk, "l3cache")) {
0575         events = mlxbf_pmc_l3c_events;
0576         *size = ARRAY_SIZE(mlxbf_pmc_l3c_events);
0577     } else if (strstr(blk, "gic")) {
0578         events = mlxbf_pmc_smgen_events;
0579         *size = ARRAY_SIZE(mlxbf_pmc_smgen_events);
0580     } else if (strstr(blk, "smmu")) {
0581         events = mlxbf_pmc_smgen_events;
0582         *size = ARRAY_SIZE(mlxbf_pmc_smgen_events);
0583     } else {
0584         events = NULL;
0585         *size = 0;
0586     }
0587 
0588     return events;
0589 }
0590 
0591 /* Get the event number given the name */
0592 static int mlxbf_pmc_get_event_num(const char *blk, const char *evt)
0593 {
0594     const struct mlxbf_pmc_events *events;
0595     int i, size;
0596 
0597     events = mlxbf_pmc_event_list(blk, &size);
0598     if (!events)
0599         return -EINVAL;
0600 
0601     for (i = 0; i < size; ++i) {
0602         if (!strcmp(evt, events[i].evt_name))
0603             return events[i].evt_num;
0604     }
0605 
0606     return -ENODEV;
0607 }
0608 
0609 /* Get the event number given the name */
0610 static char *mlxbf_pmc_get_event_name(const char *blk, int evt)
0611 {
0612     const struct mlxbf_pmc_events *events;
0613     int i, size;
0614 
0615     events = mlxbf_pmc_event_list(blk, &size);
0616     if (!events)
0617         return NULL;
0618 
0619     for (i = 0; i < size; ++i) {
0620         if (evt == events[i].evt_num)
0621             return events[i].evt_name;
0622     }
0623 
0624     return NULL;
0625 }
0626 
0627 /* Method to enable/disable/reset l3cache counters */
0628 static int mlxbf_pmc_config_l3_counters(int blk_num, bool enable, bool reset)
0629 {
0630     uint32_t perfcnt_cfg = 0;
0631 
0632     if (enable)
0633         perfcnt_cfg |= MLXBF_PMC_L3C_PERF_CNT_CFG_EN;
0634     if (reset)
0635         perfcnt_cfg |= MLXBF_PMC_L3C_PERF_CNT_CFG_RST;
0636 
0637     return mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
0638                        MLXBF_PMC_L3C_PERF_CNT_CFG,
0639                    MLXBF_PMC_WRITE_REG_32, perfcnt_cfg);
0640 }
0641 
0642 /* Method to handle l3cache counter programming */
0643 static int mlxbf_pmc_program_l3_counter(int blk_num, uint32_t cnt_num,
0644                     uint32_t evt)
0645 {
0646     uint32_t perfcnt_sel_1 = 0;
0647     uint32_t perfcnt_sel = 0;
0648     uint32_t *wordaddr;
0649     void __iomem *pmcaddr;
0650     int ret;
0651 
0652     /* Disable all counters before programming them */
0653     if (mlxbf_pmc_config_l3_counters(blk_num, false, false))
0654         return -EINVAL;
0655 
0656     /* Select appropriate register information */
0657     switch (cnt_num) {
0658     case 0 ... 3:
0659         pmcaddr = pmc->block[blk_num].mmio_base +
0660               MLXBF_PMC_L3C_PERF_CNT_SEL;
0661         wordaddr = &perfcnt_sel;
0662         break;
0663     case 4:
0664         pmcaddr = pmc->block[blk_num].mmio_base +
0665               MLXBF_PMC_L3C_PERF_CNT_SEL_1;
0666         wordaddr = &perfcnt_sel_1;
0667         break;
0668     default:
0669         return -EINVAL;
0670     }
0671 
0672     ret = mlxbf_pmc_readl(pmcaddr, wordaddr);
0673     if (ret)
0674         return ret;
0675 
0676     switch (cnt_num) {
0677     case 0:
0678         perfcnt_sel &= ~MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_0;
0679         perfcnt_sel |= FIELD_PREP(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_0,
0680                       evt);
0681         break;
0682     case 1:
0683         perfcnt_sel &= ~MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_1;
0684         perfcnt_sel |= FIELD_PREP(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_1,
0685                       evt);
0686         break;
0687     case 2:
0688         perfcnt_sel &= ~MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_2;
0689         perfcnt_sel |= FIELD_PREP(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_2,
0690                       evt);
0691         break;
0692     case 3:
0693         perfcnt_sel &= ~MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_3;
0694         perfcnt_sel |= FIELD_PREP(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_3,
0695                       evt);
0696         break;
0697     case 4:
0698         perfcnt_sel_1 &= ~MLXBF_PMC_L3C_PERF_CNT_SEL_1_CNT_4;
0699         perfcnt_sel_1 |= FIELD_PREP(MLXBF_PMC_L3C_PERF_CNT_SEL_1_CNT_4,
0700                         evt);
0701         break;
0702     default:
0703         return -EINVAL;
0704     }
0705 
0706     return mlxbf_pmc_write(pmcaddr, MLXBF_PMC_WRITE_REG_32, *wordaddr);
0707 }
0708 
0709 /* Method to program a counter to monitor an event */
0710 static int mlxbf_pmc_program_counter(int blk_num, uint32_t cnt_num,
0711                      uint32_t evt, bool is_l3)
0712 {
0713     uint64_t perfctl, perfevt, perfmon_cfg;
0714 
0715     if (cnt_num >= pmc->block[blk_num].counters)
0716         return -ENODEV;
0717 
0718     if (is_l3)
0719         return mlxbf_pmc_program_l3_counter(blk_num, cnt_num, evt);
0720 
0721     /* Configure the counter */
0722     perfctl = FIELD_PREP(MLXBF_PMC_PERFCTL_EN0, 1);
0723     perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_EB0, 0);
0724     perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_ETRIG0, 1);
0725     perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_AD0, 0);
0726     perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_ACCM0, 0);
0727     perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_MS0, 0);
0728     perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_FM0, 0);
0729 
0730     perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WDATA, perfctl);
0731     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
0732                   MLXBF_PMC_PERFCTL);
0733     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
0734     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 1);
0735 
0736     if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
0737                     cnt_num * MLXBF_PMC_REG_SIZE,
0738                 MLXBF_PMC_WRITE_REG_64, perfmon_cfg))
0739         return -EFAULT;
0740 
0741     /* Select the event */
0742     perfevt = FIELD_PREP(MLXBF_PMC_PERFEVT_EVTSEL, evt);
0743 
0744     perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WDATA, perfevt);
0745     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
0746                   MLXBF_PMC_PERFEVT);
0747     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
0748     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 1);
0749 
0750     if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
0751                     cnt_num * MLXBF_PMC_REG_SIZE,
0752                 MLXBF_PMC_WRITE_REG_64, perfmon_cfg))
0753         return -EFAULT;
0754 
0755     /* Clear the accumulator */
0756     perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
0757                  MLXBF_PMC_PERFACC0);
0758     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
0759     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 1);
0760 
0761     if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
0762                     cnt_num * MLXBF_PMC_REG_SIZE,
0763                 MLXBF_PMC_WRITE_REG_64, perfmon_cfg))
0764         return -EFAULT;
0765 
0766     return 0;
0767 }
0768 
0769 /* Method to handle l3 counter reads */
0770 static int mlxbf_pmc_read_l3_counter(int blk_num, uint32_t cnt_num,
0771                      uint64_t *result)
0772 {
0773     uint32_t perfcnt_low = 0, perfcnt_high = 0;
0774     uint64_t value;
0775     int status = 0;
0776 
0777     status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
0778                      MLXBF_PMC_L3C_PERF_CNT_LOW +
0779                      cnt_num * MLXBF_PMC_L3C_REG_SIZE,
0780                  &perfcnt_low);
0781 
0782     if (status)
0783         return status;
0784 
0785     status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
0786                      MLXBF_PMC_L3C_PERF_CNT_HIGH +
0787                      cnt_num * MLXBF_PMC_L3C_REG_SIZE,
0788                  &perfcnt_high);
0789 
0790     if (status)
0791         return status;
0792 
0793     value = perfcnt_high;
0794     value = value << 32;
0795     value |= perfcnt_low;
0796     *result = value;
0797 
0798     return 0;
0799 }
0800 
0801 /* Method to read the counter value */
0802 static int mlxbf_pmc_read_counter(int blk_num, uint32_t cnt_num, bool is_l3,
0803                   uint64_t *result)
0804 {
0805     uint32_t perfcfg_offset, perfval_offset;
0806     uint64_t perfmon_cfg;
0807     int status;
0808 
0809     if (cnt_num >= pmc->block[blk_num].counters)
0810         return -EINVAL;
0811 
0812     if (is_l3)
0813         return mlxbf_pmc_read_l3_counter(blk_num, cnt_num, result);
0814 
0815     perfcfg_offset = cnt_num * MLXBF_PMC_REG_SIZE;
0816     perfval_offset = perfcfg_offset +
0817              pmc->block[blk_num].counters * MLXBF_PMC_REG_SIZE;
0818 
0819     /* Set counter in "read" mode */
0820     perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
0821                  MLXBF_PMC_PERFACC0);
0822     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
0823     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 0);
0824 
0825     status = mlxbf_pmc_write(pmc->block[blk_num].mmio_base + perfcfg_offset,
0826                  MLXBF_PMC_WRITE_REG_64, perfmon_cfg);
0827 
0828     if (status)
0829         return status;
0830 
0831     /* Get the counter value */
0832     return mlxbf_pmc_read(pmc->block[blk_num].mmio_base + perfval_offset,
0833                   MLXBF_PMC_READ_REG_64, result);
0834 }
0835 
0836 /* Method to read L3 block event */
0837 static int mlxbf_pmc_read_l3_event(int blk_num, uint32_t cnt_num,
0838                    uint64_t *result)
0839 {
0840     uint32_t perfcnt_sel = 0, perfcnt_sel_1 = 0;
0841     uint32_t *wordaddr;
0842     void __iomem *pmcaddr;
0843     uint64_t evt;
0844 
0845     /* Select appropriate register information */
0846     switch (cnt_num) {
0847     case 0 ... 3:
0848         pmcaddr = pmc->block[blk_num].mmio_base +
0849               MLXBF_PMC_L3C_PERF_CNT_SEL;
0850         wordaddr = &perfcnt_sel;
0851         break;
0852     case 4:
0853         pmcaddr = pmc->block[blk_num].mmio_base +
0854               MLXBF_PMC_L3C_PERF_CNT_SEL_1;
0855         wordaddr = &perfcnt_sel_1;
0856         break;
0857     default:
0858         return -EINVAL;
0859     }
0860 
0861     if (mlxbf_pmc_readl(pmcaddr, wordaddr))
0862         return -EINVAL;
0863 
0864     /* Read from appropriate register field for the counter */
0865     switch (cnt_num) {
0866     case 0:
0867         evt = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_0, perfcnt_sel);
0868         break;
0869     case 1:
0870         evt = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_1, perfcnt_sel);
0871         break;
0872     case 2:
0873         evt = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_2, perfcnt_sel);
0874         break;
0875     case 3:
0876         evt = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_3, perfcnt_sel);
0877         break;
0878     case 4:
0879         evt = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_SEL_1_CNT_4,
0880                 perfcnt_sel_1);
0881         break;
0882     default:
0883         return -EINVAL;
0884     }
0885     *result = evt;
0886 
0887     return 0;
0888 }
0889 
0890 /* Method to find the event currently being monitored by a counter */
0891 static int mlxbf_pmc_read_event(int blk_num, uint32_t cnt_num, bool is_l3,
0892                 uint64_t *result)
0893 {
0894     uint32_t perfcfg_offset, perfval_offset;
0895     uint64_t perfmon_cfg, perfevt, perfctl;
0896 
0897     if (cnt_num >= pmc->block[blk_num].counters)
0898         return -EINVAL;
0899 
0900     if (is_l3)
0901         return mlxbf_pmc_read_l3_event(blk_num, cnt_num, result);
0902 
0903     perfcfg_offset = cnt_num * MLXBF_PMC_REG_SIZE;
0904     perfval_offset = perfcfg_offset +
0905              pmc->block[blk_num].counters * MLXBF_PMC_REG_SIZE;
0906 
0907     /* Set counter in "read" mode */
0908     perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
0909                  MLXBF_PMC_PERFCTL);
0910     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
0911     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 0);
0912 
0913     if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + perfcfg_offset,
0914                 MLXBF_PMC_WRITE_REG_64, perfmon_cfg))
0915         return -EFAULT;
0916 
0917     /* Check if the counter is enabled */
0918 
0919     if (mlxbf_pmc_read(pmc->block[blk_num].mmio_base + perfval_offset,
0920                MLXBF_PMC_READ_REG_64, &perfctl))
0921         return -EFAULT;
0922 
0923     if (!FIELD_GET(MLXBF_PMC_PERFCTL_EN0, perfctl))
0924         return -EINVAL;
0925 
0926     /* Set counter in "read" mode */
0927     perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
0928                  MLXBF_PMC_PERFEVT);
0929     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
0930     perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 0);
0931 
0932     if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + perfcfg_offset,
0933                 MLXBF_PMC_WRITE_REG_64, perfmon_cfg))
0934         return -EFAULT;
0935 
0936     /* Get the event number */
0937     if (mlxbf_pmc_read(pmc->block[blk_num].mmio_base + perfval_offset,
0938                MLXBF_PMC_READ_REG_64, &perfevt))
0939         return -EFAULT;
0940 
0941     *result = FIELD_GET(MLXBF_PMC_PERFEVT_EVTSEL, perfevt);
0942 
0943     return 0;
0944 }
0945 
0946 /* Method to read a register */
0947 static int mlxbf_pmc_read_reg(int blk_num, uint32_t offset, uint64_t *result)
0948 {
0949     uint32_t ecc_out;
0950 
0951     if (strstr(pmc->block_name[blk_num], "ecc")) {
0952         if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset,
0953                     &ecc_out))
0954             return -EFAULT;
0955 
0956         *result = ecc_out;
0957         return 0;
0958     }
0959 
0960     if (mlxbf_pmc_valid_range(blk_num, offset))
0961         return mlxbf_pmc_read(pmc->block[blk_num].mmio_base + offset,
0962                       MLXBF_PMC_READ_REG_64, result);
0963 
0964     return -EINVAL;
0965 }
0966 
0967 /* Method to write to a register */
0968 static int mlxbf_pmc_write_reg(int blk_num, uint32_t offset, uint64_t data)
0969 {
0970     if (strstr(pmc->block_name[blk_num], "ecc")) {
0971         return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset,
0972                        MLXBF_PMC_WRITE_REG_32, data);
0973     }
0974 
0975     if (mlxbf_pmc_valid_range(blk_num, offset))
0976         return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset,
0977                        MLXBF_PMC_WRITE_REG_64, data);
0978 
0979     return -EINVAL;
0980 }
0981 
0982 /* Show function for "counter" sysfs files */
0983 static ssize_t mlxbf_pmc_counter_show(struct device *dev,
0984                       struct device_attribute *attr, char *buf)
0985 {
0986     struct mlxbf_pmc_attribute *attr_counter = container_of(
0987         attr, struct mlxbf_pmc_attribute, dev_attr);
0988     int blk_num, cnt_num, offset;
0989     bool is_l3 = false;
0990     uint64_t value;
0991 
0992     blk_num = attr_counter->nr;
0993     cnt_num = attr_counter->index;
0994 
0995     if (strstr(pmc->block_name[blk_num], "l3cache"))
0996         is_l3 = true;
0997 
0998     if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_COUNTER) {
0999         if (mlxbf_pmc_read_counter(blk_num, cnt_num, is_l3, &value))
1000             return -EINVAL;
1001     } else if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_REGISTER) {
1002         offset = mlxbf_pmc_get_event_num(pmc->block_name[blk_num],
1003                          attr->attr.name);
1004         if (offset < 0)
1005             return -EINVAL;
1006         if (mlxbf_pmc_read_reg(blk_num, offset, &value))
1007             return -EINVAL;
1008     } else
1009         return -EINVAL;
1010 
1011     return sprintf(buf, "0x%llx\n", value);
1012 }
1013 
1014 /* Store function for "counter" sysfs files */
1015 static ssize_t mlxbf_pmc_counter_store(struct device *dev,
1016                        struct device_attribute *attr,
1017                        const char *buf, size_t count)
1018 {
1019     struct mlxbf_pmc_attribute *attr_counter = container_of(
1020         attr, struct mlxbf_pmc_attribute, dev_attr);
1021     int blk_num, cnt_num, offset, err, data;
1022     bool is_l3 = false;
1023     uint64_t evt_num;
1024 
1025     blk_num = attr_counter->nr;
1026     cnt_num = attr_counter->index;
1027 
1028     err = kstrtoint(buf, 0, &data);
1029     if (err < 0)
1030         return err;
1031 
1032     /* Allow non-zero writes only to the ecc regs */
1033     if (!(strstr(pmc->block_name[blk_num], "ecc")) && data)
1034         return -EINVAL;
1035 
1036     /* Do not allow writes to the L3C regs */
1037     if (strstr(pmc->block_name[blk_num], "l3cache"))
1038         return -EINVAL;
1039 
1040     if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_COUNTER) {
1041         err = mlxbf_pmc_read_event(blk_num, cnt_num, is_l3, &evt_num);
1042         if (err)
1043             return err;
1044         err = mlxbf_pmc_program_counter(blk_num, cnt_num, evt_num,
1045                         is_l3);
1046         if (err)
1047             return err;
1048     } else if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_REGISTER) {
1049         offset = mlxbf_pmc_get_event_num(pmc->block_name[blk_num],
1050                          attr->attr.name);
1051         if (offset < 0)
1052             return -EINVAL;
1053         err = mlxbf_pmc_write_reg(blk_num, offset, data);
1054         if (err)
1055             return err;
1056     } else
1057         return -EINVAL;
1058 
1059     return count;
1060 }
1061 
1062 /* Show function for "event" sysfs files */
1063 static ssize_t mlxbf_pmc_event_show(struct device *dev,
1064                     struct device_attribute *attr, char *buf)
1065 {
1066     struct mlxbf_pmc_attribute *attr_event = container_of(
1067         attr, struct mlxbf_pmc_attribute, dev_attr);
1068     int blk_num, cnt_num, err;
1069     bool is_l3 = false;
1070     uint64_t evt_num;
1071     char *evt_name;
1072 
1073     blk_num = attr_event->nr;
1074     cnt_num = attr_event->index;
1075 
1076     if (strstr(pmc->block_name[blk_num], "l3cache"))
1077         is_l3 = true;
1078 
1079     err = mlxbf_pmc_read_event(blk_num, cnt_num, is_l3, &evt_num);
1080     if (err)
1081         return sprintf(buf, "No event being monitored\n");
1082 
1083     evt_name = mlxbf_pmc_get_event_name(pmc->block_name[blk_num], evt_num);
1084     if (!evt_name)
1085         return -EINVAL;
1086 
1087     return sprintf(buf, "0x%llx: %s\n", evt_num, evt_name);
1088 }
1089 
1090 /* Store function for "event" sysfs files */
1091 static ssize_t mlxbf_pmc_event_store(struct device *dev,
1092                      struct device_attribute *attr,
1093                      const char *buf, size_t count)
1094 {
1095     struct mlxbf_pmc_attribute *attr_event = container_of(
1096         attr, struct mlxbf_pmc_attribute, dev_attr);
1097     int blk_num, cnt_num, evt_num, err;
1098     bool is_l3 = false;
1099 
1100     blk_num = attr_event->nr;
1101     cnt_num = attr_event->index;
1102 
1103     if (isalpha(buf[0])) {
1104         evt_num = mlxbf_pmc_get_event_num(pmc->block_name[blk_num],
1105                           buf);
1106         if (evt_num < 0)
1107             return -EINVAL;
1108     } else {
1109         err = kstrtoint(buf, 0, &evt_num);
1110         if (err < 0)
1111             return err;
1112     }
1113 
1114     if (strstr(pmc->block_name[blk_num], "l3cache"))
1115         is_l3 = true;
1116 
1117     err = mlxbf_pmc_program_counter(blk_num, cnt_num, evt_num, is_l3);
1118     if (err)
1119         return err;
1120 
1121     return count;
1122 }
1123 
1124 /* Show function for "event_list" sysfs files */
1125 static ssize_t mlxbf_pmc_event_list_show(struct device *dev,
1126                      struct device_attribute *attr,
1127                      char *buf)
1128 {
1129     struct mlxbf_pmc_attribute *attr_event_list = container_of(
1130         attr, struct mlxbf_pmc_attribute, dev_attr);
1131     int blk_num, i, size, len = 0, ret = 0;
1132     const struct mlxbf_pmc_events *events;
1133     char e_info[MLXBF_PMC_EVENT_INFO_LEN];
1134 
1135     blk_num = attr_event_list->nr;
1136 
1137     events = mlxbf_pmc_event_list(pmc->block_name[blk_num], &size);
1138     if (!events)
1139         return -EINVAL;
1140 
1141     for (i = 0, buf[0] = '\0'; i < size; ++i) {
1142         len += sprintf(e_info, "0x%x: %s\n", events[i].evt_num,
1143                    events[i].evt_name);
1144         if (len > PAGE_SIZE)
1145             break;
1146         strcat(buf, e_info);
1147         ret = len;
1148     }
1149 
1150     return ret;
1151 }
1152 
1153 /* Show function for "enable" sysfs files - only for l3cache */
1154 static ssize_t mlxbf_pmc_enable_show(struct device *dev,
1155                      struct device_attribute *attr, char *buf)
1156 {
1157     struct mlxbf_pmc_attribute *attr_enable = container_of(
1158         attr, struct mlxbf_pmc_attribute, dev_attr);
1159     uint32_t perfcnt_cfg;
1160     int blk_num, value;
1161 
1162     blk_num = attr_enable->nr;
1163 
1164     if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
1165                     MLXBF_PMC_L3C_PERF_CNT_CFG,
1166                 &perfcnt_cfg))
1167         return -EINVAL;
1168 
1169     value = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_CFG_EN, perfcnt_cfg);
1170 
1171     return sprintf(buf, "%d\n", value);
1172 }
1173 
1174 /* Store function for "enable" sysfs files - only for l3cache */
1175 static ssize_t mlxbf_pmc_enable_store(struct device *dev,
1176                       struct device_attribute *attr,
1177                       const char *buf, size_t count)
1178 {
1179     struct mlxbf_pmc_attribute *attr_enable = container_of(
1180         attr, struct mlxbf_pmc_attribute, dev_attr);
1181     int err, en, blk_num;
1182 
1183     blk_num = attr_enable->nr;
1184 
1185     err = kstrtoint(buf, 0, &en);
1186     if (err < 0)
1187         return err;
1188 
1189     if (!en) {
1190         err = mlxbf_pmc_config_l3_counters(blk_num, false, false);
1191         if (err)
1192             return err;
1193     } else if (en == 1) {
1194         err = mlxbf_pmc_config_l3_counters(blk_num, false, true);
1195         if (err)
1196             return err;
1197         err = mlxbf_pmc_config_l3_counters(blk_num, true, false);
1198         if (err)
1199             return err;
1200     } else
1201         return -EINVAL;
1202 
1203     return count;
1204 }
1205 
1206 /* Populate attributes for blocks with counters to monitor performance */
1207 static int mlxbf_pmc_init_perftype_counter(struct device *dev, int blk_num)
1208 {
1209     struct mlxbf_pmc_attribute *attr;
1210     int i = 0, j = 0;
1211 
1212     /* "event_list" sysfs to list events supported by the block */
1213     attr = &pmc->block[blk_num].attr_event_list;
1214     attr->dev_attr.attr.mode = 0444;
1215     attr->dev_attr.show = mlxbf_pmc_event_list_show;
1216     attr->nr = blk_num;
1217     attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, "event_list");
1218     pmc->block[blk_num].block_attr[i] = &attr->dev_attr.attr;
1219     attr = NULL;
1220 
1221     /* "enable" sysfs to start/stop the counters. Only in L3C blocks */
1222     if (strstr(pmc->block_name[blk_num], "l3cache")) {
1223         attr = &pmc->block[blk_num].attr_enable;
1224         attr->dev_attr.attr.mode = 0644;
1225         attr->dev_attr.show = mlxbf_pmc_enable_show;
1226         attr->dev_attr.store = mlxbf_pmc_enable_store;
1227         attr->nr = blk_num;
1228         attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL,
1229                               "enable");
1230         pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr;
1231         attr = NULL;
1232     }
1233 
1234     pmc->block[blk_num].attr_counter = devm_kcalloc(
1235         dev, pmc->block[blk_num].counters,
1236         sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL);
1237     if (!pmc->block[blk_num].attr_counter)
1238         return -ENOMEM;
1239 
1240     pmc->block[blk_num].attr_event = devm_kcalloc(
1241         dev, pmc->block[blk_num].counters,
1242         sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL);
1243     if (!pmc->block[blk_num].attr_event)
1244         return -ENOMEM;
1245 
1246     /* "eventX" and "counterX" sysfs to program and read counter values */
1247     for (j = 0; j < pmc->block[blk_num].counters; ++j) {
1248         attr = &pmc->block[blk_num].attr_counter[j];
1249         attr->dev_attr.attr.mode = 0644;
1250         attr->dev_attr.show = mlxbf_pmc_counter_show;
1251         attr->dev_attr.store = mlxbf_pmc_counter_store;
1252         attr->index = j;
1253         attr->nr = blk_num;
1254         attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL,
1255                               "counter%d", j);
1256         pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr;
1257         attr = NULL;
1258 
1259         attr = &pmc->block[blk_num].attr_event[j];
1260         attr->dev_attr.attr.mode = 0644;
1261         attr->dev_attr.show = mlxbf_pmc_event_show;
1262         attr->dev_attr.store = mlxbf_pmc_event_store;
1263         attr->index = j;
1264         attr->nr = blk_num;
1265         attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL,
1266                               "event%d", j);
1267         pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr;
1268         attr = NULL;
1269     }
1270 
1271     return 0;
1272 }
1273 
1274 /* Populate attributes for blocks with registers to monitor performance */
1275 static int mlxbf_pmc_init_perftype_reg(struct device *dev, int blk_num)
1276 {
1277     struct mlxbf_pmc_attribute *attr;
1278     const struct mlxbf_pmc_events *events;
1279     int i = 0, j = 0;
1280 
1281     events = mlxbf_pmc_event_list(pmc->block_name[blk_num], &j);
1282     if (!events)
1283         return -EINVAL;
1284 
1285     pmc->block[blk_num].attr_event = devm_kcalloc(
1286         dev, j, sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL);
1287     if (!pmc->block[blk_num].attr_event)
1288         return -ENOMEM;
1289 
1290     while (j > 0) {
1291         --j;
1292         attr = &pmc->block[blk_num].attr_event[j];
1293         attr->dev_attr.attr.mode = 0644;
1294         attr->dev_attr.show = mlxbf_pmc_counter_show;
1295         attr->dev_attr.store = mlxbf_pmc_counter_store;
1296         attr->nr = blk_num;
1297         attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL,
1298                               events[j].evt_name);
1299         pmc->block[blk_num].block_attr[i] = &attr->dev_attr.attr;
1300         attr = NULL;
1301         i++;
1302     }
1303 
1304     return 0;
1305 }
1306 
1307 /* Helper to create the bfperf sysfs sub-directories and files */
1308 static int mlxbf_pmc_create_groups(struct device *dev, int blk_num)
1309 {
1310     int err;
1311 
1312     /* Populate attributes based on counter type */
1313     if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_COUNTER)
1314         err = mlxbf_pmc_init_perftype_counter(dev, blk_num);
1315     else if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_REGISTER)
1316         err = mlxbf_pmc_init_perftype_reg(dev, blk_num);
1317     else
1318         err = -EINVAL;
1319 
1320     if (err)
1321         return err;
1322 
1323     /* Add a new attribute_group for the block */
1324     pmc->block[blk_num].block_attr_grp.attrs = pmc->block[blk_num].block_attr;
1325     pmc->block[blk_num].block_attr_grp.name = devm_kasprintf(
1326         dev, GFP_KERNEL, pmc->block_name[blk_num]);
1327     pmc->groups[blk_num] = &pmc->block[blk_num].block_attr_grp;
1328 
1329     return 0;
1330 }
1331 
1332 static bool mlxbf_pmc_guid_match(const guid_t *guid,
1333                  const struct arm_smccc_res *res)
1334 {
1335     guid_t id = GUID_INIT(res->a0, res->a1, res->a1 >> 16, res->a2,
1336                   res->a2 >> 8, res->a2 >> 16, res->a2 >> 24,
1337                   res->a3, res->a3 >> 8, res->a3 >> 16,
1338                   res->a3 >> 24);
1339 
1340     return guid_equal(guid, &id);
1341 }
1342 
1343 /* Helper to map the Performance Counters from the varios blocks */
1344 static int mlxbf_pmc_map_counters(struct device *dev)
1345 {
1346     uint64_t info[MLXBF_PMC_INFO_SZ];
1347     int i, tile_num, ret;
1348 
1349     for (i = 0; i < pmc->total_blocks; ++i) {
1350         if (strstr(pmc->block_name[i], "tile")) {
1351             ret = sscanf(pmc->block_name[i], "tile%d", &tile_num);
1352             if (ret < 0)
1353                 return ret;
1354 
1355             if (tile_num >= pmc->tile_count)
1356                 continue;
1357         }
1358         ret = device_property_read_u64_array(dev, pmc->block_name[i],
1359                              info, MLXBF_PMC_INFO_SZ);
1360         if (ret)
1361             return ret;
1362 
1363         /*
1364          * Do not remap if the proper SMC calls are supported,
1365          * since the SMC calls expect physical addresses.
1366          */
1367         if (pmc->svc_sreg_support)
1368             pmc->block[i].mmio_base = (void __iomem *)info[0];
1369         else
1370             pmc->block[i].mmio_base =
1371                 devm_ioremap(dev, info[0], info[1]);
1372 
1373         pmc->block[i].blk_size = info[1];
1374         pmc->block[i].counters = info[2];
1375         pmc->block[i].type = info[3];
1376 
1377         if (!pmc->block[i].mmio_base)
1378             return -ENOMEM;
1379 
1380         ret = mlxbf_pmc_create_groups(dev, i);
1381         if (ret)
1382             return ret;
1383     }
1384 
1385     return 0;
1386 }
1387 
1388 static int mlxbf_pmc_probe(struct platform_device *pdev)
1389 {
1390     struct acpi_device *acpi_dev = ACPI_COMPANION(&pdev->dev);
1391     const char *hid = acpi_device_hid(acpi_dev);
1392     struct device *dev = &pdev->dev;
1393     struct arm_smccc_res res;
1394     guid_t guid;
1395     int ret;
1396 
1397     /* Ensure we have the UUID we expect for this service. */
1398     arm_smccc_smc(MLXBF_PMC_SIP_SVC_UID, 0, 0, 0, 0, 0, 0, 0, &res);
1399     guid_parse(mlxbf_pmc_svc_uuid_str, &guid);
1400     if (!mlxbf_pmc_guid_match(&guid, &res))
1401         return -ENODEV;
1402 
1403     pmc = devm_kzalloc(dev, sizeof(struct mlxbf_pmc_context), GFP_KERNEL);
1404     if (!pmc)
1405         return -ENOMEM;
1406 
1407     /*
1408      * ACPI indicates whether we use SMCs to access registers or not.
1409      * If sreg_tbl_perf is not present, just assume we're not using SMCs.
1410      */
1411     ret = device_property_read_u32(dev, "sec_reg_block",
1412                        &pmc->sreg_tbl_perf);
1413     if (ret) {
1414         pmc->svc_sreg_support = false;
1415     } else {
1416         /*
1417          * Check service version to see if we actually do support the
1418          * needed SMCs. If we have the calls we need, mark support for
1419          * them in the pmc struct.
1420          */
1421         arm_smccc_smc(MLXBF_PMC_SIP_SVC_VERSION, 0, 0, 0, 0, 0, 0, 0,
1422                   &res);
1423         if (res.a0 == MLXBF_PMC_SVC_REQ_MAJOR &&
1424             res.a1 >= MLXBF_PMC_SVC_MIN_MINOR)
1425             pmc->svc_sreg_support = true;
1426         else
1427             return -EINVAL;
1428     }
1429 
1430     if (!strcmp(hid, "MLNXBFD0"))
1431         pmc->event_set = MLXBF_PMC_EVENT_SET_BF1;
1432     else if (!strcmp(hid, "MLNXBFD1"))
1433         pmc->event_set = MLXBF_PMC_EVENT_SET_BF2;
1434     else
1435         return -ENODEV;
1436 
1437     ret = device_property_read_u32(dev, "block_num", &pmc->total_blocks);
1438     if (ret)
1439         return ret;
1440 
1441     ret = device_property_read_string_array(dev, "block_name",
1442                         pmc->block_name,
1443                         pmc->total_blocks);
1444     if (ret != pmc->total_blocks)
1445         return -EFAULT;
1446 
1447     ret = device_property_read_u32(dev, "tile_num", &pmc->tile_count);
1448     if (ret)
1449         return ret;
1450 
1451     pmc->pdev = pdev;
1452 
1453     ret = mlxbf_pmc_map_counters(dev);
1454     if (ret)
1455         return ret;
1456 
1457     pmc->hwmon_dev = devm_hwmon_device_register_with_groups(
1458         dev, "bfperf", pmc, pmc->groups);
1459     platform_set_drvdata(pdev, pmc);
1460 
1461     return 0;
1462 }
1463 
1464 static const struct acpi_device_id mlxbf_pmc_acpi_ids[] = { { "MLNXBFD0", 0 },
1465                                 { "MLNXBFD1", 0 },
1466                                 {}, };
1467 
1468 MODULE_DEVICE_TABLE(acpi, mlxbf_pmc_acpi_ids);
1469 static struct platform_driver pmc_driver = {
1470     .driver = { .name = "mlxbf-pmc",
1471             .acpi_match_table = ACPI_PTR(mlxbf_pmc_acpi_ids), },
1472     .probe = mlxbf_pmc_probe,
1473 };
1474 
1475 module_platform_driver(pmc_driver);
1476 
1477 MODULE_AUTHOR("Shravan Kumar Ramani <sramani@mellanox.com>");
1478 MODULE_DESCRIPTION("Mellanox PMC driver");
1479 MODULE_LICENSE("Dual BSD/GPL");
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