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0007 #ifndef GOLDFISH_PIPE_QEMU_H
0008 #define GOLDFISH_PIPE_QEMU_H
0009
0010
0011 enum PipePollFlags {
0012 PIPE_POLL_IN = 1 << 0,
0013 PIPE_POLL_OUT = 1 << 1,
0014 PIPE_POLL_HUP = 1 << 2
0015 };
0016
0017
0018 enum PipeErrors {
0019 PIPE_ERROR_INVAL = -1,
0020 PIPE_ERROR_AGAIN = -2,
0021 PIPE_ERROR_NOMEM = -3,
0022 PIPE_ERROR_IO = -4
0023 };
0024
0025
0026 enum PipeWakeFlags {
0027
0028 PIPE_WAKE_CLOSED = 1 << 0,
0029
0030
0031 PIPE_WAKE_READ = 1 << 1,
0032
0033
0034 PIPE_WAKE_WRITE = 1 << 2,
0035
0036
0037 PIPE_WAKE_UNLOCK_DMA = 1 << 3,
0038
0039
0040 PIPE_WAKE_UNLOCK_DMA_SHARED = 1 << 4,
0041 };
0042
0043
0044 enum PipeCloseReason {
0045
0046 PIPE_CLOSE_GRACEFUL = 0,
0047
0048
0049 PIPE_CLOSE_REBOOT = 1,
0050
0051
0052 PIPE_CLOSE_LOAD_SNAPSHOT = 2,
0053
0054
0055 PIPE_CLOSE_ERROR = 3,
0056 };
0057
0058
0059 enum PipeFlagsBits {
0060 BIT_CLOSED_ON_HOST = 0,
0061 BIT_WAKE_ON_WRITE = 1,
0062 BIT_WAKE_ON_READ = 2,
0063 };
0064
0065 enum PipeRegs {
0066 PIPE_REG_CMD = 0,
0067
0068 PIPE_REG_SIGNAL_BUFFER_HIGH = 4,
0069 PIPE_REG_SIGNAL_BUFFER = 8,
0070 PIPE_REG_SIGNAL_BUFFER_COUNT = 12,
0071
0072 PIPE_REG_OPEN_BUFFER_HIGH = 20,
0073 PIPE_REG_OPEN_BUFFER = 24,
0074
0075 PIPE_REG_VERSION = 36,
0076
0077 PIPE_REG_GET_SIGNALLED = 48,
0078 };
0079
0080 enum PipeCmdCode {
0081
0082 PIPE_CMD_OPEN = 1,
0083
0084 PIPE_CMD_CLOSE,
0085 PIPE_CMD_POLL,
0086 PIPE_CMD_WRITE,
0087 PIPE_CMD_WAKE_ON_WRITE,
0088 PIPE_CMD_READ,
0089 PIPE_CMD_WAKE_ON_READ,
0090
0091
0092
0093
0094
0095 PIPE_CMD_WAKE_ON_DONE_IO,
0096 };
0097
0098 #endif