platform/chrome/cros_ec_lpc_mec.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * LPC variant I/O for Microchip EC
0004  *
0005  * Copyright (C) 2016 Google, Inc
0006  */
0007
0008 #ifndef __CROS_EC_LPC_MEC_H
0009 #define __CROS_EC_LPC_MEC_H
0010
0011 enum cros_ec_lpc_mec_emi_access_mode {
0012     /* 8-bit access */
0013     ACCESS_TYPE_BYTE = 0x0,
0014     /* 16-bit access */
0015     ACCESS_TYPE_WORD = 0x1,
0016     /* 32-bit access */
0017     ACCESS_TYPE_LONG = 0x2,
0018     /*
0019      * 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the
0020      * EC data register to be incremented.
0021      */
0022     ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3,
0023 };
0024
0025 enum cros_ec_lpc_mec_io_type {
0026     MEC_IO_READ,
0027     MEC_IO_WRITE,
0028 };
0029
0030 /* EMI registers are relative to base */
0031 #define MEC_EMI_HOST_TO_EC(MEC_EMI_BASE)    ((MEC_EMI_BASE) + 0)
0032 #define MEC_EMI_EC_TO_HOST(MEC_EMI_BASE)    ((MEC_EMI_BASE) + 1)
0033 #define MEC_EMI_EC_ADDRESS_B0(MEC_EMI_BASE) ((MEC_EMI_BASE) + 2)
0034 #define MEC_EMI_EC_ADDRESS_B1(MEC_EMI_BASE) ((MEC_EMI_BASE) + 3)
0035 #define MEC_EMI_EC_DATA_B0(MEC_EMI_BASE)    ((MEC_EMI_BASE) + 4)
0036 #define MEC_EMI_EC_DATA_B1(MEC_EMI_BASE)    ((MEC_EMI_BASE) + 5)
0037 #define MEC_EMI_EC_DATA_B2(MEC_EMI_BASE)    ((MEC_EMI_BASE) + 6)
0038 #define MEC_EMI_EC_DATA_B3(MEC_EMI_BASE)    ((MEC_EMI_BASE) + 7)
0039
0040 /**
0041  * cros_ec_lpc_mec_init() - Initialize MEC I/O.
0042  *
0043  * @base: MEC EMI Base address
0044  * @end: MEC EMI End address
0045  */
0046 void cros_ec_lpc_mec_init(unsigned int base, unsigned int end);
0047
0048 /*
0049  * cros_ec_lpc_mec_destroy
0050  *
0051  * Cleanup MEC I/O.
0052  */
0053 void cros_ec_lpc_mec_destroy(void);
0054
0055 /**
0056  * cros_ec_lpc_mec_in_range() - Determine if addresses are in MEC EMI range.
0057  *
0058  * @offset: Address offset
0059  * @length: Number of bytes to check
0060  *
0061  * Return: 1 if in range, 0 if not, and -EINVAL on failure
0062  *         such as the mec range not being initialized
0063  */
0064 int cros_ec_lpc_mec_in_range(unsigned int offset, unsigned int length);
0065
0066 /**
0067  * cros_ec_lpc_io_bytes_mec - Read / write bytes to MEC EMI port
0068  *
0069  * @io_type: MEC_IO_READ or MEC_IO_WRITE, depending on request
0070  * @offset:  Base read / write address
0071  * @length:  Number of bytes to read / write
0072  * @buf:     Destination / source buffer
0073  *
0074  * @return 8-bit checksum of all bytes read / written
0075  */
0076 u8 cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type,
0077                 unsigned int offset, unsigned int length, u8 *buf);
0078
0079 #endif /* __CROS_EC_LPC_MEC_H */