pinctrl/visconti/pinctrl-tmpv7700.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 TOSHIBA CORPORATION
0004  * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation
0005  * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
0006  */
0007
0008 #include <linux/init.h>
0009 #include <linux/io.h>
0010 #include <linux/of.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/pinctrl/pinctrl.h>
0013 #include "pinctrl-common.h"
0014
0015 #define tmpv7700_MAGIC_NUM 0x4932f70e
0016
0017 /* register offset */
0018 #define REG_KEY_CTRL    0x0000
0019 #define REG_KEY_CMD 0x0004
0020 #define REG_PINMUX1 0x3000
0021 #define REG_PINMUX2 0x3004
0022 #define REG_PINMUX3 0x3008
0023 #define REG_PINMUX4 0x300c
0024 #define REG_PINMUX5 0x3010
0025 #define REG_IOSET   0x3014
0026 #define REG_IO_VSEL 0x3018
0027 #define REG_IO_DSEL1    0x301c
0028 #define REG_IO_DSEL2    0x3020
0029 #define REG_IO_DSEL3    0x3024
0030 #define REG_IO_DSEL4    0x3028
0031 #define REG_IO_DSEL5    0x302c
0032 #define REG_IO_DSEL6    0x3030
0033 #define REG_IO_DSEL7    0x3034
0034 #define REG_IO_DSEL8    0x3038
0035 #define REG_IO_PUDE1    0x303c
0036 #define REG_IO_PUDE2    0x3040
0037 #define REG_IO_PUDSEL1  0x3044
0038 #define REG_IO_PUDSEL2  0x3048
0039
0040 /* PIN */
0041 static const struct visconti_desc_pin pins_tmpv7700[] = {
0042     VISCONTI_PIN(PINCTRL_PIN(0, "gpio0"), REG_IO_DSEL4, 24,
0043             REG_IO_PUDE1, REG_IO_PUDSEL1, 30),
0044     VISCONTI_PIN(PINCTRL_PIN(1, "gpio1"), REG_IO_DSEL4, 28,
0045             REG_IO_PUDE1, REG_IO_PUDSEL1, 31),
0046     VISCONTI_PIN(PINCTRL_PIN(2, "gpio2"), REG_IO_DSEL5, 0,
0047             REG_IO_PUDE2, REG_IO_PUDSEL2, 0),
0048     VISCONTI_PIN(PINCTRL_PIN(3, "gpio3"), REG_IO_DSEL5, 4,
0049             REG_IO_PUDE2, REG_IO_PUDSEL2, 1),
0050     VISCONTI_PIN(PINCTRL_PIN(4, "gpio4"), REG_IO_DSEL5, 8,
0051             REG_IO_PUDE2, REG_IO_PUDSEL2, 2),
0052     VISCONTI_PIN(PINCTRL_PIN(5, "gpio5"), REG_IO_DSEL5, 12,
0053             REG_IO_PUDE2, REG_IO_PUDSEL2, 3),
0054     VISCONTI_PIN(PINCTRL_PIN(6, "gpio6"), REG_IO_DSEL5, 16,
0055             REG_IO_PUDE2, REG_IO_PUDSEL2, 4),
0056     VISCONTI_PIN(PINCTRL_PIN(7, "gpio7"), REG_IO_DSEL5, 20,
0057             REG_IO_PUDE2, REG_IO_PUDSEL2, 5),
0058     VISCONTI_PIN(PINCTRL_PIN(8, "gpio8"), REG_IO_DSEL5, 24,
0059             REG_IO_PUDE2, REG_IO_PUDSEL2, 6),
0060     VISCONTI_PIN(PINCTRL_PIN(9, "gpio9"), REG_IO_DSEL5, 28,
0061             REG_IO_PUDE2, REG_IO_PUDSEL2, 7),
0062     VISCONTI_PIN(PINCTRL_PIN(10, "gpio10"), REG_IO_DSEL6, 0,
0063             REG_IO_PUDE2, REG_IO_PUDSEL2, 8),
0064     VISCONTI_PIN(PINCTRL_PIN(11, "gpio11"), REG_IO_DSEL6, 4,
0065             REG_IO_PUDE2, REG_IO_PUDSEL2, 9),
0066     VISCONTI_PIN(PINCTRL_PIN(12, "gpio12"), REG_IO_DSEL6, 8,
0067             REG_IO_PUDE2, REG_IO_PUDSEL2, 10),
0068     VISCONTI_PIN(PINCTRL_PIN(13, "gpio13"), REG_IO_DSEL6, 12,
0069             REG_IO_PUDE2, REG_IO_PUDSEL2, 11),
0070     VISCONTI_PIN(PINCTRL_PIN(14, "gpio14"), REG_IO_DSEL6, 16,
0071             REG_IO_PUDE2, REG_IO_PUDSEL2, 12),
0072     VISCONTI_PIN(PINCTRL_PIN(15, "gpio15"), REG_IO_DSEL6, 20,
0073             REG_IO_PUDE2, REG_IO_PUDSEL2, 13),
0074     VISCONTI_PIN(PINCTRL_PIN(16, "gpio16"), REG_IO_DSEL6, 24,
0075             REG_IO_PUDE2, REG_IO_PUDSEL2, 14),
0076     VISCONTI_PIN(PINCTRL_PIN(17, "gpio17"), REG_IO_DSEL6, 28,
0077             REG_IO_PUDE2, REG_IO_PUDSEL2, 15),
0078     VISCONTI_PIN(PINCTRL_PIN(18, "gpio18"), REG_IO_DSEL7, 0,
0079             REG_IO_PUDE2, REG_IO_PUDSEL2, 16),
0080     VISCONTI_PIN(PINCTRL_PIN(19, "gpio19"), REG_IO_DSEL7, 4,
0081             REG_IO_PUDE2, REG_IO_PUDSEL2, 17),
0082     VISCONTI_PIN(PINCTRL_PIN(20, "gpio20"), REG_IO_DSEL7, 8,
0083             REG_IO_PUDE2, REG_IO_PUDSEL2, 18),
0084     VISCONTI_PIN(PINCTRL_PIN(21, "gpio21"), REG_IO_DSEL7, 12,
0085             REG_IO_PUDE2, REG_IO_PUDSEL2, 19),
0086     VISCONTI_PIN(PINCTRL_PIN(22, "gpio22"), REG_IO_DSEL7, 16,
0087             REG_IO_PUDE2, REG_IO_PUDSEL2, 20),
0088     VISCONTI_PIN(PINCTRL_PIN(23, "gpio23"), REG_IO_DSEL7, 20,
0089             REG_IO_PUDE2, REG_IO_PUDSEL2, 21),
0090     VISCONTI_PIN(PINCTRL_PIN(24, "gpio24"), REG_IO_DSEL7, 24,
0091             REG_IO_PUDE2, REG_IO_PUDSEL2, 22),
0092     VISCONTI_PIN(PINCTRL_PIN(25, "gpio25"), REG_IO_DSEL7, 28,
0093             REG_IO_PUDE2, REG_IO_PUDSEL2, 23),
0094     VISCONTI_PIN(PINCTRL_PIN(26, "gpio26"), REG_IO_DSEL8, 0,
0095             REG_IO_PUDE2, REG_IO_PUDSEL2, 24),
0096     VISCONTI_PIN(PINCTRL_PIN(27, "gpio27"), REG_IO_DSEL8, 4,
0097             REG_IO_PUDE2, REG_IO_PUDSEL2, 25),
0098     VISCONTI_PIN(PINCTRL_PIN(28, "gpio28"), REG_IO_DSEL8, 8,
0099             REG_IO_PUDE2, REG_IO_PUDSEL2, 26),
0100     VISCONTI_PIN(PINCTRL_PIN(29, "gpio29"), REG_IO_DSEL4, 8,
0101             REG_IO_PUDE1, REG_IO_PUDSEL1, 26),
0102     VISCONTI_PIN(PINCTRL_PIN(30, "gpio30"), REG_IO_DSEL4, 4,
0103             REG_IO_PUDE1, REG_IO_PUDSEL1, 25),
0104     VISCONTI_PIN(PINCTRL_PIN(31, "gpio31"), REG_IO_DSEL4, 0,
0105             REG_IO_PUDE1, REG_IO_PUDSEL1, 24),
0106     VISCONTI_PIN(PINCTRL_PIN(32, "spi_sck"), REG_IO_DSEL4, 12,
0107             REG_IO_PUDE1, REG_IO_PUDSEL1, 27),
0108     VISCONTI_PIN(PINCTRL_PIN(33, "spi_sdo"), REG_IO_DSEL4, 16,
0109             REG_IO_PUDE1, REG_IO_PUDSEL1, 28),
0110     VISCONTI_PIN(PINCTRL_PIN(34, "spi_sdi"), REG_IO_DSEL4, 20,
0111             REG_IO_PUDE1, REG_IO_PUDSEL1, 29),
0112 };
0113
0114 /* Group */
0115 VISCONTI_PINS(i2c0, 0, 1);
0116 VISCONTI_PINS(i2c1, 2, 3);
0117 VISCONTI_PINS(i2c2, 12, 13);
0118 VISCONTI_PINS(i2c3, 14, 15);
0119 VISCONTI_PINS(i2c4, 16, 17);
0120 VISCONTI_PINS(i2c5, 18, 19);
0121 VISCONTI_PINS(i2c6, 33, 34);
0122 VISCONTI_PINS(i2c7, 29, 32);
0123 VISCONTI_PINS(i2c8, 30, 31);
0124 VISCONTI_PINS(spi0_cs0, 29);
0125 VISCONTI_PINS(spi0_cs1, 30);
0126 VISCONTI_PINS(spi0_cs2, 31);
0127 VISCONTI_PINS(spi1_cs, 3);
0128 VISCONTI_PINS(spi2_cs, 7);
0129 VISCONTI_PINS(spi3_cs, 11);
0130 VISCONTI_PINS(spi4_cs, 15);
0131 VISCONTI_PINS(spi5_cs, 19);
0132 VISCONTI_PINS(spi6_cs, 27);
0133 VISCONTI_PINS(spi0, 32, 33, 34);
0134 VISCONTI_PINS(spi1, 0, 1, 2);
0135 VISCONTI_PINS(spi2, 4, 5, 6);
0136 VISCONTI_PINS(spi3, 8, 9, 10);
0137 VISCONTI_PINS(spi4, 12, 13, 14);
0138 VISCONTI_PINS(spi5, 16, 17, 18);
0139 VISCONTI_PINS(spi6, 24, 25, 26);
0140 VISCONTI_PINS(uart0, 4, 5, 6, 7);
0141 VISCONTI_PINS(uart1, 8, 9, 10, 11);
0142 VISCONTI_PINS(uart2, 12, 13, 14, 15);
0143 VISCONTI_PINS(uart3, 16, 17, 18, 19);
0144 VISCONTI_PINS(pwm0_gpio4, 4);
0145 VISCONTI_PINS(pwm1_gpio5, 5);
0146 VISCONTI_PINS(pwm2_gpio6, 6);
0147 VISCONTI_PINS(pwm3_gpio7, 7);
0148 VISCONTI_PINS(pwm0_gpio8, 8);
0149 VISCONTI_PINS(pwm1_gpio9, 9);
0150 VISCONTI_PINS(pwm2_gpio10, 10);
0151 VISCONTI_PINS(pwm3_gpio11, 11);
0152 VISCONTI_PINS(pwm0_gpio12, 12);
0153 VISCONTI_PINS(pwm1_gpio13, 13);
0154 VISCONTI_PINS(pwm2_gpio14, 14);
0155 VISCONTI_PINS(pwm3_gpio15, 15);
0156 VISCONTI_PINS(pwm0_gpio16, 16);
0157 VISCONTI_PINS(pwm1_gpio17, 17);
0158 VISCONTI_PINS(pwm2_gpio18, 18);
0159 VISCONTI_PINS(pwm3_gpio19, 19);
0160 VISCONTI_PINS(pcmif_out, 20, 21, 22);
0161 VISCONTI_PINS(pcmif_in, 24, 25, 26);
0162
0163 static const struct visconti_pin_group groups_tmpv7700[] = {
0164     VISCONTI_PIN_GROUP(i2c0, REG_PINMUX2, GENMASK(7, 0), 0x00000022),
0165     VISCONTI_PIN_GROUP(i2c1, REG_PINMUX2, GENMASK(15, 8), 0x00002200),
0166     VISCONTI_PIN_GROUP(i2c2, REG_PINMUX3, GENMASK(23, 16), 0x00770000),
0167     VISCONTI_PIN_GROUP(i2c3, REG_PINMUX3, GENMASK(31, 24), 0x77000000),
0168     VISCONTI_PIN_GROUP(i2c4, REG_PINMUX4, GENMASK(7, 0), 0x00000077),
0169     VISCONTI_PIN_GROUP(i2c5, REG_PINMUX4, GENMASK(15, 8), 0x00007700),
0170     VISCONTI_PIN_GROUP(i2c6, REG_PINMUX1, GENMASK(3, 0), 0x0000002),
0171     VISCONTI_PIN_GROUP(i2c7, REG_PINMUX5, GENMASK(23, 20), 0x00200000),
0172     VISCONTI_PIN_GROUP(i2c8, REG_PINMUX5, GENMASK(31, 24), 0x22000000),
0173     VISCONTI_PIN_GROUP(spi0_cs0, REG_PINMUX5, GENMASK(23, 20), 0x00100000),
0174     VISCONTI_PIN_GROUP(spi0_cs1, REG_PINMUX5, GENMASK(27, 24), 0x01000000),
0175     VISCONTI_PIN_GROUP(spi0_cs2, REG_PINMUX5, GENMASK(31, 28), 0x10000000),
0176     VISCONTI_PIN_GROUP(spi1_cs, REG_PINMUX2, GENMASK(15, 12), 0x00001000),
0177     VISCONTI_PIN_GROUP(spi2_cs, REG_PINMUX2, GENMASK(31, 28), 0x10000000),
0178     VISCONTI_PIN_GROUP(spi3_cs, REG_PINMUX3, GENMASK(15, 12), 0x00001000),
0179     VISCONTI_PIN_GROUP(spi4_cs, REG_PINMUX4, GENMASK(31, 28), 0x10000000),
0180     VISCONTI_PIN_GROUP(spi5_cs, REG_PINMUX4, GENMASK(15, 12), 0x00001000),
0181     VISCONTI_PIN_GROUP(spi6_cs, REG_PINMUX5, GENMASK(15, 12), 0x00001000),
0182     VISCONTI_PIN_GROUP(spi0, REG_PINMUX1, GENMASK(3, 0), 0x00000001),
0183     VISCONTI_PIN_GROUP(spi1, REG_PINMUX2, GENMASK(11, 0), 0x00000111),
0184     VISCONTI_PIN_GROUP(spi2, REG_PINMUX2, GENMASK(27, 16), 0x01110000),
0185     VISCONTI_PIN_GROUP(spi3, REG_PINMUX3, GENMASK(11, 0), 0x00000111),
0186     VISCONTI_PIN_GROUP(spi4, REG_PINMUX3, GENMASK(27, 16), 0x01110000),
0187     VISCONTI_PIN_GROUP(spi5, REG_PINMUX4, GENMASK(11, 0), 0x00000111),
0188     VISCONTI_PIN_GROUP(spi6, REG_PINMUX5, GENMASK(11, 0), 0x00000111),
0189     VISCONTI_PIN_GROUP(uart0, REG_PINMUX2, GENMASK(31, 16), 0x22220000),
0190     VISCONTI_PIN_GROUP(uart1, REG_PINMUX3, GENMASK(15, 0), 0x00002222),
0191     VISCONTI_PIN_GROUP(uart2, REG_PINMUX3, GENMASK(31, 16), 0x22220000),
0192     VISCONTI_PIN_GROUP(uart3, REG_PINMUX4, GENMASK(15, 0), 0x00002222),
0193     VISCONTI_PIN_GROUP(pwm0_gpio4, REG_PINMUX2, GENMASK(19, 16), 0x00050000),
0194     VISCONTI_PIN_GROUP(pwm1_gpio5, REG_PINMUX2, GENMASK(23, 20), 0x00500000),
0195     VISCONTI_PIN_GROUP(pwm2_gpio6, REG_PINMUX2, GENMASK(27, 24), 0x05000000),
0196     VISCONTI_PIN_GROUP(pwm3_gpio7, REG_PINMUX2, GENMASK(31, 28), 0x50000000),
0197     VISCONTI_PIN_GROUP(pwm0_gpio8, REG_PINMUX3, GENMASK(3, 0), 0x00000005),
0198     VISCONTI_PIN_GROUP(pwm1_gpio9, REG_PINMUX3, GENMASK(7, 4), 0x00000050),
0199     VISCONTI_PIN_GROUP(pwm2_gpio10, REG_PINMUX3, GENMASK(11, 8), 0x00000500),
0200     VISCONTI_PIN_GROUP(pwm3_gpio11, REG_PINMUX3, GENMASK(15, 12), 0x00005000),
0201     VISCONTI_PIN_GROUP(pwm0_gpio12, REG_PINMUX3, GENMASK(19, 16), 0x00050000),
0202     VISCONTI_PIN_GROUP(pwm1_gpio13, REG_PINMUX3, GENMASK(23, 20), 0x00500000),
0203     VISCONTI_PIN_GROUP(pwm2_gpio14, REG_PINMUX3, GENMASK(27, 24), 0x05000000),
0204     VISCONTI_PIN_GROUP(pwm3_gpio15, REG_PINMUX3, GENMASK(31, 28), 0x50000000),
0205     VISCONTI_PIN_GROUP(pwm0_gpio16, REG_PINMUX4, GENMASK(3, 0), 0x00000005),
0206     VISCONTI_PIN_GROUP(pwm1_gpio17, REG_PINMUX4, GENMASK(7, 4), 0x00000050),
0207     VISCONTI_PIN_GROUP(pwm2_gpio18, REG_PINMUX4, GENMASK(11, 8), 0x00000500),
0208     VISCONTI_PIN_GROUP(pwm3_gpio19, REG_PINMUX4, GENMASK(15, 12), 0x00005000),
0209     VISCONTI_PIN_GROUP(pcmif_out, REG_PINMUX4, GENMASK(27, 16), 0x01110000),
0210     VISCONTI_PIN_GROUP(pcmif_in, REG_PINMUX5, GENMASK(11, 0), 0x00000222),
0211 };
0212
0213 /* MUX */
0214 VISCONTI_GROUPS(i2c0, "i2c0_grp");
0215 VISCONTI_GROUPS(i2c1, "i2c1_grp");
0216 VISCONTI_GROUPS(i2c2, "i2c2_grp");
0217 VISCONTI_GROUPS(i2c3, "i2c3_grp");
0218 VISCONTI_GROUPS(i2c4, "i2c4_grp");
0219 VISCONTI_GROUPS(i2c5, "i2c5_grp");
0220 VISCONTI_GROUPS(i2c6, "i2c6_grp");
0221 VISCONTI_GROUPS(i2c7, "i2c7_grp");
0222 VISCONTI_GROUPS(i2c8, "i2c8_grp");
0223 VISCONTI_GROUPS(spi0, "spi0_grp", "spi0_cs0_grp",
0224         "spi0_cs1_grp", "spi0_cs2_grp");
0225 VISCONTI_GROUPS(spi1, "spi1_grp", "spi1_cs_grp");
0226 VISCONTI_GROUPS(spi2, "spi2_grp", "spi2_cs_grp");
0227 VISCONTI_GROUPS(spi3, "spi3_grp", "spi3_cs_grp");
0228 VISCONTI_GROUPS(spi4, "spi4_grp", "spi4_cs_grp");
0229 VISCONTI_GROUPS(spi5, "spi5_grp", "spi5_cs_grp");
0230 VISCONTI_GROUPS(spi6, "spi6_grp", "spi6_cs_grp");
0231 VISCONTI_GROUPS(uart0, "uart0_grp");
0232 VISCONTI_GROUPS(uart1, "uart1_grp");
0233 VISCONTI_GROUPS(uart2, "uart2_grp");
0234 VISCONTI_GROUPS(uart3, "uart3_grp");
0235 VISCONTI_GROUPS(pwm, "pwm0_gpio4_grp", "pwm0_gpio8_grp",
0236         "pwm0_gpio12_grp", "pwm0_gpio16_grp",
0237         "pwm1_gpio5_grp", "pwm1_gpio9_grp",
0238         "pwm1_gpio13_grp", "pwm1_gpio17_grp",
0239         "pwm2_gpio6_grp", "pwm2_gpio10_grp",
0240         "pwm2_gpio14_grp", "pwm2_gpio18_grp",
0241         "pwm3_gpio7_grp", "pwm3_gpio11_grp",
0242         "pwm3_gpio15_grp", "pwm3_gpio19_grp");
0243 VISCONTI_GROUPS(pcmif_out, "pcmif_out_grp");
0244 VISCONTI_GROUPS(pcmif_in, "pcmif_in_grp");
0245
0246 static const struct visconti_pin_function functions_tmpv7700[] = {
0247     VISCONTI_PIN_FUNCTION(i2c0),
0248     VISCONTI_PIN_FUNCTION(i2c1),
0249     VISCONTI_PIN_FUNCTION(i2c2),
0250     VISCONTI_PIN_FUNCTION(i2c3),
0251     VISCONTI_PIN_FUNCTION(i2c4),
0252     VISCONTI_PIN_FUNCTION(i2c5),
0253     VISCONTI_PIN_FUNCTION(i2c6),
0254     VISCONTI_PIN_FUNCTION(i2c7),
0255     VISCONTI_PIN_FUNCTION(i2c8),
0256     VISCONTI_PIN_FUNCTION(spi0),
0257     VISCONTI_PIN_FUNCTION(spi1),
0258     VISCONTI_PIN_FUNCTION(spi2),
0259     VISCONTI_PIN_FUNCTION(spi3),
0260     VISCONTI_PIN_FUNCTION(spi4),
0261     VISCONTI_PIN_FUNCTION(spi5),
0262     VISCONTI_PIN_FUNCTION(spi6),
0263     VISCONTI_PIN_FUNCTION(uart0),
0264     VISCONTI_PIN_FUNCTION(uart1),
0265     VISCONTI_PIN_FUNCTION(uart2),
0266     VISCONTI_PIN_FUNCTION(uart3),
0267     VISCONTI_PIN_FUNCTION(pwm),
0268     VISCONTI_PIN_FUNCTION(pcmif_in),
0269     VISCONTI_PIN_FUNCTION(pcmif_out),
0270 };
0271
0272 /* GPIO MUX */
0273 #define tmpv7700_GPIO_MUX(off, msk) \
0274 {                   \
0275     .offset = off,          \
0276     .mask = msk,            \
0277     .val = 0,           \
0278 }
0279
0280 static const struct visconti_mux gpio_mux_tmpv7700[] = {
0281     tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(3, 0)),
0282     tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(7, 4)),
0283     tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(11, 8)),
0284     tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(15, 12)),
0285     tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(19, 16)),
0286     tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(23, 20)),
0287     tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(27, 24)),
0288     tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(31, 28)),
0289     tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(3, 0)),
0290     tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(7, 4)),
0291     tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(11, 8)),
0292     tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(15, 12)),
0293     tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(19, 16)),
0294     tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(23, 20)),
0295     tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(27, 24)),
0296     tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(31, 28)),
0297     tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(3, 0)),
0298     tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(7, 4)),
0299     tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(11, 8)),
0300     tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(15, 12)),
0301     tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(19, 16)),
0302     tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(23, 20)),
0303     tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(27, 24)),
0304     tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(31, 28)),
0305     tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(3, 0)),
0306     tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(7, 4)),
0307     tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(11, 8)),
0308     tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(15, 12)),
0309     tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(19, 16)),
0310     tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(23, 20)),
0311     tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(27, 24)),
0312     tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(31, 28)),
0313 };
0314
0315 static void tmpv7700_pinctrl_unlock(void __iomem *base)
0316 {
0317     writel(1, base + REG_KEY_CTRL);
0318     writel(tmpv7700_MAGIC_NUM, base + REG_KEY_CMD);
0319 }
0320
0321 /* chip dependent data */
0322 static const struct visconti_pinctrl_devdata tmpv7700_pinctrl_data = {
0323     .pins = pins_tmpv7700,
0324     .nr_pins = ARRAY_SIZE(pins_tmpv7700),
0325     .groups = groups_tmpv7700,
0326     .nr_groups = ARRAY_SIZE(groups_tmpv7700),
0327     .functions = functions_tmpv7700,
0328     .nr_functions = ARRAY_SIZE(functions_tmpv7700),
0329     .gpio_mux = gpio_mux_tmpv7700,
0330     .unlock = tmpv7700_pinctrl_unlock,
0331 };
0332
0333 static int tmpv7700_pinctrl_probe(struct platform_device *pdev)
0334 {
0335     return visconti_pinctrl_probe(pdev, &tmpv7700_pinctrl_data);
0336 }
0337
0338 static const struct of_device_id tmpv7700_pctrl_of_match[] = {
0339     { .compatible = "toshiba,tmpv7708-pinctrl", },
0340     {},
0341 };
0342
0343 static struct platform_driver tmpv7700_pinctrl_driver = {
0344     .probe = tmpv7700_pinctrl_probe,
0345     .driver = {
0346         .name = "tmpv7700-pinctrl",
0347         .of_match_table = tmpv7700_pctrl_of_match,
0348     },
0349 };
0350
0351 static int __init tmpv7700_pinctrl_init(void)
0352 {
0353     return platform_driver_register(&tmpv7700_pinctrl_driver);
0354 }
0355 arch_initcall(tmpv7700_pinctrl_init);