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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright (C) 2015-2017 Socionext Inc.
0004 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0005 
0006 #include <linux/list.h>
0007 #include <linux/mfd/syscon.h>
0008 #include <linux/of.h>
0009 #include <linux/pinctrl/pinconf.h>
0010 #include <linux/pinctrl/pinconf-generic.h>
0011 #include <linux/pinctrl/pinctrl.h>
0012 #include <linux/pinctrl/pinmux.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regmap.h>
0015 
0016 #include "../core.h"
0017 #include "../pinctrl-utils.h"
0018 #include "pinctrl-uniphier.h"
0019 
0020 #define UNIPHIER_PINCTRL_PINMUX_BASE    0x1000
0021 #define UNIPHIER_PINCTRL_LOAD_PINMUX    0x1700
0022 #define UNIPHIER_PINCTRL_DRVCTRL_BASE   0x1800
0023 #define UNIPHIER_PINCTRL_DRV2CTRL_BASE  0x1900
0024 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE  0x1980
0025 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE  0x1a00
0026 #define UNIPHIER_PINCTRL_IECTRL_BASE    0x1d00
0027 
0028 struct uniphier_pinctrl_reg_region {
0029     struct list_head node;
0030     unsigned int base;
0031     unsigned int nregs;
0032     u32 vals[];
0033 };
0034 
0035 struct uniphier_pinctrl_priv {
0036     struct pinctrl_desc pctldesc;
0037     struct pinctrl_dev *pctldev;
0038     struct regmap *regmap;
0039     const struct uniphier_pinctrl_socdata *socdata;
0040     struct list_head reg_regions;
0041 };
0042 
0043 static int uniphier_pctl_get_groups_count(struct pinctrl_dev *pctldev)
0044 {
0045     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0046 
0047     return priv->socdata->groups_count;
0048 }
0049 
0050 static const char *uniphier_pctl_get_group_name(struct pinctrl_dev *pctldev,
0051                         unsigned selector)
0052 {
0053     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0054 
0055     return priv->socdata->groups[selector].name;
0056 }
0057 
0058 static int uniphier_pctl_get_group_pins(struct pinctrl_dev *pctldev,
0059                     unsigned selector,
0060                     const unsigned **pins,
0061                     unsigned *num_pins)
0062 {
0063     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0064 
0065     *pins = priv->socdata->groups[selector].pins;
0066     *num_pins = priv->socdata->groups[selector].num_pins;
0067 
0068     return 0;
0069 }
0070 
0071 #ifdef CONFIG_DEBUG_FS
0072 static void uniphier_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
0073                        struct seq_file *s, unsigned offset)
0074 {
0075     const struct pin_desc *desc = pin_desc_get(pctldev, offset);
0076     const char *pull_dir, *drv_type;
0077 
0078     switch (uniphier_pin_get_pull_dir(desc->drv_data)) {
0079     case UNIPHIER_PIN_PULL_UP:
0080         pull_dir = "UP";
0081         break;
0082     case UNIPHIER_PIN_PULL_DOWN:
0083         pull_dir = "DOWN";
0084         break;
0085     case UNIPHIER_PIN_PULL_UP_FIXED:
0086         pull_dir = "UP(FIXED)";
0087         break;
0088     case UNIPHIER_PIN_PULL_DOWN_FIXED:
0089         pull_dir = "DOWN(FIXED)";
0090         break;
0091     case UNIPHIER_PIN_PULL_NONE:
0092         pull_dir = "NONE";
0093         break;
0094     default:
0095         BUG();
0096     }
0097 
0098     switch (uniphier_pin_get_drv_type(desc->drv_data)) {
0099     case UNIPHIER_PIN_DRV_1BIT:
0100         drv_type = "4/8(mA)";
0101         break;
0102     case UNIPHIER_PIN_DRV_2BIT:
0103         drv_type = "8/12/16/20(mA)";
0104         break;
0105     case UNIPHIER_PIN_DRV_3BIT:
0106         drv_type = "4/5/7/9/11/12/14/16(mA)";
0107         break;
0108     case UNIPHIER_PIN_DRV_FIXED4:
0109         drv_type = "4(mA)";
0110         break;
0111     case UNIPHIER_PIN_DRV_FIXED5:
0112         drv_type = "5(mA)";
0113         break;
0114     case UNIPHIER_PIN_DRV_FIXED8:
0115         drv_type = "8(mA)";
0116         break;
0117     case UNIPHIER_PIN_DRV_NONE:
0118         drv_type = "NONE";
0119         break;
0120     default:
0121         BUG();
0122     }
0123 
0124     seq_printf(s, " PULL_DIR=%s  DRV_TYPE=%s", pull_dir, drv_type);
0125 }
0126 #endif
0127 
0128 static const struct pinctrl_ops uniphier_pctlops = {
0129     .get_groups_count = uniphier_pctl_get_groups_count,
0130     .get_group_name = uniphier_pctl_get_group_name,
0131     .get_group_pins = uniphier_pctl_get_group_pins,
0132 #ifdef CONFIG_DEBUG_FS
0133     .pin_dbg_show = uniphier_pctl_pin_dbg_show,
0134 #endif
0135     .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
0136     .dt_free_map = pinctrl_utils_free_map,
0137 };
0138 
0139 static const unsigned int uniphier_conf_drv_strengths_1bit[] = {4, 8};
0140 static const unsigned int uniphier_conf_drv_strengths_2bit[] = {8, 12, 16, 20};
0141 static const unsigned int uniphier_conf_drv_strengths_3bit[] = {4, 5, 7, 9, 11,
0142                                 12, 14, 16};
0143 static const unsigned int uniphier_conf_drv_strengths_fixed4[] = {4};
0144 static const unsigned int uniphier_conf_drv_strengths_fixed5[] = {5};
0145 static const unsigned int uniphier_conf_drv_strengths_fixed8[] = {8};
0146 
0147 static int uniphier_conf_get_drvctrl_data(struct pinctrl_dev *pctldev,
0148                       unsigned int pin, unsigned int *reg,
0149                       unsigned int *shift,
0150                       unsigned int *mask,
0151                       const unsigned int **strengths)
0152 {
0153     const struct pin_desc *desc = pin_desc_get(pctldev, pin);
0154     enum uniphier_pin_drv_type type =
0155                 uniphier_pin_get_drv_type(desc->drv_data);
0156     unsigned int base = 0;
0157     unsigned int stride = 0;
0158     unsigned int width = 0;
0159     unsigned int drvctrl;
0160 
0161     switch (type) {
0162     case UNIPHIER_PIN_DRV_1BIT:
0163         *strengths = uniphier_conf_drv_strengths_1bit;
0164         base = UNIPHIER_PINCTRL_DRVCTRL_BASE;
0165         stride = 1;
0166         width = 1;
0167         break;
0168     case UNIPHIER_PIN_DRV_2BIT:
0169         *strengths = uniphier_conf_drv_strengths_2bit;
0170         base = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
0171         stride = 2;
0172         width = 2;
0173         break;
0174     case UNIPHIER_PIN_DRV_3BIT:
0175         *strengths = uniphier_conf_drv_strengths_3bit;
0176         base = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
0177         stride = 4;
0178         width = 3;
0179         break;
0180     case UNIPHIER_PIN_DRV_FIXED4:
0181         *strengths = uniphier_conf_drv_strengths_fixed4;
0182         break;
0183     case UNIPHIER_PIN_DRV_FIXED5:
0184         *strengths = uniphier_conf_drv_strengths_fixed5;
0185         break;
0186     case UNIPHIER_PIN_DRV_FIXED8:
0187         *strengths = uniphier_conf_drv_strengths_fixed8;
0188         break;
0189     default:
0190         /* drive strength control is not supported for this pin */
0191         return -EINVAL;
0192     }
0193 
0194     drvctrl = uniphier_pin_get_drvctrl(desc->drv_data);
0195     drvctrl *= stride;
0196 
0197     *reg = base + drvctrl / 32 * 4;
0198     *shift = drvctrl % 32;
0199     *mask = (1U << width) - 1;
0200 
0201     return 0;
0202 }
0203 
0204 static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev,
0205                       unsigned int pin,
0206                       enum pin_config_param param)
0207 {
0208     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0209     const struct pin_desc *desc = pin_desc_get(pctldev, pin);
0210     enum uniphier_pin_pull_dir pull_dir =
0211                 uniphier_pin_get_pull_dir(desc->drv_data);
0212     unsigned int pupdctrl, reg, shift, val;
0213     unsigned int expected = 1;
0214     int ret;
0215 
0216     switch (param) {
0217     case PIN_CONFIG_BIAS_DISABLE:
0218         if (pull_dir == UNIPHIER_PIN_PULL_NONE)
0219             return 0;
0220         if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED ||
0221             pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED)
0222             return -EINVAL;
0223         expected = 0;
0224         break;
0225     case PIN_CONFIG_BIAS_PULL_UP:
0226         if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED)
0227             return 0;
0228         if (pull_dir != UNIPHIER_PIN_PULL_UP)
0229             return -EINVAL;
0230         break;
0231     case PIN_CONFIG_BIAS_PULL_DOWN:
0232         if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED)
0233             return 0;
0234         if (pull_dir != UNIPHIER_PIN_PULL_DOWN)
0235             return -EINVAL;
0236         break;
0237     default:
0238         BUG();
0239     }
0240 
0241     pupdctrl = uniphier_pin_get_pupdctrl(desc->drv_data);
0242 
0243     reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4;
0244     shift = pupdctrl % 32;
0245 
0246     ret = regmap_read(priv->regmap, reg, &val);
0247     if (ret)
0248         return ret;
0249 
0250     val = (val >> shift) & 1;
0251 
0252     return (val == expected) ? 0 : -EINVAL;
0253 }
0254 
0255 static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev,
0256                        unsigned int pin, u32 *strength)
0257 {
0258     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0259     unsigned int reg, shift, mask, val;
0260     const unsigned int *strengths;
0261     int ret;
0262 
0263     ret = uniphier_conf_get_drvctrl_data(pctldev, pin, &reg, &shift,
0264                          &mask, &strengths);
0265     if (ret)
0266         return ret;
0267 
0268     if (mask) {
0269         ret = regmap_read(priv->regmap, reg, &val);
0270         if (ret)
0271             return ret;
0272     } else {
0273         val = 0;
0274     }
0275 
0276     *strength = strengths[(val >> shift) & mask];
0277 
0278     return 0;
0279 }
0280 
0281 static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev,
0282                           unsigned int pin)
0283 {
0284     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0285     const struct pin_desc *desc = pin_desc_get(pctldev, pin);
0286     unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
0287     unsigned int reg, mask, val;
0288     int ret;
0289 
0290     if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
0291         /* This pin is always input-enabled. */
0292         return 0;
0293 
0294     if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
0295         iectrl = pin;
0296 
0297     reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4;
0298     mask = BIT(iectrl % 32);
0299 
0300     ret = regmap_read(priv->regmap, reg, &val);
0301     if (ret)
0302         return ret;
0303 
0304     return val & mask ? 0 : -EINVAL;
0305 }
0306 
0307 static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev,
0308                     unsigned pin,
0309                     unsigned long *configs)
0310 {
0311     enum pin_config_param param = pinconf_to_config_param(*configs);
0312     bool has_arg = false;
0313     u32 arg;
0314     int ret;
0315 
0316     switch (param) {
0317     case PIN_CONFIG_BIAS_DISABLE:
0318     case PIN_CONFIG_BIAS_PULL_UP:
0319     case PIN_CONFIG_BIAS_PULL_DOWN:
0320         ret = uniphier_conf_pin_bias_get(pctldev, pin, param);
0321         break;
0322     case PIN_CONFIG_DRIVE_STRENGTH:
0323         ret = uniphier_conf_pin_drive_get(pctldev, pin, &arg);
0324         has_arg = true;
0325         break;
0326     case PIN_CONFIG_INPUT_ENABLE:
0327         ret = uniphier_conf_pin_input_enable_get(pctldev, pin);
0328         break;
0329     default:
0330         /* unsupported parameter */
0331         ret = -EINVAL;
0332         break;
0333     }
0334 
0335     if (ret == 0 && has_arg)
0336         *configs = pinconf_to_config_packed(param, arg);
0337 
0338     return ret;
0339 }
0340 
0341 static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
0342                       unsigned int pin,
0343                       enum pin_config_param param, u32 arg)
0344 {
0345     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0346     const struct pin_desc *desc = pin_desc_get(pctldev, pin);
0347     enum uniphier_pin_pull_dir pull_dir =
0348                 uniphier_pin_get_pull_dir(desc->drv_data);
0349     unsigned int pupdctrl, reg, shift;
0350     unsigned int val = 1;
0351 
0352     switch (param) {
0353     case PIN_CONFIG_BIAS_DISABLE:
0354         if (pull_dir == UNIPHIER_PIN_PULL_NONE)
0355             return 0;
0356         if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED ||
0357             pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) {
0358             dev_err(pctldev->dev,
0359                 "can not disable pull register for pin %s\n",
0360                 desc->name);
0361             return -EINVAL;
0362         }
0363         val = 0;
0364         break;
0365     case PIN_CONFIG_BIAS_PULL_UP:
0366         if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED && arg != 0)
0367             return 0;
0368         if (pull_dir != UNIPHIER_PIN_PULL_UP) {
0369             dev_err(pctldev->dev,
0370                 "pull-up is unsupported for pin %s\n",
0371                 desc->name);
0372             return -EINVAL;
0373         }
0374         if (arg == 0) {
0375             dev_err(pctldev->dev, "pull-up can not be total\n");
0376             return -EINVAL;
0377         }
0378         break;
0379     case PIN_CONFIG_BIAS_PULL_DOWN:
0380         if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED && arg != 0)
0381             return 0;
0382         if (pull_dir != UNIPHIER_PIN_PULL_DOWN) {
0383             dev_err(pctldev->dev,
0384                 "pull-down is unsupported for pin %s\n",
0385                 desc->name);
0386             return -EINVAL;
0387         }
0388         if (arg == 0) {
0389             dev_err(pctldev->dev, "pull-down can not be total\n");
0390             return -EINVAL;
0391         }
0392         break;
0393     case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
0394         if (pull_dir == UNIPHIER_PIN_PULL_NONE) {
0395             dev_err(pctldev->dev,
0396                 "pull-up/down is unsupported for pin %s\n",
0397                 desc->name);
0398             return -EINVAL;
0399         }
0400 
0401         if (arg == 0)
0402             return 0; /* configuration ingored */
0403         break;
0404     default:
0405         BUG();
0406     }
0407 
0408     pupdctrl = uniphier_pin_get_pupdctrl(desc->drv_data);
0409 
0410     reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4;
0411     shift = pupdctrl % 32;
0412 
0413     return regmap_update_bits(priv->regmap, reg, 1 << shift, val << shift);
0414 }
0415 
0416 static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev,
0417                        unsigned int pin, u32 strength)
0418 {
0419     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0420     const struct pin_desc *desc = pin_desc_get(pctldev, pin);
0421     unsigned int reg, shift, mask, val;
0422     const unsigned int *strengths;
0423     int ret;
0424 
0425     ret = uniphier_conf_get_drvctrl_data(pctldev, pin, &reg, &shift,
0426                          &mask, &strengths);
0427     if (ret) {
0428         dev_err(pctldev->dev, "cannot set drive strength for pin %s\n",
0429             desc->name);
0430         return ret;
0431     }
0432 
0433     for (val = 0; val <= mask; val++) {
0434         if (strengths[val] > strength)
0435             break;
0436     }
0437 
0438     if (val == 0) {
0439         dev_err(pctldev->dev,
0440             "unsupported drive strength %u mA for pin %s\n",
0441             strength, desc->name);
0442         return -EINVAL;
0443     }
0444 
0445     if (!mask)
0446         return 0;
0447 
0448     val--;
0449 
0450     return regmap_update_bits(priv->regmap, reg,
0451                   mask << shift, val << shift);
0452 }
0453 
0454 static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev,
0455                       unsigned int pin, u32 enable)
0456 {
0457     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0458     const struct pin_desc *desc = pin_desc_get(pctldev, pin);
0459     unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
0460     unsigned int reg, mask;
0461 
0462     /*
0463      * Multiple pins share one input enable, per-pin disabling is
0464      * impossible.
0465      */
0466     if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) &&
0467         !enable)
0468         return -EINVAL;
0469 
0470     /* UNIPHIER_PIN_IECTRL_NONE means the pin is always input-enabled */
0471     if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
0472         return enable ? 0 : -EINVAL;
0473 
0474     if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
0475         iectrl = pin;
0476 
0477     reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4;
0478     mask = BIT(iectrl % 32);
0479 
0480     return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0);
0481 }
0482 
0483 static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev,
0484                     unsigned pin,
0485                     unsigned long *configs,
0486                     unsigned num_configs)
0487 {
0488     int i, ret;
0489 
0490     for (i = 0; i < num_configs; i++) {
0491         enum pin_config_param param =
0492                     pinconf_to_config_param(configs[i]);
0493         u32 arg = pinconf_to_config_argument(configs[i]);
0494 
0495         switch (param) {
0496         case PIN_CONFIG_BIAS_DISABLE:
0497         case PIN_CONFIG_BIAS_PULL_UP:
0498         case PIN_CONFIG_BIAS_PULL_DOWN:
0499         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
0500             ret = uniphier_conf_pin_bias_set(pctldev, pin,
0501                              param, arg);
0502             break;
0503         case PIN_CONFIG_DRIVE_STRENGTH:
0504             ret = uniphier_conf_pin_drive_set(pctldev, pin, arg);
0505             break;
0506         case PIN_CONFIG_INPUT_ENABLE:
0507             ret = uniphier_conf_pin_input_enable(pctldev, pin, arg);
0508             break;
0509         default:
0510             dev_err(pctldev->dev,
0511                 "unsupported configuration parameter %u\n",
0512                 param);
0513             return -EINVAL;
0514         }
0515 
0516         if (ret)
0517             return ret;
0518     }
0519 
0520     return 0;
0521 }
0522 
0523 static int uniphier_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
0524                           unsigned selector,
0525                           unsigned long *configs,
0526                           unsigned num_configs)
0527 {
0528     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0529     const unsigned *pins = priv->socdata->groups[selector].pins;
0530     unsigned num_pins = priv->socdata->groups[selector].num_pins;
0531     int i, ret;
0532 
0533     for (i = 0; i < num_pins; i++) {
0534         ret = uniphier_conf_pin_config_set(pctldev, pins[i],
0535                            configs, num_configs);
0536         if (ret)
0537             return ret;
0538     }
0539 
0540     return 0;
0541 }
0542 
0543 static const struct pinconf_ops uniphier_confops = {
0544     .is_generic = true,
0545     .pin_config_get = uniphier_conf_pin_config_get,
0546     .pin_config_set = uniphier_conf_pin_config_set,
0547     .pin_config_group_set = uniphier_conf_pin_config_group_set,
0548 };
0549 
0550 static int uniphier_pmx_get_functions_count(struct pinctrl_dev *pctldev)
0551 {
0552     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0553 
0554     return priv->socdata->functions_count;
0555 }
0556 
0557 static const char *uniphier_pmx_get_function_name(struct pinctrl_dev *pctldev,
0558                           unsigned selector)
0559 {
0560     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0561 
0562     return priv->socdata->functions[selector].name;
0563 }
0564 
0565 static int uniphier_pmx_get_function_groups(struct pinctrl_dev *pctldev,
0566                         unsigned selector,
0567                         const char * const **groups,
0568                         unsigned *num_groups)
0569 {
0570     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0571 
0572     *groups = priv->socdata->functions[selector].groups;
0573     *num_groups = priv->socdata->functions[selector].num_groups;
0574 
0575     return 0;
0576 }
0577 
0578 static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin,
0579                     int muxval)
0580 {
0581     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0582     unsigned int mux_bits, reg_stride, reg, reg_end, shift, mask;
0583     bool load_pinctrl;
0584     int ret;
0585 
0586     /* some pins need input-enabling */
0587     ret = uniphier_conf_pin_input_enable(pctldev, pin, 1);
0588     if (ret)
0589         return ret;
0590 
0591     if (muxval < 0)
0592         return 0;   /* dedicated pin; nothing to do for pin-mux */
0593 
0594     if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
0595         /*
0596          *  Mode     reg_offset     bit_position
0597          *  Normal    4 * n        shift+3:shift
0598          *  Debug     4 * n        shift+7:shift+4
0599          */
0600         mux_bits = 4;
0601         reg_stride = 8;
0602         load_pinctrl = true;
0603     } else {
0604         /*
0605          *  Mode     reg_offset     bit_position
0606          *  Normal    8 * n        shift+3:shift
0607          *  Debug     8 * n + 4    shift+3:shift
0608          */
0609         mux_bits = 8;
0610         reg_stride = 4;
0611         load_pinctrl = false;
0612     }
0613 
0614     reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
0615     reg_end = reg + reg_stride;
0616     shift = pin * mux_bits % 32;
0617     mask = (1U << mux_bits) - 1;
0618 
0619     /*
0620      * If reg_stride is greater than 4, the MSB of each pinsel shall be
0621      * stored in the offset+4.
0622      */
0623     for (; reg < reg_end; reg += 4) {
0624         ret = regmap_update_bits(priv->regmap, reg,
0625                      mask << shift, muxval << shift);
0626         if (ret)
0627             return ret;
0628         muxval >>= mux_bits;
0629     }
0630 
0631     if (load_pinctrl) {
0632         ret = regmap_write(priv->regmap,
0633                    UNIPHIER_PINCTRL_LOAD_PINMUX, 1);
0634         if (ret)
0635             return ret;
0636     }
0637 
0638     return 0;
0639 }
0640 
0641 static int uniphier_pmx_set_mux(struct pinctrl_dev *pctldev,
0642                 unsigned func_selector,
0643                 unsigned group_selector)
0644 {
0645     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0646     const struct uniphier_pinctrl_group *grp =
0647                     &priv->socdata->groups[group_selector];
0648     int i;
0649     int ret;
0650 
0651     for (i = 0; i < grp->num_pins; i++) {
0652         ret = uniphier_pmx_set_one_mux(pctldev, grp->pins[i],
0653                            grp->muxvals[i]);
0654         if (ret)
0655             return ret;
0656     }
0657 
0658     return 0;
0659 }
0660 
0661 static int uniphier_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
0662                         struct pinctrl_gpio_range *range,
0663                         unsigned offset)
0664 {
0665     struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0666     unsigned int gpio_offset;
0667     int muxval, i;
0668 
0669     if (range->pins) {
0670         for (i = 0; i < range->npins; i++)
0671             if (range->pins[i] == offset)
0672                 break;
0673 
0674         if (WARN_ON(i == range->npins))
0675             return -EINVAL;
0676 
0677         gpio_offset = i;
0678     } else {
0679         gpio_offset = offset - range->pin_base;
0680     }
0681 
0682     gpio_offset += range->id;
0683 
0684     muxval = priv->socdata->get_gpio_muxval(offset, gpio_offset);
0685 
0686     return uniphier_pmx_set_one_mux(pctldev, offset, muxval);
0687 }
0688 
0689 static const struct pinmux_ops uniphier_pmxops = {
0690     .get_functions_count = uniphier_pmx_get_functions_count,
0691     .get_function_name = uniphier_pmx_get_function_name,
0692     .get_function_groups = uniphier_pmx_get_function_groups,
0693     .set_mux = uniphier_pmx_set_mux,
0694     .gpio_request_enable = uniphier_pmx_gpio_request_enable,
0695     .strict = true,
0696 };
0697 
0698 #ifdef CONFIG_PM_SLEEP
0699 static int uniphier_pinctrl_suspend(struct device *dev)
0700 {
0701     struct uniphier_pinctrl_priv *priv = dev_get_drvdata(dev);
0702     struct uniphier_pinctrl_reg_region *r;
0703     int ret;
0704 
0705     list_for_each_entry(r, &priv->reg_regions, node) {
0706         ret = regmap_bulk_read(priv->regmap, r->base, r->vals,
0707                        r->nregs);
0708         if (ret)
0709             return ret;
0710     }
0711 
0712     return 0;
0713 }
0714 
0715 static int uniphier_pinctrl_resume(struct device *dev)
0716 {
0717     struct uniphier_pinctrl_priv *priv = dev_get_drvdata(dev);
0718     struct uniphier_pinctrl_reg_region *r;
0719     int ret;
0720 
0721     list_for_each_entry(r, &priv->reg_regions, node) {
0722         ret = regmap_bulk_write(priv->regmap, r->base, r->vals,
0723                     r->nregs);
0724         if (ret)
0725             return ret;
0726     }
0727 
0728     if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
0729         ret = regmap_write(priv->regmap,
0730                    UNIPHIER_PINCTRL_LOAD_PINMUX, 1);
0731         if (ret)
0732             return ret;
0733     }
0734 
0735     return 0;
0736 }
0737 
0738 static int uniphier_pinctrl_add_reg_region(struct device *dev,
0739                        struct uniphier_pinctrl_priv *priv,
0740                        unsigned int base,
0741                        unsigned int count,
0742                        unsigned int width)
0743 {
0744     struct uniphier_pinctrl_reg_region *region;
0745     unsigned int nregs;
0746 
0747     if (!count)
0748         return 0;
0749 
0750     nregs = DIV_ROUND_UP(count * width, 32);
0751 
0752     region = devm_kzalloc(dev, struct_size(region, vals, nregs),
0753                   GFP_KERNEL);
0754     if (!region)
0755         return -ENOMEM;
0756 
0757     region->base = base;
0758     region->nregs = nregs;
0759 
0760     list_add_tail(&region->node, &priv->reg_regions);
0761 
0762     return 0;
0763 }
0764 #endif
0765 
0766 static int uniphier_pinctrl_pm_init(struct device *dev,
0767                     struct uniphier_pinctrl_priv *priv)
0768 {
0769 #ifdef CONFIG_PM_SLEEP
0770     const struct uniphier_pinctrl_socdata *socdata = priv->socdata;
0771     unsigned int num_drvctrl = 0;
0772     unsigned int num_drv2ctrl = 0;
0773     unsigned int num_drv3ctrl = 0;
0774     unsigned int num_pupdctrl = 0;
0775     unsigned int num_iectrl = 0;
0776     unsigned int iectrl, drvctrl, pupdctrl;
0777     enum uniphier_pin_drv_type drv_type;
0778     enum uniphier_pin_pull_dir pull_dir;
0779     int i, ret;
0780 
0781     for (i = 0; i < socdata->npins; i++) {
0782         void *drv_data = socdata->pins[i].drv_data;
0783 
0784         drvctrl = uniphier_pin_get_drvctrl(drv_data);
0785         drv_type = uniphier_pin_get_drv_type(drv_data);
0786         pupdctrl = uniphier_pin_get_pupdctrl(drv_data);
0787         pull_dir = uniphier_pin_get_pull_dir(drv_data);
0788         iectrl = uniphier_pin_get_iectrl(drv_data);
0789 
0790         switch (drv_type) {
0791         case UNIPHIER_PIN_DRV_1BIT:
0792             num_drvctrl = max(num_drvctrl, drvctrl + 1);
0793             break;
0794         case UNIPHIER_PIN_DRV_2BIT:
0795             num_drv2ctrl = max(num_drv2ctrl, drvctrl + 1);
0796             break;
0797         case UNIPHIER_PIN_DRV_3BIT:
0798             num_drv3ctrl = max(num_drv3ctrl, drvctrl + 1);
0799             break;
0800         default:
0801             break;
0802         }
0803 
0804         if (pull_dir == UNIPHIER_PIN_PULL_UP ||
0805             pull_dir == UNIPHIER_PIN_PULL_DOWN)
0806             num_pupdctrl = max(num_pupdctrl, pupdctrl + 1);
0807 
0808         if (iectrl != UNIPHIER_PIN_IECTRL_NONE) {
0809             if (socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
0810                 iectrl = i;
0811             num_iectrl = max(num_iectrl, iectrl + 1);
0812         }
0813     }
0814 
0815     INIT_LIST_HEAD(&priv->reg_regions);
0816 
0817     ret = uniphier_pinctrl_add_reg_region(dev, priv,
0818                           UNIPHIER_PINCTRL_PINMUX_BASE,
0819                           socdata->npins, 8);
0820     if (ret)
0821         return ret;
0822 
0823     ret = uniphier_pinctrl_add_reg_region(dev, priv,
0824                           UNIPHIER_PINCTRL_DRVCTRL_BASE,
0825                           num_drvctrl, 1);
0826     if (ret)
0827         return ret;
0828 
0829     ret = uniphier_pinctrl_add_reg_region(dev, priv,
0830                           UNIPHIER_PINCTRL_DRV2CTRL_BASE,
0831                           num_drv2ctrl, 2);
0832     if (ret)
0833         return ret;
0834 
0835     ret = uniphier_pinctrl_add_reg_region(dev, priv,
0836                           UNIPHIER_PINCTRL_DRV3CTRL_BASE,
0837                           num_drv3ctrl, 3);
0838     if (ret)
0839         return ret;
0840 
0841     ret = uniphier_pinctrl_add_reg_region(dev, priv,
0842                           UNIPHIER_PINCTRL_PUPDCTRL_BASE,
0843                           num_pupdctrl, 1);
0844     if (ret)
0845         return ret;
0846 
0847     ret = uniphier_pinctrl_add_reg_region(dev, priv,
0848                           UNIPHIER_PINCTRL_IECTRL_BASE,
0849                           num_iectrl, 1);
0850     if (ret)
0851         return ret;
0852 #endif
0853     return 0;
0854 }
0855 
0856 const struct dev_pm_ops uniphier_pinctrl_pm_ops = {
0857     SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_pinctrl_suspend,
0858                      uniphier_pinctrl_resume)
0859 };
0860 
0861 int uniphier_pinctrl_probe(struct platform_device *pdev,
0862                const struct uniphier_pinctrl_socdata *socdata)
0863 {
0864     struct device *dev = &pdev->dev;
0865     struct uniphier_pinctrl_priv *priv;
0866     struct device_node *parent;
0867     int ret;
0868 
0869     if (!socdata ||
0870         !socdata->pins || !socdata->npins ||
0871         !socdata->groups || !socdata->groups_count ||
0872         !socdata->functions || !socdata->functions_count) {
0873         dev_err(dev, "pinctrl socdata lacks necessary members\n");
0874         return -EINVAL;
0875     }
0876 
0877     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0878     if (!priv)
0879         return -ENOMEM;
0880 
0881     parent = of_get_parent(dev->of_node);
0882     priv->regmap = syscon_node_to_regmap(parent);
0883     of_node_put(parent);
0884 
0885     if (IS_ERR(priv->regmap)) {
0886         dev_err(dev, "failed to get regmap\n");
0887         return PTR_ERR(priv->regmap);
0888     }
0889 
0890     priv->socdata = socdata;
0891     priv->pctldesc.name = dev->driver->name;
0892     priv->pctldesc.pins = socdata->pins;
0893     priv->pctldesc.npins = socdata->npins;
0894     priv->pctldesc.pctlops = &uniphier_pctlops;
0895     priv->pctldesc.pmxops = &uniphier_pmxops;
0896     priv->pctldesc.confops = &uniphier_confops;
0897     priv->pctldesc.owner = dev->driver->owner;
0898 
0899     ret = uniphier_pinctrl_pm_init(dev, priv);
0900     if (ret)
0901         return ret;
0902 
0903     priv->pctldev = devm_pinctrl_register(dev, &priv->pctldesc, priv);
0904     if (IS_ERR(priv->pctldev)) {
0905         dev_err(dev, "failed to register UniPhier pinctrl driver\n");
0906         return PTR_ERR(priv->pctldev);
0907     }
0908 
0909     platform_set_drvdata(pdev, priv);
0910 
0911     return 0;
0912 }
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