Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Support for configuration of IO Delay module found on Texas Instruments SoCs
0003  * such as DRA7
0004  *
0005  * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
0006  *
0007  * This file is licensed under the terms of the GNU General Public
0008  * License version 2. This program is licensed "as is" without any
0009  * warranty of any kind, whether express or implied.
0010  */
0011 
0012 #include <linux/err.h>
0013 #include <linux/init.h>
0014 #include <linux/io.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/pinctrl/pinconf.h>
0019 #include <linux/pinctrl/pinconf-generic.h>
0020 #include <linux/pinctrl/pinctrl.h>
0021 #include <linux/regmap.h>
0022 #include <linux/slab.h>
0023 
0024 #include "../core.h"
0025 #include "../devicetree.h"
0026 
0027 #define DRIVER_NAME "ti-iodelay"
0028 
0029 /**
0030  * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance
0031  * @signature_mask: CONFIG_REG mask for the signature bits (see TRM)
0032  * @signature_value: CONFIG_REG signature value to be written (see TRM)
0033  * @lock_mask: CONFIG_REG mask for the lock bits (see TRM)
0034  * @lock_val: CONFIG_REG lock value for the lock bits (see TRM)
0035  * @unlock_val:CONFIG_REG unlock value for the lock bits (see TRM)
0036  * @binary_data_coarse_mask: CONFIG_REG coarse mask (see TRM)
0037  * @binary_data_fine_mask: CONFIG_REG fine mask (see TRM)
0038  * @reg_refclk_offset: Refclk register offset
0039  * @refclk_period_mask: Refclk mask
0040  * @reg_coarse_offset: Coarse register configuration offset
0041  * @coarse_delay_count_mask: Coarse delay count mask
0042  * @coarse_ref_count_mask: Coarse ref count mask
0043  * @reg_fine_offset: Fine register configuration offset
0044  * @fine_delay_count_mask: Fine delay count mask
0045  * @fine_ref_count_mask: Fine ref count mask
0046  * @reg_global_lock_offset: Global iodelay module lock register offset
0047  * @global_lock_mask: Lock mask
0048  * @global_unlock_val: Unlock value
0049  * @global_lock_val: Lock value
0050  * @reg_start_offset: Offset to iodelay registers after the CONFIG_REG_0 to 8
0051  * @reg_nr_per_pin: Number of iodelay registers for each pin
0052  * @regmap_config: Regmap configuration for the IODelay region
0053  */
0054 struct ti_iodelay_reg_data {
0055     u32 signature_mask;
0056     u32 signature_value;
0057     u32 lock_mask;
0058     u32 lock_val;
0059     u32 unlock_val;
0060     u32 binary_data_coarse_mask;
0061     u32 binary_data_fine_mask;
0062 
0063     u32 reg_refclk_offset;
0064     u32 refclk_period_mask;
0065 
0066     u32 reg_coarse_offset;
0067     u32 coarse_delay_count_mask;
0068     u32 coarse_ref_count_mask;
0069 
0070     u32 reg_fine_offset;
0071     u32 fine_delay_count_mask;
0072     u32 fine_ref_count_mask;
0073 
0074     u32 reg_global_lock_offset;
0075     u32 global_lock_mask;
0076     u32 global_unlock_val;
0077     u32 global_lock_val;
0078 
0079     u32 reg_start_offset;
0080     u32 reg_nr_per_pin;
0081 
0082     struct regmap_config *regmap_config;
0083 };
0084 
0085 /**
0086  * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM)
0087  * @coarse_ref_count: Coarse reference count
0088  * @coarse_delay_count: Coarse delay count
0089  * @fine_ref_count: Fine reference count
0090  * @fine_delay_count: Fine Delay count
0091  * @ref_clk_period: Reference Clock period
0092  * @cdpe: Coarse delay parameter
0093  * @fdpe: Fine delay parameter
0094  */
0095 struct ti_iodelay_reg_values {
0096     u16 coarse_ref_count;
0097     u16 coarse_delay_count;
0098 
0099     u16 fine_ref_count;
0100     u16 fine_delay_count;
0101 
0102     u16 ref_clk_period;
0103 
0104     u32 cdpe;
0105     u32 fdpe;
0106 };
0107 
0108 /**
0109  * struct ti_iodelay_cfg - Description of each configuration parameters
0110  * @offset: Configuration register offset
0111  * @a_delay: Agnostic Delay (in ps)
0112  * @g_delay: Gnostic Delay (in ps)
0113  */
0114 struct ti_iodelay_cfg {
0115     u16 offset;
0116     u16 a_delay;
0117     u16 g_delay;
0118 };
0119 
0120 /**
0121  * struct ti_iodelay_pingroup - Structure that describes one group
0122  * @cfg: configuration array for the pin (from dt)
0123  * @ncfg: number of configuration values allocated
0124  * @config: pinconf "Config" - currently a dummy value
0125  */
0126 struct ti_iodelay_pingroup {
0127     struct ti_iodelay_cfg *cfg;
0128     int ncfg;
0129     unsigned long config;
0130 };
0131 
0132 /**
0133  * struct ti_iodelay_device - Represents information for a iodelay instance
0134  * @dev: Device pointer
0135  * @phys_base: Physical address base of the iodelay device
0136  * @reg_base: Virtual address base of the iodelay device
0137  * @regmap: Regmap for this iodelay instance
0138  * @pctl: Pinctrl device
0139  * @desc: pinctrl descriptor for pctl
0140  * @pa: pinctrl pin wise description
0141  * @reg_data: Register definition data for the IODelay instance
0142  * @reg_init_conf_values: Initial configuration values.
0143  */
0144 struct ti_iodelay_device {
0145     struct device *dev;
0146     unsigned long phys_base;
0147     void __iomem *reg_base;
0148     struct regmap *regmap;
0149 
0150     struct pinctrl_dev *pctl;
0151     struct pinctrl_desc desc;
0152     struct pinctrl_pin_desc *pa;
0153 
0154     const struct ti_iodelay_reg_data *reg_data;
0155     struct ti_iodelay_reg_values reg_init_conf_values;
0156 };
0157 
0158 /**
0159  * ti_iodelay_extract() - extract bits for a field
0160  * @val: Register value
0161  * @mask: Mask
0162  *
0163  * Return: extracted value which is appropriately shifted
0164  */
0165 static inline u32 ti_iodelay_extract(u32 val, u32 mask)
0166 {
0167     return (val & mask) >> __ffs(mask);
0168 }
0169 
0170 /**
0171  * ti_iodelay_compute_dpe() - Compute equation for delay parameter
0172  * @period: Period to use
0173  * @ref: Reference Count
0174  * @delay: Delay count
0175  * @delay_m: Delay multiplier
0176  *
0177  * Return: Computed delay parameter
0178  */
0179 static inline u32 ti_iodelay_compute_dpe(u16 period, u16 ref, u16 delay,
0180                      u16 delay_m)
0181 {
0182     u64 m, d;
0183 
0184     /* Handle overflow conditions */
0185     m = 10 * (u64)period * (u64)ref;
0186     d = 2 * (u64)delay * (u64)delay_m;
0187 
0188     /* Truncate result back to 32 bits */
0189     return div64_u64(m, d);
0190 }
0191 
0192 /**
0193  * ti_iodelay_pinconf_set() - Configure the pin configuration
0194  * @iod: iodelay device
0195  * @cfg: Configuration
0196  *
0197  * Update the configuration register as per TRM and lockup once done.
0198  * *IMPORTANT NOTE* SoC TRM does recommend doing iodelay programmation only
0199  * while in Isolation. But, then, isolation also implies that every pin
0200  * on the SoC (including DDR) will be isolated out. The only benefit being
0201  * a glitchless configuration, However, the intent of this driver is purely
0202  * to support a "glitchy" configuration where applicable.
0203  *
0204  * Return: 0 in case of success, else appropriate error value
0205  */
0206 static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod,
0207                   struct ti_iodelay_cfg *cfg)
0208 {
0209     const struct ti_iodelay_reg_data *reg = iod->reg_data;
0210     struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values;
0211     struct device *dev = iod->dev;
0212     u32 g_delay_coarse, g_delay_fine;
0213     u32 a_delay_coarse, a_delay_fine;
0214     u32 c_elements, f_elements;
0215     u32 total_delay;
0216     u32 reg_mask, reg_val, tmp_val;
0217     int r;
0218 
0219     /* NOTE: Truncation is expected in all division below */
0220     g_delay_coarse = cfg->g_delay / 920;
0221     g_delay_fine = ((cfg->g_delay % 920) * 10) / 60;
0222 
0223     a_delay_coarse = cfg->a_delay / ival->cdpe;
0224     a_delay_fine = ((cfg->a_delay % ival->cdpe) * 10) / ival->fdpe;
0225 
0226     c_elements = g_delay_coarse + a_delay_coarse;
0227     f_elements = (g_delay_fine + a_delay_fine) / 10;
0228 
0229     if (f_elements > 22) {
0230         total_delay = c_elements * ival->cdpe + f_elements * ival->fdpe;
0231         c_elements = total_delay / ival->cdpe;
0232         f_elements = (total_delay % ival->cdpe) / ival->fdpe;
0233     }
0234 
0235     reg_mask = reg->signature_mask;
0236     reg_val = reg->signature_value << __ffs(reg->signature_mask);
0237 
0238     reg_mask |= reg->binary_data_coarse_mask;
0239     tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask);
0240     if (tmp_val & ~reg->binary_data_coarse_mask) {
0241         dev_err(dev, "Masking overflow of coarse elements %08x\n",
0242             tmp_val);
0243         tmp_val &= reg->binary_data_coarse_mask;
0244     }
0245     reg_val |= tmp_val;
0246 
0247     reg_mask |= reg->binary_data_fine_mask;
0248     tmp_val = f_elements << __ffs(reg->binary_data_fine_mask);
0249     if (tmp_val & ~reg->binary_data_fine_mask) {
0250         dev_err(dev, "Masking overflow of fine elements %08x\n",
0251             tmp_val);
0252         tmp_val &= reg->binary_data_fine_mask;
0253     }
0254     reg_val |= tmp_val;
0255 
0256     /*
0257      * NOTE: we leave the iodelay values unlocked - this is to work around
0258      * situations such as those found with mmc mode change.
0259      * However, this leaves open any unwarranted changes to padconf register
0260      * impacting iodelay configuration. Use with care!
0261      */
0262     reg_mask |= reg->lock_mask;
0263     reg_val |= reg->unlock_val << __ffs(reg->lock_mask);
0264     r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val);
0265 
0266     dev_dbg(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n",
0267         cfg->offset, cfg->a_delay, cfg->g_delay, c_elements,
0268         f_elements, reg_val);
0269 
0270     return r;
0271 }
0272 
0273 /**
0274  * ti_iodelay_pinconf_init_dev() - Initialize IODelay device
0275  * @iod: iodelay device
0276  *
0277  * Unlocks the iodelay region, computes the common parameters
0278  *
0279  * Return: 0 in case of success, else appropriate error value
0280  */
0281 static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod)
0282 {
0283     const struct ti_iodelay_reg_data *reg = iod->reg_data;
0284     struct device *dev = iod->dev;
0285     struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values;
0286     u32 val;
0287     int r;
0288 
0289     /* unlock the iodelay region */
0290     r = regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,
0291                    reg->global_lock_mask, reg->global_unlock_val);
0292     if (r)
0293         return r;
0294 
0295     /* Read up Recalibration sequence done by bootloader */
0296     r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val);
0297     if (r)
0298         return r;
0299     ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask);
0300     dev_dbg(dev, "refclk_period=0x%04x\n", ival->ref_clk_period);
0301 
0302     r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val);
0303     if (r)
0304         return r;
0305     ival->coarse_ref_count =
0306         ti_iodelay_extract(val, reg->coarse_ref_count_mask);
0307     ival->coarse_delay_count =
0308         ti_iodelay_extract(val, reg->coarse_delay_count_mask);
0309     if (!ival->coarse_delay_count) {
0310         dev_err(dev, "Invalid Coarse delay count (0) (reg=0x%08x)\n",
0311             val);
0312         return -EINVAL;
0313     }
0314     ival->cdpe = ti_iodelay_compute_dpe(ival->ref_clk_period,
0315                         ival->coarse_ref_count,
0316                         ival->coarse_delay_count, 88);
0317     if (!ival->cdpe) {
0318         dev_err(dev, "Invalid cdpe computed params = %d %d %d\n",
0319             ival->ref_clk_period, ival->coarse_ref_count,
0320             ival->coarse_delay_count);
0321         return -EINVAL;
0322     }
0323     dev_dbg(iod->dev, "coarse: ref=0x%04x delay=0x%04x cdpe=0x%08x\n",
0324         ival->coarse_ref_count, ival->coarse_delay_count, ival->cdpe);
0325 
0326     r = regmap_read(iod->regmap, reg->reg_fine_offset, &val);
0327     if (r)
0328         return r;
0329     ival->fine_ref_count =
0330         ti_iodelay_extract(val, reg->fine_ref_count_mask);
0331     ival->fine_delay_count =
0332         ti_iodelay_extract(val, reg->fine_delay_count_mask);
0333     if (!ival->fine_delay_count) {
0334         dev_err(dev, "Invalid Fine delay count (0) (reg=0x%08x)\n",
0335             val);
0336         return -EINVAL;
0337     }
0338     ival->fdpe = ti_iodelay_compute_dpe(ival->ref_clk_period,
0339                         ival->fine_ref_count,
0340                         ival->fine_delay_count, 264);
0341     if (!ival->fdpe) {
0342         dev_err(dev, "Invalid fdpe(0) computed params = %d %d %d\n",
0343             ival->ref_clk_period, ival->fine_ref_count,
0344             ival->fine_delay_count);
0345         return -EINVAL;
0346     }
0347     dev_dbg(iod->dev, "fine: ref=0x%04x delay=0x%04x fdpe=0x%08x\n",
0348         ival->fine_ref_count, ival->fine_delay_count, ival->fdpe);
0349 
0350     return 0;
0351 }
0352 
0353 /**
0354  * ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device
0355  * @iod:    IODelay device
0356  *
0357  * Deinitialize the IODelay device (basically just lock the region back up.
0358  */
0359 static void ti_iodelay_pinconf_deinit_dev(struct ti_iodelay_device *iod)
0360 {
0361     const struct ti_iodelay_reg_data *reg = iod->reg_data;
0362 
0363     /* lock the iodelay region back again */
0364     regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,
0365                reg->global_lock_mask, reg->global_lock_val);
0366 }
0367 
0368 /**
0369  * ti_iodelay_get_pingroup() - Find the group mapped by a group selector
0370  * @iod: iodelay device
0371  * @selector: Group Selector
0372  *
0373  * Return: Corresponding group representing group selector
0374  */
0375 static struct ti_iodelay_pingroup *
0376 ti_iodelay_get_pingroup(struct ti_iodelay_device *iod, unsigned int selector)
0377 {
0378     struct group_desc *g;
0379 
0380     g = pinctrl_generic_get_group(iod->pctl, selector);
0381     if (!g) {
0382         dev_err(iod->dev, "%s could not find pingroup %i\n", __func__,
0383             selector);
0384 
0385         return NULL;
0386     }
0387 
0388     return g->data;
0389 }
0390 
0391 /**
0392  * ti_iodelay_offset_to_pin() - get a pin index based on the register offset
0393  * @iod: iodelay driver instance
0394  * @offset: register offset from the base
0395  */
0396 static int ti_iodelay_offset_to_pin(struct ti_iodelay_device *iod,
0397                     unsigned int offset)
0398 {
0399     const struct ti_iodelay_reg_data *r = iod->reg_data;
0400     unsigned int index;
0401 
0402     if (offset > r->regmap_config->max_register) {
0403         dev_err(iod->dev, "mux offset out of range: 0x%x (0x%x)\n",
0404             offset, r->regmap_config->max_register);
0405         return -EINVAL;
0406     }
0407 
0408     index = (offset - r->reg_start_offset) / r->regmap_config->reg_stride;
0409     index /= r->reg_nr_per_pin;
0410 
0411     return index;
0412 }
0413 
0414 /**
0415  * ti_iodelay_node_iterator() - Iterate iodelay node
0416  * @pctldev: Pin controller driver
0417  * @np: Device node
0418  * @pinctrl_spec: Parsed arguments from device tree
0419  * @pins: Array of pins in the pin group
0420  * @pin_index: Pin index in the pin array
0421  * @data: Pin controller driver specific data
0422  *
0423  */
0424 static int ti_iodelay_node_iterator(struct pinctrl_dev *pctldev,
0425                     struct device_node *np,
0426                     const struct of_phandle_args *pinctrl_spec,
0427                     int *pins, int pin_index, void *data)
0428 {
0429     struct ti_iodelay_device *iod;
0430     struct ti_iodelay_cfg *cfg = data;
0431     const struct ti_iodelay_reg_data *r;
0432     struct pinctrl_pin_desc *pd;
0433     int pin;
0434 
0435     iod = pinctrl_dev_get_drvdata(pctldev);
0436     if (!iod)
0437         return -EINVAL;
0438 
0439     r = iod->reg_data;
0440 
0441     if (pinctrl_spec->args_count < r->reg_nr_per_pin) {
0442         dev_err(iod->dev, "invalid args_count for spec: %i\n",
0443             pinctrl_spec->args_count);
0444 
0445         return -EINVAL;
0446     }
0447 
0448     /* Index plus two value cells */
0449     cfg[pin_index].offset = pinctrl_spec->args[0];
0450     cfg[pin_index].a_delay = pinctrl_spec->args[1] & 0xffff;
0451     cfg[pin_index].g_delay = pinctrl_spec->args[2] & 0xffff;
0452 
0453     pin = ti_iodelay_offset_to_pin(iod, cfg[pin_index].offset);
0454     if (pin < 0) {
0455         dev_err(iod->dev, "could not add functions for %pOFn %ux\n",
0456             np, cfg[pin_index].offset);
0457         return -ENODEV;
0458     }
0459     pins[pin_index] = pin;
0460 
0461     pd = &iod->pa[pin];
0462     pd->drv_data = &cfg[pin_index];
0463 
0464     dev_dbg(iod->dev, "%pOFn offset=%x a_delay = %d g_delay = %d\n",
0465         np, cfg[pin_index].offset, cfg[pin_index].a_delay,
0466         cfg[pin_index].g_delay);
0467 
0468     return 0;
0469 }
0470 
0471 /**
0472  * ti_iodelay_dt_node_to_map() - Map a device tree node to appropriate group
0473  * @pctldev: pinctrl device representing IODelay device
0474  * @np: Node Pointer (device tree)
0475  * @map: Pinctrl Map returned back to pinctrl framework
0476  * @num_maps: Number of maps (1)
0477  *
0478  * Maps the device tree description into a group of configuration parameters
0479  * for iodelay block entry.
0480  *
0481  * Return: 0 in case of success, else appropriate error value
0482  */
0483 static int ti_iodelay_dt_node_to_map(struct pinctrl_dev *pctldev,
0484                      struct device_node *np,
0485                      struct pinctrl_map **map,
0486                      unsigned int *num_maps)
0487 {
0488     struct ti_iodelay_device *iod;
0489     struct ti_iodelay_cfg *cfg;
0490     struct ti_iodelay_pingroup *g;
0491     const char *name = "pinctrl-pin-array";
0492     int rows, *pins, error = -EINVAL, i;
0493 
0494     iod = pinctrl_dev_get_drvdata(pctldev);
0495     if (!iod)
0496         return -EINVAL;
0497 
0498     rows = pinctrl_count_index_with_args(np, name);
0499     if (rows < 0)
0500         return rows;
0501 
0502     *map = devm_kzalloc(iod->dev, sizeof(**map), GFP_KERNEL);
0503     if (!*map)
0504         return -ENOMEM;
0505     *num_maps = 0;
0506 
0507     g = devm_kzalloc(iod->dev, sizeof(*g), GFP_KERNEL);
0508     if (!g) {
0509         error = -ENOMEM;
0510         goto free_map;
0511     }
0512 
0513     pins = devm_kcalloc(iod->dev, rows, sizeof(*pins), GFP_KERNEL);
0514     if (!pins) {
0515         error = -ENOMEM;
0516         goto free_group;
0517     }
0518 
0519     cfg = devm_kcalloc(iod->dev, rows, sizeof(*cfg), GFP_KERNEL);
0520     if (!cfg) {
0521         error = -ENOMEM;
0522         goto free_pins;
0523     }
0524 
0525     for (i = 0; i < rows; i++) {
0526         struct of_phandle_args pinctrl_spec;
0527 
0528         error = pinctrl_parse_index_with_args(np, name, i,
0529                               &pinctrl_spec);
0530         if (error)
0531             goto free_data;
0532 
0533         error = ti_iodelay_node_iterator(pctldev, np, &pinctrl_spec,
0534                          pins, i, cfg);
0535         if (error)
0536             goto free_data;
0537     }
0538 
0539     g->cfg = cfg;
0540     g->ncfg = i;
0541     g->config = PIN_CONFIG_END;
0542 
0543     error = pinctrl_generic_add_group(iod->pctl, np->name, pins, i, g);
0544     if (error < 0)
0545         goto free_data;
0546 
0547     (*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP;
0548     (*map)->data.configs.group_or_pin = np->name;
0549     (*map)->data.configs.configs = &g->config;
0550     (*map)->data.configs.num_configs = 1;
0551     *num_maps = 1;
0552 
0553     return 0;
0554 
0555 free_data:
0556     devm_kfree(iod->dev, cfg);
0557 free_pins:
0558     devm_kfree(iod->dev, pins);
0559 free_group:
0560     devm_kfree(iod->dev, g);
0561 free_map:
0562     devm_kfree(iod->dev, *map);
0563 
0564     return error;
0565 }
0566 
0567 /**
0568  * ti_iodelay_pinconf_group_get() - Get the group configuration
0569  * @pctldev: pinctrl device representing IODelay device
0570  * @selector: Group selector
0571  * @config: Configuration returned
0572  *
0573  * Return: The configuration if the group is valid, else returns -EINVAL
0574  */
0575 static int ti_iodelay_pinconf_group_get(struct pinctrl_dev *pctldev,
0576                     unsigned int selector,
0577                     unsigned long *config)
0578 {
0579     struct ti_iodelay_device *iod;
0580     struct ti_iodelay_pingroup *group;
0581 
0582     iod = pinctrl_dev_get_drvdata(pctldev);
0583     group = ti_iodelay_get_pingroup(iod, selector);
0584 
0585     if (!group)
0586         return -EINVAL;
0587 
0588     *config = group->config;
0589     return 0;
0590 }
0591 
0592 /**
0593  * ti_iodelay_pinconf_group_set() - Configure the groups of pins
0594  * @pctldev: pinctrl device representing IODelay device
0595  * @selector: Group selector
0596  * @configs: Configurations
0597  * @num_configs: Number of configurations
0598  *
0599  * Return: 0 if all went fine, else appropriate error value.
0600  */
0601 static int ti_iodelay_pinconf_group_set(struct pinctrl_dev *pctldev,
0602                     unsigned int selector,
0603                     unsigned long *configs,
0604                     unsigned int num_configs)
0605 {
0606     struct ti_iodelay_device *iod;
0607     struct device *dev;
0608     struct ti_iodelay_pingroup *group;
0609     int i;
0610 
0611     iod = pinctrl_dev_get_drvdata(pctldev);
0612     dev = iod->dev;
0613     group = ti_iodelay_get_pingroup(iod, selector);
0614 
0615     if (num_configs != 1) {
0616         dev_err(dev, "Unsupported number of configurations %d\n",
0617             num_configs);
0618         return -EINVAL;
0619     }
0620 
0621     if (*configs != PIN_CONFIG_END) {
0622         dev_err(dev, "Unsupported configuration\n");
0623         return -EINVAL;
0624     }
0625 
0626     for (i = 0; i < group->ncfg; i++) {
0627         if (ti_iodelay_pinconf_set(iod, &group->cfg[i]))
0628             return -ENOTSUPP;
0629     }
0630 
0631     return 0;
0632 }
0633 
0634 #ifdef CONFIG_DEBUG_FS
0635 /**
0636  * ti_iodelay_pin_to_offset() - get pin register offset based on the pin index
0637  * @iod: iodelay driver instance
0638  * @selector: Pin index
0639  */
0640 static unsigned int ti_iodelay_pin_to_offset(struct ti_iodelay_device *iod,
0641                          unsigned int selector)
0642 {
0643     const struct ti_iodelay_reg_data *r = iod->reg_data;
0644     unsigned int offset;
0645 
0646     offset = selector * r->regmap_config->reg_stride;
0647     offset *= r->reg_nr_per_pin;
0648     offset += r->reg_start_offset;
0649 
0650     return offset;
0651 }
0652 
0653 static void ti_iodelay_pin_dbg_show(struct pinctrl_dev *pctldev,
0654                     struct seq_file *s,
0655                     unsigned int pin)
0656 {
0657     struct ti_iodelay_device *iod;
0658     struct pinctrl_pin_desc *pd;
0659     struct ti_iodelay_cfg *cfg;
0660     const struct ti_iodelay_reg_data *r;
0661     unsigned long offset;
0662     u32 in, oen, out;
0663 
0664     iod = pinctrl_dev_get_drvdata(pctldev);
0665     r = iod->reg_data;
0666 
0667     offset = ti_iodelay_pin_to_offset(iod, pin);
0668     pd = &iod->pa[pin];
0669     cfg = pd->drv_data;
0670 
0671     regmap_read(iod->regmap, offset, &in);
0672     regmap_read(iod->regmap, offset + r->regmap_config->reg_stride, &oen);
0673     regmap_read(iod->regmap, offset + r->regmap_config->reg_stride * 2,
0674             &out);
0675 
0676     seq_printf(s, "%lx a: %i g: %i (%08x %08x %08x) %s ",
0677            iod->phys_base + offset,
0678            cfg ? cfg->a_delay : -1,
0679            cfg ? cfg->g_delay : -1,
0680            in, oen, out, DRIVER_NAME);
0681 }
0682 
0683 /**
0684  * ti_iodelay_pinconf_group_dbg_show() - show the group information
0685  * @pctldev: Show the group information
0686  * @s: Sequence file
0687  * @selector: Group selector
0688  *
0689  * Provide the configuration information of the selected group
0690  */
0691 static void ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
0692                           struct seq_file *s,
0693                           unsigned int selector)
0694 {
0695     struct ti_iodelay_device *iod;
0696     struct ti_iodelay_pingroup *group;
0697     int i;
0698 
0699     iod = pinctrl_dev_get_drvdata(pctldev);
0700     group = ti_iodelay_get_pingroup(iod, selector);
0701     if (!group)
0702         return;
0703 
0704     for (i = 0; i < group->ncfg; i++) {
0705         struct ti_iodelay_cfg *cfg;
0706         u32 reg = 0;
0707 
0708         cfg = &group->cfg[i];
0709         regmap_read(iod->regmap, cfg->offset, &reg);
0710         seq_printf(s, "\n\t0x%08x = 0x%08x (%3d, %3d)",
0711             cfg->offset, reg, cfg->a_delay, cfg->g_delay);
0712     }
0713 }
0714 #endif
0715 
0716 static const struct pinctrl_ops ti_iodelay_pinctrl_ops = {
0717     .get_groups_count = pinctrl_generic_get_group_count,
0718     .get_group_name = pinctrl_generic_get_group_name,
0719     .get_group_pins = pinctrl_generic_get_group_pins,
0720 #ifdef CONFIG_DEBUG_FS
0721     .pin_dbg_show = ti_iodelay_pin_dbg_show,
0722 #endif
0723     .dt_node_to_map = ti_iodelay_dt_node_to_map,
0724 };
0725 
0726 static const struct pinconf_ops ti_iodelay_pinctrl_pinconf_ops = {
0727     .pin_config_group_get = ti_iodelay_pinconf_group_get,
0728     .pin_config_group_set = ti_iodelay_pinconf_group_set,
0729 #ifdef CONFIG_DEBUG_FS
0730     .pin_config_group_dbg_show = ti_iodelay_pinconf_group_dbg_show,
0731 #endif
0732 };
0733 
0734 /**
0735  * ti_iodelay_alloc_pins() - Allocate structures needed for pins for iodelay
0736  * @dev: Device pointer
0737  * @iod: iodelay device
0738  * @base_phy: Base Physical Address
0739  *
0740  * Return: 0 if all went fine, else appropriate error value.
0741  */
0742 static int ti_iodelay_alloc_pins(struct device *dev,
0743                  struct ti_iodelay_device *iod, u32 base_phy)
0744 {
0745     const struct ti_iodelay_reg_data *r = iod->reg_data;
0746     struct pinctrl_pin_desc *pin;
0747     u32 phy_reg;
0748     int nr_pins, i;
0749 
0750     nr_pins = ti_iodelay_offset_to_pin(iod, r->regmap_config->max_register);
0751     dev_dbg(dev, "Allocating %i pins\n", nr_pins);
0752 
0753     iod->pa = devm_kcalloc(dev, nr_pins, sizeof(*iod->pa), GFP_KERNEL);
0754     if (!iod->pa)
0755         return -ENOMEM;
0756 
0757     iod->desc.pins = iod->pa;
0758     iod->desc.npins = nr_pins;
0759 
0760     phy_reg = r->reg_start_offset + base_phy;
0761 
0762     for (i = 0; i < nr_pins; i++, phy_reg += 4) {
0763         pin = &iod->pa[i];
0764         pin->number = i;
0765     }
0766 
0767     return 0;
0768 }
0769 
0770 static struct regmap_config dra7_iodelay_regmap_config = {
0771     .reg_bits = 32,
0772     .reg_stride = 4,
0773     .val_bits = 32,
0774     .max_register = 0xd1c,
0775 };
0776 
0777 static struct ti_iodelay_reg_data dra7_iodelay_data = {
0778     .signature_mask = 0x0003f000,
0779     .signature_value = 0x29,
0780     .lock_mask = 0x00000400,
0781     .lock_val = 1,
0782     .unlock_val = 0,
0783     .binary_data_coarse_mask = 0x000003e0,
0784     .binary_data_fine_mask = 0x0000001f,
0785 
0786     .reg_refclk_offset = 0x14,
0787     .refclk_period_mask = 0xffff,
0788 
0789     .reg_coarse_offset = 0x18,
0790     .coarse_delay_count_mask = 0xffff0000,
0791     .coarse_ref_count_mask = 0x0000ffff,
0792 
0793     .reg_fine_offset = 0x1C,
0794     .fine_delay_count_mask = 0xffff0000,
0795     .fine_ref_count_mask = 0x0000ffff,
0796 
0797     .reg_global_lock_offset = 0x2c,
0798     .global_lock_mask = 0x0000ffff,
0799     .global_unlock_val = 0x0000aaaa,
0800     .global_lock_val = 0x0000aaab,
0801 
0802     .reg_start_offset = 0x30,
0803     .reg_nr_per_pin = 3,
0804     .regmap_config = &dra7_iodelay_regmap_config,
0805 };
0806 
0807 static const struct of_device_id ti_iodelay_of_match[] = {
0808     {.compatible = "ti,dra7-iodelay", .data = &dra7_iodelay_data},
0809     { /* Hopefully no more.. */ },
0810 };
0811 MODULE_DEVICE_TABLE(of, ti_iodelay_of_match);
0812 
0813 /**
0814  * ti_iodelay_probe() - Standard probe
0815  * @pdev: platform device
0816  *
0817  * Return: 0 if all went fine, else appropriate error value.
0818  */
0819 static int ti_iodelay_probe(struct platform_device *pdev)
0820 {
0821     struct device *dev = &pdev->dev;
0822     struct device_node *np = of_node_get(dev->of_node);
0823     const struct of_device_id *match;
0824     struct resource *res;
0825     struct ti_iodelay_device *iod;
0826     int ret = 0;
0827 
0828     if (!np) {
0829         ret = -EINVAL;
0830         dev_err(dev, "No OF node\n");
0831         goto exit_out;
0832     }
0833 
0834     match = of_match_device(ti_iodelay_of_match, dev);
0835     if (!match) {
0836         ret = -EINVAL;
0837         dev_err(dev, "No DATA match\n");
0838         goto exit_out;
0839     }
0840 
0841     iod = devm_kzalloc(dev, sizeof(*iod), GFP_KERNEL);
0842     if (!iod) {
0843         ret = -ENOMEM;
0844         goto exit_out;
0845     }
0846     iod->dev = dev;
0847     iod->reg_data = match->data;
0848 
0849     /* So far We can assume there is only 1 bank of registers */
0850     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0851     if (!res) {
0852         dev_err(dev, "Missing MEM resource\n");
0853         ret = -ENODEV;
0854         goto exit_out;
0855     }
0856 
0857     iod->phys_base = res->start;
0858     iod->reg_base = devm_ioremap_resource(dev, res);
0859     if (IS_ERR(iod->reg_base)) {
0860         ret = PTR_ERR(iod->reg_base);
0861         goto exit_out;
0862     }
0863 
0864     iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base,
0865                         iod->reg_data->regmap_config);
0866     if (IS_ERR(iod->regmap)) {
0867         dev_err(dev, "Regmap MMIO init failed.\n");
0868         ret = PTR_ERR(iod->regmap);
0869         goto exit_out;
0870     }
0871 
0872     ret = ti_iodelay_pinconf_init_dev(iod);
0873     if (ret)
0874         goto exit_out;
0875 
0876     ret = ti_iodelay_alloc_pins(dev, iod, res->start);
0877     if (ret)
0878         goto exit_out;
0879 
0880     iod->desc.pctlops = &ti_iodelay_pinctrl_ops;
0881     /* no pinmux ops - we are pinconf */
0882     iod->desc.confops = &ti_iodelay_pinctrl_pinconf_ops;
0883     iod->desc.name = dev_name(dev);
0884     iod->desc.owner = THIS_MODULE;
0885 
0886     ret = pinctrl_register_and_init(&iod->desc, dev, iod, &iod->pctl);
0887     if (ret) {
0888         dev_err(dev, "Failed to register pinctrl\n");
0889         goto exit_out;
0890     }
0891 
0892     platform_set_drvdata(pdev, iod);
0893 
0894     return pinctrl_enable(iod->pctl);
0895 
0896 exit_out:
0897     of_node_put(np);
0898     return ret;
0899 }
0900 
0901 /**
0902  * ti_iodelay_remove() - standard remove
0903  * @pdev: platform device
0904  *
0905  * Return: 0 if all went fine, else appropriate error value.
0906  */
0907 static int ti_iodelay_remove(struct platform_device *pdev)
0908 {
0909     struct ti_iodelay_device *iod = platform_get_drvdata(pdev);
0910 
0911     if (!iod)
0912         return 0;
0913 
0914     if (iod->pctl)
0915         pinctrl_unregister(iod->pctl);
0916 
0917     ti_iodelay_pinconf_deinit_dev(iod);
0918 
0919     /* Expect other allocations to be freed by devm */
0920 
0921     return 0;
0922 }
0923 
0924 static struct platform_driver ti_iodelay_driver = {
0925     .probe = ti_iodelay_probe,
0926     .remove = ti_iodelay_remove,
0927     .driver = {
0928            .name = DRIVER_NAME,
0929            .of_match_table = ti_iodelay_of_match,
0930     },
0931 };
0932 module_platform_driver(ti_iodelay_driver);
0933 
0934 MODULE_AUTHOR("Texas Instruments, Inc.");
0935 MODULE_DESCRIPTION("Pinconf driver for TI's IO Delay module");
0936 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!