pinctrl/tegra/pinctrl-tegra.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Driver for the NVIDIA Tegra pinmux
0004  *
0005  * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
0006  */
0007
0008 #ifndef __PINMUX_TEGRA_H__
0009 #define __PINMUX_TEGRA_H__
0010
0011 struct tegra_pmx {
0012     struct device *dev;
0013     struct pinctrl_dev *pctl;
0014
0015     const struct tegra_pinctrl_soc_data *soc;
0016     const char **group_pins;
0017
0018     int nbanks;
0019     void __iomem **regs;
0020     u32 *backup_regs;
0021 };
0022
0023 enum tegra_pinconf_param {
0024     /* argument: tegra_pinconf_pull */
0025     TEGRA_PINCONF_PARAM_PULL,
0026     /* argument: tegra_pinconf_tristate */
0027     TEGRA_PINCONF_PARAM_TRISTATE,
0028     /* argument: Boolean */
0029     TEGRA_PINCONF_PARAM_ENABLE_INPUT,
0030     /* argument: Boolean */
0031     TEGRA_PINCONF_PARAM_OPEN_DRAIN,
0032     /* argument: Boolean */
0033     TEGRA_PINCONF_PARAM_LOCK,
0034     /* argument: Boolean */
0035     TEGRA_PINCONF_PARAM_IORESET,
0036     /* argument: Boolean */
0037     TEGRA_PINCONF_PARAM_RCV_SEL,
0038     /* argument: Boolean */
0039     TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
0040     /* argument: Boolean */
0041     TEGRA_PINCONF_PARAM_SCHMITT,
0042     /* argument: Boolean */
0043     TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
0044     /* argument: Integer, range is HW-dependant */
0045     TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
0046     /* argument: Integer, range is HW-dependant */
0047     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
0048     /* argument: Integer, range is HW-dependant */
0049     TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
0050     /* argument: Integer, range is HW-dependant */
0051     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
0052     /* argument: Integer, range is HW-dependant */
0053     TEGRA_PINCONF_PARAM_DRIVE_TYPE,
0054 };
0055
0056 enum tegra_pinconf_pull {
0057     TEGRA_PINCONFIG_PULL_NONE,
0058     TEGRA_PINCONFIG_PULL_DOWN,
0059     TEGRA_PINCONFIG_PULL_UP,
0060 };
0061
0062 enum tegra_pinconf_tristate {
0063     TEGRA_PINCONFIG_DRIVEN,
0064     TEGRA_PINCONFIG_TRISTATE,
0065 };
0066
0067 #define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
0068 #define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
0069 #define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
0070
0071 /**
0072  * struct tegra_function - Tegra pinctrl mux function
0073  * @name: The name of the function, exported to pinctrl core.
0074  * @groups: An array of pin groups that may select this function.
0075  * @ngroups: The number of entries in @groups.
0076  */
0077 struct tegra_function {
0078     const char *name;
0079     const char **groups;
0080     unsigned ngroups;
0081 };
0082
0083 /**
0084  * struct tegra_pingroup - Tegra pin group
0085  * @name        The name of the pin group.
0086  * @pins        An array of pin IDs included in this pin group.
0087  * @npins       The number of entries in @pins.
0088  * @funcs       The mux functions which can be muxed onto this group.
0089  * @mux_reg:        Mux register offset.
0090  *          This register contains the mux, einput, odrain, lock,
0091  *          ioreset, rcv_sel parameters.
0092  * @mux_bank:       Mux register bank.
0093  * @mux_bit:        Mux register bit.
0094  * @pupd_reg:       Pull-up/down register offset.
0095  * @pupd_bank:      Pull-up/down register bank.
0096  * @pupd_bit:       Pull-up/down register bit.
0097  * @tri_reg:        Tri-state register offset.
0098  * @tri_bank:       Tri-state register bank.
0099  * @tri_bit:        Tri-state register bit.
0100  * @einput_bit:     Enable-input register bit.
0101  * @odrain_bit:     Open-drain register bit.
0102  * @lock_bit:       Lock register bit.
0103  * @ioreset_bit:    IO reset register bit.
0104  * @rcv_sel_bit:    Receiver select bit.
0105  * @drv_reg:        Drive fields register offset.
0106  *          This register contains hsm, schmitt, lpmd, drvdn,
0107  *          drvup, slwr, slwf, and drvtype parameters.
0108  * @drv_bank:       Drive fields register bank.
0109  * @hsm_bit:        High Speed Mode register bit.
0110  * @sfsel_bit:      GPIO/SFIO selection register bit.
0111  * @schmitt_bit:    Schmitt register bit.
0112  * @lpmd_bit:       Low Power Mode register bit.
0113  * @drvdn_bit:      Drive Down register bit.
0114  * @drvdn_width:    Drive Down field width.
0115  * @drvup_bit:      Drive Up register bit.
0116  * @drvup_width:    Drive Up field width.
0117  * @slwr_bit:       Slew Rising register bit.
0118  * @slwr_width:     Slew Rising field width.
0119  * @slwf_bit:       Slew Falling register bit.
0120  * @slwf_width:     Slew Falling field width.
0121  * @lpdr_bit:       Base driver enabling bit.
0122  * @drvtype_bit:    Drive type register bit.
0123  * @parked_bitmask: Parked register mask. 0 if unsupported.
0124  *
0125  * -1 in a *_reg field means that feature is unsupported for this group.
0126  * *_bank and *_reg values are irrelevant when *_reg is -1.
0127  * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
0128  *
0129  * A representation of a group of pins (possibly just one pin) in the Tegra
0130  * pin controller. Each group allows some parameter or parameters to be
0131  * configured. The most common is mux function selection. Many others exist
0132  * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
0133  * certain groups may only support configuring certain parameters, hence
0134  * each parameter is optional.
0135  */
0136 struct tegra_pingroup {
0137     const char *name;
0138     const unsigned *pins;
0139     u8 npins;
0140     u8 funcs[4];
0141     s32 mux_reg;
0142     s32 pupd_reg;
0143     s32 tri_reg;
0144     s32 drv_reg;
0145     u32 mux_bank:2;
0146     u32 pupd_bank:2;
0147     u32 tri_bank:2;
0148     u32 drv_bank:2;
0149     s32 mux_bit:6;
0150     s32 pupd_bit:6;
0151     s32 tri_bit:6;
0152     s32 einput_bit:6;
0153     s32 odrain_bit:6;
0154     s32 lock_bit:6;
0155     s32 ioreset_bit:6;
0156     s32 rcv_sel_bit:6;
0157     s32 hsm_bit:6;
0158     s32 sfsel_bit:6;
0159     s32 schmitt_bit:6;
0160     s32 lpmd_bit:6;
0161     s32 drvdn_bit:6;
0162     s32 drvup_bit:6;
0163     s32 slwr_bit:6;
0164     s32 slwf_bit:6;
0165     s32 lpdr_bit:6;
0166     s32 drvtype_bit:6;
0167     s32 drvdn_width:6;
0168     s32 drvup_width:6;
0169     s32 slwr_width:6;
0170     s32 slwf_width:6;
0171     u32 parked_bitmask;
0172 };
0173
0174 /**
0175  * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
0176  * @ngpios: The number of GPIO pins the pin controller HW affects.
0177  * @pins:   An array describing all pins the pin controller affects.
0178  *      All pins which are also GPIOs must be listed first within the
0179  *      array, and be numbered identically to the GPIO controller's
0180  *      numbering.
0181  * @npins:  The numbmer of entries in @pins.
0182  * @functions:  An array describing all mux functions the SoC supports.
0183  * @nfunctions: The numbmer of entries in @functions.
0184  * @groups: An array describing all pin groups the pin SoC supports.
0185  * @ngroups:    The numbmer of entries in @groups.
0186  */
0187 struct tegra_pinctrl_soc_data {
0188     unsigned ngpios;
0189     const char *gpio_compatible;
0190     const struct pinctrl_pin_desc *pins;
0191     unsigned npins;
0192     struct tegra_function *functions;
0193     unsigned nfunctions;
0194     const struct tegra_pingroup *groups;
0195     unsigned ngroups;
0196     bool hsm_in_mux;
0197     bool schmitt_in_mux;
0198     bool drvtype_in_mux;
0199     bool sfsel_in_mux;
0200 };
0201
0202 extern const struct dev_pm_ops tegra_pinctrl_pm;
0203
0204 int tegra_pinctrl_probe(struct platform_device *pdev,
0205             const struct tegra_pinctrl_soc_data *soc_data);
0206 #endif